VLSI Design by K.lal Kishore

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K. Lai Kishore V s.v . Prabhakar

VLSI DESIGN

VLSI DESIGN

K. LAL KISHORE M T ech , Ph.D. (I.I.Sc), MIEEE, FIETE, FIE, MISTE, M ISHM Professor in ECE and RECTOR, ' Jaw aharlal Nehru Technological University, H yderabad

V.

s. V. PRABHAKAR B E., M .S. (Ph.D.) P ro fe s s o r a n d H.O.D. D e p a r tm e n t o f ECE,

L e n d i In s titu te o f E n g in e e rin g a n d T e c h n o lo g y J o n n a d a , V iz ia n a g a r a m (Dist.)

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I.K. International Publishing House Pvt. Ltd. New Delhi

• Bangalore

Published by I.K. International Publishing House Pvt. Ltd. S-25, Green Park Extension, Uphaar Cinema Market New Delhi-110 016 (India) E-mail : [email protected] Website : www.ikbooks.com

ISBN 978-93-80026-67-1 © 2009 I.K. International Publishing House Pvt. Ltd.

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9 8 7 6 5 4 3

Reprint 2011

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or any means: electronic, mechanical, photocopying, recording or otherwise, without the prior wntten permission from the publisher. Published by Krishan Makhijani for I.K. International Publishing House Pvt Ltd. S-25 Green Park Extension, Uphaar Cinema M^ket, New Delhi-110 016 and Printed by Rddia Prmters Pvt Ltd., Okhla Industrial Area, Phase n, New Delhi-110 020.

This book is dedicated to The Omnipotent and Omnipresent Goddess

SRI VANAMALAMMA

Preface

The widespread acceptance of sophisticated electronic devices in our daily life and the grow­ ing challenges of a more technically oriented future have created an unprecedented demand for very large-scale integration, or VLSI, circuits. The art of VLSI cừcuit design is dynamic; it evolves constantly with advances in process technology and innovations in the electronic design automation (EDA) industry. The objective of this book is to give the reader the oppor­ tunity to see the whole picture of how a complex chip is developed, from concept to silicon through various stages. It aims at providing the students with understanding the basic principles of VLSI devices as well as circuits. Another important aspect of this book is a brief but comprehensive discussion of device fabrication technology. The perfonnance of modem day devices depends, to a great extent, on technological advances. This cannot be appreciated without an exposure to the vari­ ous processing steps and so, it has been included in this book. Chapter 1 discusses the basic processing technologies used in the semiconductor foundry. The reader gets clear-cut idea about various complicated processes from oxidation to packaging in detail. The industry standards like RCA cleaning were discussed to give a confidential feel to the reader. Chapter 2 discusses about MOSFET and its operation. The importance of threshold voltage is reflected in this chapter. As inverter is the basic circuit, the characteristics of nMOS inverter as well as CMOS inverter were discussed in detail. BiCMOS family is introduced and its inverter cừcuits are given. Chapter 3 is the heart of the entừe book. It discusses about design flow of VLSI. It starts with requirements and ends with tapeout. Each step of the flow is explained clearly with relevant e x a m p le s and pictures. Various verification and validation techniques like static timing analy­ sis design rule checks are presented in the text.

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Preface

Chapter 4 focuses on concepts of VLSI cữcuits. The reader is inữoduced to the concqits of stick diagrams and theừ importance in design of the cừcuits. Layouts of various basic gates are given discussing lambda based rules. The major goals of VLSI are low power and less sili­ con area consumption. CMOS scaling is done to achieve the goal of less area. Various scaling parameters and theữ limitations are presented in detail. Chapter 5 describes various CMOS complex logic gates and their working. Propagation delays are very important in digital circuits. The concept of sheet resistance and unit capacitance which influence the delay of the logic gate are illustrated with solved examples. Rise time and fall time calculations are demonstrated. In Chapter 6 , PLA, PAL designs are discussed. FPGA based design consumes design tune and complexity. Hence, a thorough explanation about FPGA basics is done. Standard cell-based approach is also dealt witfi in this chapter. In Chapter 7, VLSI subsystem design is discussed. Various arithmetic components like adders, multipliers, shifters and optimization techniques for reduction of delay are given. Memory ele­ ments like SRAM, DRAM will give reader a thorough insight into the system design. Chapter 8 deals wiứi various simulation models and detailed explanation about synthesis of digital systems. VHDL synthesis is focussed. Details like timing report, area report, consừaints are also discussed. Chapter 9 describes testing of digital cữcuits. Various levels of testing life system level test­ ing, PCB based testing are explained. Chapter 10 introduces ứie concept of System-on-Chip and discusses the role of embedded processor. Power network and clock network are explained. Topics like why VLSI is so chal­ lenging clears many doubts raised of by the readers. Chapter 11 focuses on low power VLSI cữcuits and various solutions for low power consumption. Chapter 12 deals with nano electronic devices like quantum dots, single electron ữansistor, cuid carbon nanotubes, etc. which are future electronic devices. A number of “HELP DESK” questions are included in the book along with the answers. These questions are mostly “real” ones, that is, we have actually faced these questions in the class­ room. So, we think that these are genuine doubts which students have while studying VLSI for the first time and tiherefore detailed discussion. Solved problems and questions given at the end of each chapter are thought provoking. Objective type questions help the students who attend various competitive exams. The target readers of this book are AMIETE, undergraduate as well as postgraduate students of all universities in India. T he authors

Acknowledgements

I thank my wife Gayatri and daughters Kalpana and Pratyusha for their support throughout the preparation of this book. K. Lai Kishore I am thankful to management committee of Lendi Institute of Engineering and Technology, Sri P. Madhusudana Rao gam, Sri p. Srinivasa Rao garu, Sri K. Siva Rama Krishna garu for providing an excellent environment to work with all facilities and academic freedom. Heartiiil thanks to Principal, Prof. v.v. Rama Reddy gam. I am thankful to the Chairman of Avanthi Group of Colleges, Sri M. Srinivasa Rao gam, M.L.A. (Bheemili) for his encouragement. I am thankful to my parents Mr. and Mrs. V. Ram Mohan Rao, in-laws Mr. and Mrs. T.GB. Shankar Rao, for their constant support for what I am today. I thank my wife Sailaja for her help in typing, proofreading and suggestions during the work. Special thanks to my sweet son Sri Ram for his love and affection.

v.s.v. Prabhakar

Contents

Preface__________________________________________________________ _______vii

Acknowledgements................................— ..— ........................— -------------------------------—............—........ CHAPTER 1

VLSI FABRICATION TECHNOLOGY.................................................................................. 1

1.1

INTRO D UCTIO N - A BRIEF HISTORY O F VLSI................................................................................... 1

1.2

PRO CESS T EC H N O LO G IES USED IN TO DAY'S DESIGN E N V IR O N M E N T ........................................ 3

1.3

M A JO R PROCESS STEPS IN FABRICATING M O S F E T ....................................................................... 4

1.4

W AFER M A N U F A C T U R E ..................................................^.................................................................5

1.4.1 1.4.2 1.4.3

Silicon Refinement.........................................................................................................................5 Crystal G row th...............................................................................................................................6 Wafer Formation.............................................................................................................................8

1.5

W AFER C L E A N IN G .............................................................................................................................. 9

1.6

D O PING A N D IM P U R IT IE S ............................................................................................................... 9

1.6.1 1.6.2 1 6.3 17

G RO W TH A N D DEPOSITION OF DIELECTRIC FILM S......................................................................16 1 .7.1

17 2 1.8

Epitaxy.............................................................................................................................................9 Diffusion........................................................................................................................................ 11 Ion Implantation........................................................................................................................... 14

Thermal Oxidation........................................................................................................................16 Deposition o f Dielecừic Films................................................................................................... 20

M ASKIN G A N D L IT H O G R A P H Y .........................................................................................................21

1.8.1 1

1.8.3 1 .8.4 1.8.5

Photomask..................................................................................................................................... 22 82 Procedure for Pattern Transfer.................................................................................23 Contact Photolithography...........................................................................................................24 Proximity Photolithography........................................................................................................25 Projection Lithography................................................. .............................................................. 25

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Contents

1.8.6 1.8.7 1.9

ETCHIN G _____________________________________________________________________ —

1.9.1 1.9 2 1.10 1.11

Elec&mi Beam Lidiografdiy----------------------------------------------------------------------- 27 lon-Beam Lidiogra{Ay___________________________________________________ 27 -------27

Wet Chemical Etching--------------------------------------------------------------------------------------- 28 Dry Etching..........................................................................................................—.....- ........... 28

M ETALLIZATION A N D IN T ERCO N N ECTS------------------------------------------------------------------------ 29 EN CAPSULATIO N (PACK AG IN G )________________________________________________________ 31

1.11.1

Types o f Packages..........................................................................................................................35

1.12

DESIGN FOR TESTABILITY______________________________________________________________ 36

1.13

FABRICATION O F PASSIVE C O M P O N E N T S ---------------------------------------------------------------_ _ _ 3 7

1.13.1 Resistors.......................................................................................................................................... 37 1.13.2 C apacitors...................................................................................................................................... 39 1.14

PROCESS FLOW FOR SELF-ALIG N ED n M O S F E T ---------------------------------------------------------------40

1.15

PROCESS FLOW FOR C M O S FABRICATION-TW IN TU B PR O C E SS----------------------------------------41

CHAPTER 2 2.1

BASIC ELECTRICAL PROPERTIES OF MOS, BiCMOS DEVICES---------------------------45

INTRODUCTION O F M O S FE T___________________________________________________________ 45

2.1.1 2.1.2 2.1.3 2.1.4 2.1.5

Physical Sơucture of a MOSFET (The Enhaiicenieiit Mode).................................................. 46 UndCTStanding Enhancement Mode MOSFET Opoadon: A Descriptive Approach.............47 Understanding the E>epletion Mode MOSFET Operation.......................................................... 55 Leakage Cuirent Problem in ứie MOSFET.................................................................................58 A.C. Properties: Transconductance, Output Conductance and Figure o f Merit o f a MOSFET.............................................................................................60 2.1.6 Pass Transistor Lx)gic.....................................................................................................................61 2.1.7 nMOS Inverter......1 ...................................................................................................................... 62 2.1.8 CMOS Technology.........................................................................................................................65 2.1.9 BiCMOS Inverters......................................................................................................................... 69 2.1.10 Latchup m CM OS..........................................................................................................................72

CHAPTER 3

VLSI DESIGN FLOW ----------------------------------------------------------------------------79

3.1

INTRO D UCTIO N _______________________________________________________________________ 79

32

VLSI CIRCUIT DESIGN PR O C E S S________________________________________________________ 80

33

DESIGN F L O W ________________________________________________________________________ 82

3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8

Concept and Maiket Research......................................................................................................82 Architecture Specifications and Design Consoaints...................................................................82 HDL Capture and RTL Codina..................................................................................................... 83 Logic Simulation............................................................................................................................86 Logic S>-ntbesis.............................................................................................................................. 88 L o ãc Optimization.........................................................................................................................89 Fonnal Verification.........................................................................................................................90 Static Tunins Analj-sis (S T .\)....................................................................................................... 91

Contents 3.3.9 3.3.10 3.3.11 3.3.12 3.3.13 3.3.14 3.3.15

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Floor Planning.............................................. ................................................................................... Placement......................................................................................................................................94 Routing............................................................................................... ................ ........................ 96 Design Verification Tools:Layout Versus Schematic (LVS).................................................... 98 Design Rule Oieck (DRC)......................................................................................................... 99 Tapeout......................................................................................................................................... 99 Yield............................................................................................................................................ 100

3.4

THE DESIGN INTEGRITY ISSU ES..................................................................................................... 101

3.5

THE ROLE OF EDA TO O LS IN 1C DESIGN............... ....................................................................... 102

3.6

DESIGN STRATEGIES...................................................................................................................... 105

3.6.1 3.6.2 3.6.3 3.6.4 CHA'PTER 4

Hierarchy....................................................................................................................................105 Regularity.................................................................................................................................. 105 M odularity................................................................................................................................. 106 L o c a lity .!.. ...................................................... . . ..............106

VLSI CIRCUIT DESIGN PROCESS................................................................................ 109

4.1

M O S LA Y E R S ....................................................................................................................................109

4.2

STICK D IA G R A M S ............................................................................................................................109

4.2.1 4.2.2 4.3 4.4

nMOS Design Style.................................................................................................................. 112 CMOS D e s i^ Style..................................................................................................................113

LA YO U T ............................................................................................................................................ 115 DESIGN RULES ............................................................................................................................... 117

4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6

Design Rule Checking Software............................................................................................. 117 Design Rules for N-well ......................................................................................................... 118 Design Rules for n-Dififusion and p-Diflusion.......................................................................118 Design Rules for Wữes (ConductionPaths)............................................................................119 Basic Construction Rules for Transistor................................................................................. 119 Design Rules for Contact C uts................................................................................................121

4.5

D O U BLE M ETAL M O S PROCESS R U LES........................................................................................ 124

4.6

C M O S L A M B D A BASED RULES...................................................................................................... 124

4.7

DESIGN RULES FOR M ETAL 3 ........................................................................................................ 124

4.8

INTRODUCTION: C M O S SC A LIN G ................................................................................................. 125

4.9

SCALING PARAM ETERS.................................................................................................................. 126

4.10 DIFFICULTIES ARISING D UE TO M O SFET SC A LIN G ..................................................................... 129

4.10.1 4.10.2 4.10.3 4.10.4 4.10.5 4.10.6 4.10.7

Higher Sub-Threshold Conduction......................................................................................... 129 Increased Gate-Oxide Leakage................................................................................................130 Increased Junction Leakage..................................................................................................... 1 3 0 Lower Transconductance...........................................................................................................1 3 1 Interconnect Capacitance..................................................................................................... 1 3 1 Heat Production......................................................................................................................... 1 3 2 Limits o f Interconnect and Contact Resistance............................................................. 134

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Contents

CHAPTERS 5.1

5.2

GATE LEVEL DESIGN________________________ _______ _______ ________ 137

C M O S LOGIC GATES A N D OTHER C O M P LE X G A T E S -------------------------------------------------------- 137

5.1.1

CMOS Static Logic............................................................................................ 137

5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7

Transmission Gate Logic................................................. ............................... ........................... 140 Tri-State Gates.................................................................. ...........................................................141 Pass Transistor Logic.................................................................................................................. 143 Dynamic CMOS L ogic...............................................................................................................144 Domino CMOS L o g ic ................................................................................................. .............. 146 Other CMOS Logic Families.....................................................................................................147

BASIC CIRCUIT C O N C E P T S ...................................................................................................... ......148

5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3

DRIVING LARGE CAPACITIVE L O A D S ......................................................................... - ...... ....... 157

5.3.1 532 5.3.3 5.4

Cascaded Inverters as Drivers.................................................................................................... 157 Super Buffers..................................................................................... .......................................... 159 BiCMOS Drivers.......................................................................................................................... 161

PROPAGATION D ELAYS...................................................................................................................163

5.4.1 5.4.2 5.4.3 5.5

Sheet Resistance (/ỉs).................................................................................................................. 148 Sheet Resistance Concept Applied to MOS Capacitors and Inverters..................................149 Calculation o f ON Resistance of a Simple Inverter................................................................ 150 Area Capacitances o f Layers......................................................................................................151 Standard Unit o f Capacitance □ Cg........................................................................................... 152 The Delay Unit X..............................° .................................... ......................................................152 Inverter Delays ............................................................................................................................153 A More Formal Estimation o f CMOS Inverter D elay............................................................ 155

Cascaded Pass Transistors........................................................................................................... 163 Design o f Long Polysilicon W ữes............................................................................................. 164 Wiring Capacitances............ ....................................................................................................... 165

CHOICE OF LAYERS........................................- .................................. .......................................... 166

CHAPTER 6

SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN--------------------------------------- 171

6.1

PR O G R A M M IN G LOGIC D EV IC ES................................................................................... ................. 171

6.2

PR O G R A M M A B LE LOGIC ARRAYS (PLA )......................................................................................... 173

6.2.1 6.2.2 6.2.3

Architecture o f PLA.....................................................................................................................174 Advantages and Disadvantages o f PLAs...................................................................................176 Applications of PLAs.................................................................................................................. 178

6.3

PR O G R A M M A B LE ARRAY LO G iC (PAL)............................................................................................178

6.4

IMPLEMENTATION A PPR O A CH ES IN VLSI D ESIG N ........................................................................ 179

6.4.1 6.4.2 6.4.3 6.5

Custom or Full Custom Design .................................................................................................179 Semicustom Design......................................................................................................................179 Gate A ưays............................................................................. ......................................................180

C O M PLE X P R O G R A M M A B LE LOGIC DEVICES (C P LD s)................................................................. 182

Contents 6.5.1 6.5.2 6.6

CPLD Architectures...................... ............................................................................................ 182 Architecture Issues.....................................................................................................................184

ASIC Library or Standard Cell Library..................................................................................189

FIE LD -PR O G R A M M A B LE GATE ARRAY (F PG A )................................... ......................................... 190

6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.7.7 6.8

XV

STAN D A RD C E L L S ............................................................................................................................ 185

6.6.1 6.7

a

FPGA Architecture.....................................................................................................................190 Configurable Logic Blocks (CLBs)..........................................................................................193 FPGA Routing Techniques................................................ ........................................................196 Switching Methodologies.......................................................................................................... 197 Configurable I/O B locks........................................................................................................... 199 Features o f FPG A s.................................................................................................................... 200 Applications................................................................................................................................ 201

DESIGN ISSU ES.................................................................................................................. ............201

CHAPTER 7

SUBSYSTEM DESIGN

205

o 7.1

DATAPATHS IN DIGITAL PROCESSOR ARCHITECTURES.......... *................................................ 205

7.2

TH E A D D E R .....................................................................................................................................206

7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.3

THE M U LTIPLIER...............................................................................................................................221

7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.4

Partial-Product Generation........................................................................................................ 221 Partial-Product Accumulation............................................................................. .....................224 The Array M ultiplier.................................... ............................................................................ 224 Carry-Save Multiplier............................................................................................................... 225 The Tree M ultiplier.............................................................. .................................................... 226 Final Addition.............................................................................. ............................ ..................228

THE SHIFTER...................................................................................................................................^229

7.4.1 7.4.2 7.5

Foiư Bit Ripple C any A dder................................................................................................... 207 Static Adder Circuit; Cữcuit Design Considerations ............................................................209 Transmission-Gate-Based Adder...............................................................................................211 Manchester Carry-Cham A dder................................................................................................211 Carry Bypass Adder or CarrySkip A d d er...............................................................................214 The Linear Carry-Select Adder........................................................................................... ....217 The Carry-Lookahead Adder........................................................... .........................................219

Baưel Shifter............................................................................................................................ ^230 Logarithmic Shifter................................................................................... ............ ...................231

M E M O R Y E LE M E N T S....................................................................................................................... 232

7.5.1 7

SRAM ............................................... ..................................................................................... ...232 5.2 D R A M ......................................................................................................... .„239

CHAPTER 8 VHDL MODELLING OF DIGITAL SYSTEMS----------------------------------------------- 247 8.1

SIM U L/V riO N .....................................................................................................................................247

8.1.1 8.1.2

Oblivious Simulation......::......................................................................................................... 249 Event-Driven Simulation....................................................................................................... 250

XYÌ

o 8.2 8.3

Contents LOGIC SYN TH ESIS.................................................................................... ...................................... 251 INSIDE A LOGIC SYNTHESIZER......................................................................................... .............252

8.3.1 8.3.2 8.3.3 8.4

C O N ST R A IN T S.................................................................................................................................257

8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.5 8.6

Translation...................................... ........................................... .............................................. 252 Logic Minimization and Logic Optimization..................... ................................................. 253 Mapping to Gates or Technology-Decomposition...............................................................255

Timing Constraints.............................................................................................. .................... 258 Clock Constraints.................................................................... ................................................ 258 Attributes...................................................................................................................................258 Load........................................................................................................................................... 259 D rive..........................................................................................................................................259 Anival Tim e............................................................................................................................. 260

T E C H N O LO G Y LIBRARIES..........................................................................................................». .2 60 V H D L A N D LOGIC SYNTHESIS....................................................................................................... 262

8.6.1 8.6.2

Area R eport...............................................................................................................................263 Timing Report................................................... ........................................................................264

8.7

FU N C T IO N A L GATE-LEVEL VERIFICATION....................................................................................265

8.8

PLA CE A N D R O U T E ........................................................................................................................ 266

8.9

POST LAYO U T TIMING SIM U LATIO N ............................................................................................. 267

8.10

STATIC T IM IN G ................................................................................................................................ 268

8.11

M A JO R NETLIST FORMATS FOR DESIGN REPRESENTATION........................................................268

8.12

V H D L SY N T H ESIS-PR O G R A M M IN G A P P R O A C H ......................................................................... 269

8.12.1 8.12.2 8.12.3 8.12 4 8 8.12.6 8.12.7 8.12.8 8.12.9 8.13

Initialization and Reset.............................................................................................................269 Combinational Logic Syntìiesis in VHDL............................................................................. 269 Multiplexers in V H D L.............................................................................................................270 Decoders in VHDL................................................................................................................... 271 12 5 Adders in VHDL...................................................................................................... 273 Sequential Logic m VHDL..................................................................................................... 274 Shift Registers and Clocking in VHDL..................................................................................275 Adders and Aritìunetic Functions...........................................................................................276 Adder/Subtracter and Don’t Cares..........................................................................................277

A LOGIC-SYNTHESIS E X A M P L E ......................................................................................................278

CHAPTER 9

CMOS TESTING............................................................................................................ 285

9.1

NEED FOR TESTING— M OTIVATIO N ...............................................................................................285

9.2

TESTING DURING THE VLSI LIFE CYCLE.........................................................................................286

9.3

TEST PRINCIPLES............................................................................................................................. 290

9.3.1 9.3.2

Exhaiistive Testing.................................................................................................................... 290 Functional Testing.................................................................................................................... 290

Contents 9.3.3 9.3.4 9-4 9.5

DESIGN STRATEGIES FOR TESTING (CONTROLLABILITY A N D OBSERVABILITY)..................... 295 DESIGN FOR TESTABILITY (DFT)................................................................................................... 295

CHAPTER 10

10.2

Ad hoc DFT Techniques................................................... ..................................................... 295 System Level Testing or Board Test Techniques.................................................................. 297 Built-m Self-Test (BIST)............................. ...........................................................................300 ISSUES IN CHIP DESIGN........................................................................................... 307

REQUIREM ENTS O F A SU CCESSFU L CHIP D ESIGN..................................................................... 307 SYST EM -O N -CH IP (SoC)............................................................................................ .................... 308

10.2.1 10.3

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Structural Testing......................................................................................................................290 Fault Simulation....................................................................................................................... 291

9.5.1 9.5.2 9.5.3

10.1

a

Role o f the Embedded Processor in the SoC ........................................................................311

CHIP'S POW ER CO N SU M PTIO N : A N IMPORTANT ISSU E........................................................... 312

10.3.1 10.3.2 10.3.3

Power Network.........................................................................................................................313 Power Optimization................................................................................................................. 314 Chip Power Usage Analysis....................................................................................................314

10.4

CLOCK....................................................................................................................................................... 315 10.4.1 Clock Distribution................................................................................................................... 317

10.5

CHIP RELIABILITY........................................................................................................................... 320

10.6

A N A L O G INTEGRATION IN THE DIGITAL E N V IR O N M E N T ..........................................................323

10.7

SYSTEM -LEVEL STU D Y O F A PR O JECT.........................................................................................324

10.8

W H Y IS VLSI SO C H A LLE N G IN G ?.................................................................................................. 325

10.9

CRO SSTALK D E L A Y .........................................................................................................................327

11

LOÌAf“POÌWER CMOS VLSI

331

11.1

IN T R O D U CTIO N ...............................................................................................................................331

11.2

SO UR CES O F PO W ER C O N S U M P T IO N ................................................................. ........................332

11.3

SO LU TIO N S......................................................................................................................................333

11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.3.9 11.3.10 11.3.11 11.3.12 11.3.13

Reduce Vdd............................................................................................................................... 333 Power Supply Reduction......................................................................................................... 333 Variation o f tìie Threshold Voltage........................................................................................ 334 Optimal Power Voltage........................................................................................................... 335 Compensating for LowerSpeed...............................................................................................336 Voltage Swing................................................................................... .......................................338 Reduce c .................................................................................................................................. 338 Partition Blocks........................................................................................................................338 Locality of Reference.............................................................................................................. 3 3 8 Clocks and Control...................................................................................................................340 Logic D esign............................................................................................................................ 340 Buffer D esign........................................................................................................................... 342 R edu ced ................................................................................................................................... 342

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Contents 11.3.14 11.3.15 11.3.16 11.3.17 11.3.18 11.3.19 11.3.20

11.4

A P PR O A C H E S TO LOW -PO W ER D ESIG N ----------------------------------------------------------------------- 345

CHAPTER 12

12.1 12.2

NANOTECHNOLOGY: ELECTRONIC DEVICES--------------------------------------------347

INTRODUCTION..................................................................................................... ......347 N A N O -SC A LE M O S F E T S ................................................................................................................ 348

12.2.1 12.2 2 12.3

12.8

Islands, Potential Wells and Quantum Effects...................................................................... 355

Principle o f the SET....... ......................................................................... ............................... 358 I-V Characteristics o f SET...................................................................................................... 360 Conductance o f SET ............................................................................................................... 362

Q U A N T U M DOTS ( Q D s ) .................................................................................................................363

12.6.1 12.6.2 12.6.3 12.6.4 12.6.5 12.7

(CN FET)....................................................... 351

SINGLE-ELECTRON TRANSISTOR (S E T )........................................................................................358

12.5.1 12.5.2 12.5.3 12.6

EFFECTTRANSISTOR

Basic Physics o f the Carbon Nanotube................................................................................. 351 Basics of CNFETs.................................................................................................................... 353 Fabrication.................................................................................................................................355

SOLID STATE Q U A N T U M DEVICES................................................................................................ 355

12.4.1 12.5

Structure and Operation o f a MOSFET................................................................................. 348 Problems with Nano-Scale MOSFETs ................................................................................. 349

CARBO N N A N O TU BE FIELD

12.3.1 12.3.2 12.3.3 12.4

Glitch Avoidance............................................................ .......... ....................... ....................... 342 Point-to-Point Buses.................................................................................................................343 Reviewing the Algorithm........................................................................................................ 343 R e d u c e /sc.......1 ...................................................................................................................... 344 Resistive Networks........................................................................... .......................................344 Switching Ciurent..................................................................................................................... 344 Glitch Propagation.......... ................................................................ ........................................344

Physics o f a Quantum D ot.......................................................................................................363 I-V Characteristics o f a Quantum Dot............................................................... ................... 364 Quantum Cell Array (QCA).....................................................................................................365 Quantum Wires.................................................................................................. .......................366 Quantum Computing................................................................................................................ 366

OBSTACLES FOR THE SOLID STATE Q U A N T U M DEVICES......................................... ..................368 M O LE C U LA R ELECTRO N ICS...........................................................................................................368

12.8.1 12.8.2 12.8.3 12.8.4 12.8.5

Molecular Switching Devices................................................................................................. 369 Fabrication and Assembly o f Molecular Structures............................................................. 369 Molecular Wires .................................................................................................................. 370 Quantum Effect Molecular Electronic Devices.....................................................................370 Electromechanical Molecular Electtonic D evices.......................................................... 371

Q u e stio n B a n k ................................................................................................................................ 375

389

VLSI Fabrication Technology

CHAPTER

^

CHAPTER OBJECTIVES

In this chapter, you will be inữoduced to • • • • •

Fundamentals of VLSI Various processes in chip fabrication Fabrication steps of MOSFET Various packaging technologies BiCMOS device fabrication

1 .1 IN T R O D U C T IO N -A BRIEF HISTORY OF VLSI

In 1958, Jack Kilby built the first integrated circuit flip-flop with two transistors at Texas Instruments. In 2003, the Intel Pentium IV microprocessor contained 55 million transistors and a 512-Mbit dynamic random access memory (DRAM) contained more than half a billion transistors. This coưesponds to a compound annual growth rate of 53% over 45 years. No other technology in history has sustained such a high growth rate for so long. This incredible growth has come from steady miniaturization of ữansistors and improve­ ments in manufacturing processes. Most other fields of engineering involve tradeoffs between performance, power and price. However, as transistors become smaller, they also become faster, dissipate less power and are cheaper to manufacture. This synergy has revolutionized not only electronics, but also society at large. During the first half of 20th century, electronic circuits used large, expensive, powerhungry, and unreliable vacuum tubes. In 1947, John Bardeen and Walter Brattain built the first

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fiinctioning point contact transistor at Bell Laboratories. It was nearly classified as a militaiy secret, but Bell Labs publicly announced tìie device in the following year. Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization if multiple ừansistors could be built on a single piece of silicon. The invention of the fransistor earned the Nobel Prize in Physics in 1956 for Bardeen, Brattain and theứ co-worker William Shockley. Kilby received the Nobel Prize in Physics for the invention of ửie integrated circuit. Soon after mventing the pomt contact ưansistor. Bell Labs developed tiiie bipolar junction fransistor. Bipolar fransistors were more reliable, less noisy, and more power-efficient Early integrated cữcuits primarily used bipolar ừansistors. Transistors can be viewed as electeically confrolled switches with a control temiinal and two otìier termmals tiiat are connected or dis­ connected depending on the voltage applied to the control. Bipolar transistors reqvure a small current into the conttol (base) termmal to switch much larger currents between the otfier two (emitter and collector) terminals. The quiescent power dissipated by ứiese base currents limits the maximum number of transistors that can be integrated onto a single die. Metal Oxide Semi­ conductor Field Effect Transistor (MOSFETs) offers the compellmg advantage that they draw almost zero control current while idle. They come in two flavours: nMOS and pMOS, usmg n-type and p-type dopants, respectively. The onginal idea of field effect ữansistors dated back to the German Scientist Julius Lilienfield in 1952 and a structure closely resembling the MOSFET was proposed in 1935 by Oskar Heil, but materials problems foiled early attempts to make func­ tioning devices. Frank Wanlass at Fairchild described the first logic gates using MOSFETs in 1963. His gates used both nMOS and pMOS teansistors, earning the Complementary Metal Oxide Semiconductor (CMOS). The circuits used discrete transistors but consumed only nanowatts of power, six orders of magnitude less than theữ bipolar counterparts. With the develop­ ment of the silicon planar process, MOS integrated circuits became attractive for their low cost because each transistor occupied less area and the fabrication process was simpler. Early processes used only pMOS transistors and suffered from poor performance, yield, and reliability. Processes using nMOS transistors became dominant in 1970s. Intel pioneered nMOS technology with its 256-bit static random access memory and 4004 4-bit micropro­ cessor. While the nMOS process was less expensive than CMOS, nMOS logic gates still consumed power while idle. Power consumption became a major issue in 1980s as hundreds of thousands of transistors were integrated onto a single die. CMOS processes were widely adopted and have essentially replaced nMOS and bipolar processes for nearly all digital logic applications. Gorden Moore observed in 1965 that plotting the number of ừansistors that can be made economically fabricated on a chip gives a straight line on a semilogarithmic scale. He found ứansistor count doubling every 18 months. This observation has been called Moore’s Law and has become a self-fulfilling prophecy. The level of integration of chips has been classified as small-scale, medium-scale, large-scale, and very large-scale. Small-scale integration (SSI) cữcuits such as the 7404 inverter have fewer than 10 gates, with a conversion of roughly half a dozen fransistors per gate.

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Medium-scale integration (MSI) circuits such as the 74161 counter have up to 1000 gates. Large-scale integration (LSI) circuits such as simple 8 -bit microprocessors have up to 10,000 gates. It soon became apparent that new names would have to be created every five years if this naming trend continued and thus the term very large-scale integration (VLSI) is used to describe most integrated circuits from 1980s onwards. May be the next generation integration will be called as ulfra large-scale technology (ƯLSI). A corollary of Moore’s law is that transistors became faster, consume less power, and are cheaper to manufacture each year. Intel microprocessor clock frequencies have doubled roughly every 34 months. Remarkably, the improvements have accelerated in recent years. Computer performance has growth even more than raw clock speed. Even though an individ­ ual CMOS transistor uses very little energy each time it switches, the enormous numbers of ưansistors switching at very high rates of speed have made power consumption a major design consideration again. The 4004 used transistors with minimum dimensions of 10 micrometre in 1971. The Pen­ tium IV uses ttansistors with minimum dimensions of 130 nm in 2003, and even fiirther smaller dimensions nowadays. Obviously, this scaling cannot go on forever because transis­ tors cannot be smaller than atoms. Creative engineers and material scientists have billions of dollars to gain by getting ahead of their competitors. In the early 1990s, experts agreed that scaling would continue for at least a decade but that beyond that point the ftiture was murky. In 2009, we still believe that scaling will continue for at least another decade. The future is yours to mvent. In this chapter, we discuss the fabrication issues of the CMOS technologies. The reader studies each process individually and in the ending of the chapter, it will be clearly understood how integration of various processes is done for nMOS and CMOS technologies.

1.2 PROCESS TECHNOLOGIES USED IN TODAY'S DESIGN ENVIRONMENT

The mamstream process technology used in today’s chip design/manufacturing environment is Complementary Metal Oxide Semiconductor (CMOS) technology. Other technologies include bipolar, BiCMOS, Silicon on Insulator (SOI), and Gallium Arsenide (GaAs). In CMOS technol­ ogy, complementary symmetry refers to the fact that a CMOS circuit uses symmetrical pairs of p-type and n-type MOSFET transistors for logic functions. Originally, the phrase metal oxide semiconductor was a reference to the metal gate electrode placed on top of an oxide insula­ tor. MOSFET operation is discussed in detail in later chapters. However, in today’s CMOS process, instead of metal, the gate electrode is comprised of a different material, polysilicon as it can withstand high processing temperatures. As discussed above today, the majority of integrated circuits manufactured are CMOS circuits. This is due to three characteristics of CMOS devices: high noise immunity, low static power, and high density. The CMOS process has consistently advanced to smaller feature sizes over the years, allowing more circuitry to be packed in one chip, as described by Moore’s law.

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1.3 MAJOR PROCESS STEPS IN FABRICATING MOSFET

VLSI chips are manufactured on semiconductor material whose electrical conductivity lies between that of an insulator and a conductor. The electrical properties of semiconductors can be modified by introducing impurities through a process known as dopmg. The ability to control conductivity in small and well-defined regions of semiconductor material has led to the development of semiconductor devices. Combined with simpler passive components (resistors, capacitors and inductors), they are used to create a variety of electronic devices. As discussed earlier, CMOS is the most popular semiconductor process. The metal oxide semiconductorfield effect tramistor (MOSFET) is the transistor of the CMOS process. MOSFETs are comprised of channels of n-type or p-type semiconductor material and are thus called nMOSFET and pMOSFET, or nMOS and pMOS for short. The MOSFET has emerged as the omnipresent active ele­ ment for the VLSI integrated cừcuit. The competitive drive for better performance and reduced cost has resulted in the scaling of circuit elements to smaller and smaller dimensions. MOSFET teansistors are built through the semiconductor fabrication process, which is a sequence of mul­ tiple photographic and chemical processing steps. The electronic cữcuits are gradually, created on a wafer of pure semiconductor material such as silicon in a step by step manner. The processing steps are classified as follows: Silicon crystal growth Wafer cleaning Oxidation Photolithography Diffusion Ion implantation Dry etching Wet etching Plasma etching Thermal treatments (rapid thermal annealing, fiimace annealing, and oxidation) Chemical vapour deposition Physical vapour deposition Molecular beam epitaxy Electrochemical deposition Metallization Chemical-mechanical planarization Wafer testing Wafer back grinding Wafer mounting Die cutting Encapsulation Let us discuss main processing steps in detail in this chapter.

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.4 W AFER MANUfACTURE

iilicon is the second most abundant element in Ae earth’s crust; however, it occurs excluively in compounds. Elemental silicon is a man-made material refined from these various ompounds. The most common is silica (impure SÌO2). Modem ICs must be fabricated on iltrapure, defect-free slices of single-crystalline silicon, called wafers. A wafer is the circular ilicon base upon which chips are manufactured. It is made from an ingot, which is a cylin­ drical, single-crystal semiconductor typically resulting from the Czochralski crystal growth process, as depicted in Fig. 1.1. Wafer production requừes three general processes; • Silicon refinement. • Crystal growth. • Wafer formation. o 1.4 .1 Silicon Refinement Metallurgical-Grade Silicon (MGS)

Silicon refinement begins with the reduction of silica in an arc furnace at roughly 2000°c with a carbon soiưce. The carbon effectively “pulls” the oxygen from the SÌO2 molecules, thus chemically reducing the oxide to roughly 98% pure silicon, referred to as Metallurgical-Grade Silicon (MGS). The overall reduction is governed by the following equation: SÌO2 (solid) + SiC (solid)

Si (solid) + SiO (gas) + CO (gas)

(1.1)

Elecừonic-Grade Silicon (EG5)

MGS is not pure enough for microelectronic device applications because the electronic properties of a semiconductor such as silicon are extremely sensitive to impurity concen­ trations. Impurity levels measured at parts per million or less can have dramatic effects on carrier mobilities, lifetimes, etc. It is, therefore, necessary to further purify the MGS into Electronic-Grade Silicon (EGS). Silicon is pulverized and treated with hydrogen chloride (HCl) to form trichloro silane (SÌHCI3). The overall reduction is governed by the following equation; SÌHCI3 + H2 ^ Si (solid) + 3HC1 (gas)

(1.2)

This reaction takes place in a reactor containing a resistance heated silicon rod, which serves as nucleation point for the deposition of silicon. The EGS, a polycrystalline material of high purity, is the raw material used to prepare device quality, single crystal silicon.

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«

What are the environmental conditions required for IC fabrication? An IC fabrication requkes a clean processing room (especially for lỉứìogr^hy). The need for such clean room is because dust particles in the ak can settle OD the semiconductor wafers (here silicon) and masks used in the litíiography (this topic is discussed latter) and can cause defects in tíie devices fabricated which result in cữcuit failure. For example, a dust particle on a semiconductor surface can disrupt the single crystal growth of an epitaxial film causing fonnation of dislocations; a dust particle incorporated mto the gate oxide can result in device failure due to low breakdown voltage. In a clean room, the total number of dust particles per unit volume must be tightly controlled along with temperature and humidity. Various standards of clean rooms like class 100, class 1000, clean room are used. For example, class 100 clean room has dust particle count of 100 particles/ft^ with particle dimension of 0.5 fim smce the number of dust particles increases as the particle size increases a precise controlled clean room envữonment is requừed when the minimum feature lengths of ICs are reduced to submicron range. For most IC fabrication areas class 100 clean room is used whereas in lithography area class 10 clean room is used. Deionised water is used in almost all semiconductor processes. The resistivity of deionised water is very high. >■

1.4.2 Crystal Growth The Czochralski Technique

1. The Czochralski technique uses an apparatus known as crystal puller as shown in Fig. 1.1. In the crystal growth process, polycrystalline silicon (EGS) is placed in the crucible and the furnace is heated above the melting temperature of the silicon. 2. Dopant impurity atoms such as boron or phosphorus may be added to the mol­ ten intrinsic silicon in precise amounts to dope the silicon, thus changing it into n-type or p-type extrinsic silicon. This influences the electrical conductivity of the silicon. 3. A seed crystal mounted on a rod is dipped into the molten silicon. This seed crystal rod is continuously pulled upwards and rotated at the same time. The crystal ingot is then built layer by layer of atoms. 4. By precisely controlling the temperature gradients, the rate of pulling, and the speed of rotation, a large single crystal, cylindrical ingot can be extracted from the melt. This process is normally performed in an inert atmosphere (such as argon) and in the cham­ ber made of an inert material (such as quartz).

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Seed Single silicon ciystal Quartz crucible Water cooled chamber Heat shield Carbon heater Graphite crucible Crucible support Spill ưay Electrode

Fig. 1.1 Czochralski crystal puller. {Courtesy: Professor c. J. Spanos, u.c. Berkeley.)

Fig. 1.2 The silicon ingot. {Photo courtesy ofshin-Etsu Handotai Co., Tokyo)

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Fig. 1.3 Wafers cut from silicon ingot. (Photo courtesy ofshin-Etsu Handotai Co., Tokyo.) 1.4.3 Wafer Formation

Using high-precision diamond saws or diamond wkes, the ingot is first shaped and then sliced into wafers with thicknesses on the order of 0 5 mm. This wafer fabrication process includes the steps of cutting, grinding, polishing, and cleaning to transform a single-crystal rod into many circular wafers for manufacture into semiconductor devices. A wafer is measured by its diameter: 4 inches, 6 inches, 8 inches, or 12 inches. Inside a wafer, as shown in Fig. 1.4, there are many small blocks or cells. These mdividual cells are called dies or chips. A die is a small piece of silicon material upon which a given cừcuit is fabricated. Typically, integrated cữcuits are produced in large batches on a smgle wafer

Fig. 1.4 A wafer with dies. (Photo courtesy of Intel Corporation.)

through various process steps. The resultant wafer is then cut into pieces, each containing one copy of the desừed integrated cừcuit. Each one of these pieces is a die. Figure 1.4 shows a wafer with dies.

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1.5 W AFER CLEANING

Microfabrication is earned out in clean rooms where air has been filtered of particle con­ tamination and temperature, humidify^ vibrations and electrical disturbances and is under stringent control. Smoke, dust, bacteria and cells are micrometres in size, and their presence will destroy the functionality of a fabricated device. Clean rooms provide passive cleanliness but the wafers are also actively cleaned before every critical step. Wet-deaning steps in solutions

• RCA-l clean in ammonia peroxide solution removes organic contamination and particles. • RCA-2 clean in hydrogen chloride and hydrogen peroxide mixture removes metallic impurities. • Sulphuric acid and hydrogen peroxide mixture (a.k.a. Piranha) removes organics. • Hydrogen fluoride removes native oxide from silicon surface. These are all wet-cleaning steps m solutions. Dry-cleaning methods

• Oxygen and Argon plasma treatments to remove unwanted surface layers, or hydrogen bake at elevated temperature to remove native oxide before epitaxy. Oxidation, and all high temperature steps are very sensitive to contamination, and clean­ ing steps must precede high temperature steps. Formation of defect-free silicon and silicon dioxide surface is very important in MOSFET fabrication. Hence, cleaning of silicon surface before gate oxide growth is very important cleaning step in the process. 1.6 DOPING AND IMPURITIES

In order to fabricate semiconductor devices, a controlled amount of impurities has to be intro­ duced (doped) selectively into the single crystal wafers. There are three basic methods used for controlled doping of a semiconductor. They are • Epitaxy • Diffusion • Ion implantation 1.6 .1 Epitaxy

The term epitaxy literally means “aưanged upon”. In this process, a thin layer of single crystal semiconductor (typically a few nanometres to a few microns) is grown on an already existing

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crystalline substeate such that the grown film has same lattice structure as the substrate. Therế are basically two types of epitaxy: (a) Homo Epitaxy, in which the same material as that of substrate is grown, ex^iq>le is growing Si on silicon substrate. (b) Hetero Epitaxy, in which a different layer is grown over the substeate. Example is grow­ ing AlGaAs on GaAs. In this type the material grown also ứiere should be lattice match between the substrate and the g ro w material so that crystal doesn’t have strain. Thermal coefficient of expansion of botíi materials should match. Epitaxy is further classified into • Vapour-phase epitaxy (VPE). • Liquid-phase epitaxy (LPE). • Molecular beam epitaxy (MBE). Vapour-phase Epitaxy

Silicon is most commonly grown from silicon teừachloride in hydrogen at approximately 1200°c. SiCl4(g) + 2H2(g) ^ Si(s) + 4HCl(g)

(1.3)

This reaction is reversible, and the growth rate depends strongly upon the proportion of the two source gases. Growth rates above 2 micrometres per minute produce polycrystalline sili­ con, and negative growth rates (etching) may occur if too much hydrogen chloride by product is present. (In fact, hydrogen chloride may be added intentionally to etch the wafer.) An addi­ tional etching reaction competes with the deposition reaction: SiCl4(g) + Si(s)

2SiCl2(g)

(1-4)

Silicon VPE may also use silane, dichlorosilane, and ừichlorosilane source gases. For instance, the silane reaction occurs at 650°c in this way SiH4 ^ S i + 2H2

(1.5)

This reaction does not inadvertently etch the wafer, and takes place at lower temperatures than deposition from silicon tetrachloride. However, it will form a polycrystalline film unless tightly controlled, and it allows oxidizing species that leak into the reactor to contaminate the epitaxial layer with unwanted compounds such as silicon dioxide. Liquid-phase Epitaxy

Liquid-phase epitaxy (LPE) is a method to grow semiconductor crystal layers from the melt on solid subsừates. This happens at temperatures well below the meltmg point of the deposited

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semiconductor. The .semiconductor is (ịissolved in the melt of another material. At conditions that are close to tíie equilibrium between dissolution ami deposition; the deposition of the semi­ conductor crystal on the substrate is slow and imiform. The method is mainly used for the growth of compound semiconductors. Very thin, uniform and high quality layers can be pro­ duced. A typical example for the liquid-phase epitaxy method is the growth of ternary and quaternary III-V compounds on gallium arsenide (GaAs) substrates. As a solvent quite often gallium is used in this case. Another frequently used subsfrate is I n d i^ Phosphide (InP).

Mofecular Beam Epitaxy

In MBE, a source material is heated to produce an evaporated beam of particles. These parti­ cles travel through a very high vacuum (10“* Pa; practically free space) to the substrate, where they condense. MBE has lower throughput than other forms of epitaxy. An epitaxial layer can be doped during deposition by adding impurities to the source gas, such as arsine, phosphine or diborane. The concentration o f impurity in the gas phase determines its concentration in the deposited film.

1.6 .2 Diffusion

Although it is possible to grow a layer with controlled doping by epitaxy, it is not possible to control the doping of selected regions of the semiconductor surface. In other words, epitaxial growth takes place throughout the surface that is, it is non-selective. In order to achieve selec­ tive doping, the technique most commonly used in silicon processing is called as difiusion. The basic principle underlying this process is that the dopant atoms migrate from a region of high concenfration to the region of low concenữation. In simple, diffiision is the process of introducing controlled amounts of dopants into the semiconductors. For example, the selected source and drain regions of MOSFET are doped by diffusion. The unwanted regions of difiiision are covered by the masking material (example: photoresist) while others are left unpro­ tected. Now if the semiconductor is held in an ambience of high dopant concenữation and temperature is raised, dopant atoms migrate into the unprotected regions of the semiconductor while many semiconductor atoms move out of their regular lattice sites. Three kinds of situa­ tions arise in the process of the diffusion. • Substitutional diffusion • Interstitial diffiision • Interstitialcy diffusion. Subtitutional dtffusion: An impurity atom wanders through the crystal by jumping from one lattice site to the next, thus substituting for the original host atom. However, it is necessary that this adjacent site be vacant, i.e., vacancies must be present to allow substitutional difiiision to occur.

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Note: Due to high temperature, silicon atoms get removed from its lattice p o ^ o n m ữiÊ ciystal and the impurity atom takes its place. (Fig. 1.5)

o o oo o o • o o oo

o o o o • o o o o o o

Before

After Fig. 1.5 Substitutional diffusion.

Interstitial diffusion: An impurity atom moves dirough die crystal lattice by jumping one interstitial site to the next. Interstitial difiiision requữes that jump motion occurring from one interstitial site to another adjacent interstitial state. This process is relatively fast, because of large number of vacant interstitial place in ứie semiconductor ciystal. (Fig. Ỉ.6 )

o o oo o o oo 0*0 o o

o o o o o 0*0 o o o o o

Before

After Fig. 1.6 Interstitial diffusion.

Interstitial-substitutional diffusion: In ứũs case, impurity atoms occupy substitutional as well as interstitial sites. However, ứiey move only at a significant rate when in interstitial sites (by interstitial diffusion). The dissociative mechanism, by which a substitutional impurity atom can become an mterstitial, leaving behind a vacancy, can be tìie confrollmg factor for this process as a result, the effective diffusivity is a function of tìie disassociation rate and depends on botìi impxirity concentration and crystal quality. (Fig. 1.7) An alternative pathway for mterstitial diflusion is the kick-out mechanism. Here a rapidly moving interstitial diffusion can move into a substitutional site by displacing an atom, which is already in place resulting in the formation of a self-interstitial. [Fig. 1.8(a)]

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oooo o • o o oooo

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oooo o O' o 0 0*0 0

Before

After Interstitial-Substitutional diffusion.

o

o o o o o o o o o o o o

o o o o o • o o o o o o

Before

..

A fter

Fig. 1.8(a) Kick-out mechanism.

Interstitialcy diffusion: This is modified version of substitutional difiusion. Interstitial host atoms can be annihilated by pushing substitutionally located impurity atoms in interstitial sites. These impurities can now diffuse to adjacent substitutional sites and create new self­ interstitials. [Fig. 1.8(b)]

o o oo o • oo o o oo

o o o o o o o,p o o o o o o• o o o -o o o o o o Fig. 1.8(b) Interstitialcy diffusion.

DifTusion Equation The basic diffiision process is similar to that of charge carriers (electrons and holes) We define flux F as the number of dopant atoms passing through a unit area in unit time and c as the dopant concenteation per unit volume. Then

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c = carrier concentration D = dififiision coefficient (or) difiiisivity.

Note: The basic driving force of difiRision process is concentoation gradient ÕCIÕX. ITie flux is proportional to concentration gradient and the dopant atoms will move away from a high concenttation region towards a lower concenưation region. Substituting “F ” in one-dimensional continuity equation, we get _ (1.7) dt

dt

dx

When ứie concentration of dopant atoms is low, the dỉữìision coefficient can be considered independent of doping concenừation and above equation becomes

dc

( 1-8 )

=

dt

d^X

This is known as Flick’s dififtision equation or law. 1 .6 3 Ion Implantation

Ion implantation is alternative technique for selective dopmg of semiconductors. The doping profile is more precisely controlled by this technique (Fig. 1.9). • Ion unplantation equipment typically consists of an ion soiưce, where ions of the desữed element are produced, an accelerator, where ứie ions are electrostatically accelerated to a high energy, and a target chamber, where tìie ions impinge on a target, which is ứie mate­ rial (silicon substrate/wafer) to be implanted. • Each ion is typically a single atom, and thus the actual amount of material implanted in the target is the mtegral over time of the ion current. This amount is called tiie dose. • When ứiese ions enter into the semiconductor, they loose the kinetic energy tíirough a series of collisions widi the electt-ons as well as nuclei of tíie lattice atoms. • Finally, the impurity atom comes to rest when its kmetic energy falls to zero. The dis­ tance perpendicular to the semiconductor surface covered by the impurity atom is called projected range (/?p).The projected range for a particular ữnpurity species depends upon tìie energy (£) of tìie ion beam. Typical ion energies are in ứie range of 10 to 500 keV (1600 to 80,000 aJ). Energies in the range 1 to 10 keV (160 to 1600 aj) can be used, but result in a penetration of only a few nanometres or less. The doping after the implantation is given by 2>

A^W = — % = e x p A/ỉpVnĩ

X -R p

(1.9)

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Subsừate

Current integrator Ion source Fig. 1.9 Ion implantation setup with mass separator.

The implantation dose depends on the ion beam cuưent density J and implantation time t and is expressed as (1.10) Since ion unplantation dose depends only on the current and time, it can be precisely con­ trolled. From ứie equation 1.9, it is evident that the peak impurity concenữation occurs at x = Rp that is maximum number of dopants ions come to rest. By varying the energy of the ion beam, it is possible to obtain the implantation very close to the surface or deep inside as per the requữements. This phenomenon is valid for amorphous silicon. The Fig. 1.9 shows ion implan­ tation setup with mass separator. Due to the regularity of single crystal sttucture, the impurity atom finds an open coưidor in between the lattice atoms when the ion beam is projected along the major crytallographic axis and can thus peneừate much deeper. This is known as ion channelling. Channelling is severe for low dose. By tilting the substrate with respect to the ion beam direction channelling can be reduced to a great extent. Even though ion implantation offers a lot of advantages over dif­ fusion, the process of ion implantation causes lot of damages in the implanted region. This is termed as crystallographic damage. Crystallographic damage

Each individual ion produces many point defects in the target crystal on impact such as vacan­ cies and interstitials. Vacancies are crystal lattice points unoccupied by an atom. In this case

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the ion collides with a target atom, resulting in transfer of a significant amount of energy to the target atom such tìiat it leaves its crystal site. This taiget atom then itself becomes a pro­ jectile in the solid, and can cause successive collision events. Interstitials result when such atoms (or the original ion itself) come to rest in the solid, but find no vacant space m the lat­ tice to reside. These point defects can migrate and cluster with each other, resulting in dislo­ cation loops and other defects. These defects have to be tíiennally annealed in order to make doped regions elecữonically active. Annealing can be carried out in a conventional furnace at a temperature range of 800-1000“C for 20-30 minutes. This alters the doping profile considerably by driving the dopants inside the silicon substrate. Rapid thermal annealing (RTA) is an alternative tech­ nique in which the substrate temperature is suddenly raised to a high value quickly, held constant for a brief period and then cooled down fast. The entire annealing process takes a few seconds to few minutes and the doping profile remains unaltered. RTA is therefore prefeưed as an annealing technique in present day VLSI technology over conventional furnace annealing. 1 .7

GROWTH AND DEPOSITION OF DIELECTRIC FILMS

In semiconductor processing, dielectric films essentially serve three purposes. They can be • Part of the active device, for example, gate oxide of a MOS transistor. • Used as masks to protect against d iffu sio n or ion implantation. • Used as protecting layer at the end of device fabrication so as to protect from harsh ambience and ensure reliable operation. The most commonly used dielectric films in the semiconductor technology are SÌO2 and SÌ3N4. These films can be grown on the semiconductor or deposited by using various tech­ niques like oxidation, etc. 1 .7 .1 Thermal Oxidation

In micro fabrication. Thermal oxidation is a way to produce a thin layer of oxide (usually silicon dioxide) on the surface of a wafer (subsừate). This is usually earned out in an open tube furnace shown in the Fig. 1.10 at the temperature range of 900-1200°C. A single iumace accepts many wafers at the same time, in a specially designed quartz rack called a “boat”. The boat enters the oxidation chamber from one side (this design is “horizontal design”), and holds the wafers vertically, beside each other. A typical horizontal oxidation furnace is shown in the Fig. 1.10. The different types of thermal oxidation methods are (i) Dry oxidation (ii) W et o x id atio n .

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Fig. 1.10 Furnaces used for diffusion and thermal oxidation. {Courtesy: LAAS technological facility in Toulouse, France.)

If it is carried out in an atmosphere of dry oxygen, it is known as dry oxidation and if caưied in water vapour, it is known as wet oxidation. For dry oxidation, oxygen is passed through the tube where it reacts with the silicon to form SÌO2 by means of the following reaction. Si(s) + 0 2 (g)

Si0 2 (s)

In case of wet oxidation, high purity de-ionized water kept in quartz bubbler at the inlet of the fiimace is heated to a temperature close to the boiling point. High purity oxygen or niữogen is passed through it so that the gas flowing into the furnace is saturated with the water vapoiư. Water then acts as the oxidizing agent and the oxidation reaction is given by Si(s) + 2 H2 0 (1)

Si0 2 (s) + 2 H2(g)

( 1.12)

Thermal oxide incorporates silicon consumed from the substrate and oxygen supplied from tìie ambient. Thus, it grows both down into the wafer and up out of it. For every unit thickness of

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silỉtxHi consumed, 2.17 unit tfiidaiesses o f oxide will a p p ea s. ConvGEsefy, if a bare sflkxm suffioB is oxidized, 46% of die oxide dÕGÌaiess will lie bek)w die arigmal sm&ce, and 54% above it ữâdetỊaaHty

Wet oxidalion is ỊH«foied to diy oxidatirai fix growiog duck Oỉddes, because of die luglngrowtfa rate. HowevCT, Êist oxidatiỉHi leaves iiKHe dangling IxMids at ttie siliom ÌDlaâce, ^ ndi jHoduce quantum stales fix' elec^rms and allow c^nrotf to leak aling the into^ice. (H bs is called a “dirty” int«ỄK:e.) W(rt oxidalitm also yields a lowOT-doisity oxide, with lowCT didectric strmgdL The loi^ tinie required to grow a ứndc: oxide in (fay oxidation makes this process imjH^ticaL Thick oxides are usually ^ w n widi a Img wet oxidation bracketed by ^KXt dty <»ies (a dbry-wet-dry cycle). The begianing and oidiiig diy oxidalitHis produce films of highquality oxide at the outo^ and mner suiÊK:es of the oxide layo-, respectively. Sometinies tiaces of cMtsine are inttodiKed m ứie gas flow during oxidaticm to inq)n)ve the quality of gate o x i ^ fiw MOSFETs. 7.7.T.7 K m e tía o tĩh tm a lO K Ìđ a tio B Ded-GroK tnodd

The Deal-Grove model (Fig. 1.11) maổiematically describes the growth of an oxide layer on ứie suTẼice of a materiaL In particular, it is used to analyze thomal oxidation of silicon in SCTiiconductOT device âbrícation. The model was first published m 1965 by Bruce Deal and Andrew Chove, of Faừ Child Coipoiaticm. The model assumes that oxidation occurs at the mterfsu:^ between die oxide and the subsbate, radier than between the oxide and the ambient gas. Thus, it considers ứnee phenomena that die oxidizmg species undergoes, in this order as shown in die Fig. 1.11.

Fig. 1.11 Oxidation process.

1. It diflfuses from ứie bulk of the ambient ?as to the surface. 2. It diffuses duough ứie existing oxide layer to ứie oxide-substrate iaterface. 3. It reacts widi tbe substtate.

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The oxide thickness grown on the silicon by the process of dry or wet oxidation is depen­ dent on the oxidation time and temperature. This thickness can be expressed as a linear-para­ bolic relation d ^‘ + Ad=B{t + t)

(1.13)

d = oxide thickness A and B are coefficients that depend on the oxidation time and temperature t = oxidation time X= parameter for fitting the initial value of the oxide thickness. For short duration of time, d « A then equation (1.13) can be approximated as d = -{t-\-T) a

(1.14)

The equationsays thatwhen oxidation is carried out for shortdiưation of time, the oxide thickness increaseslinearly with time. The oxidation inthis regimeis limited by surface reac­ tion rate and is characterized by linear rate constant (BIA). For longer duration of oxidation {t + x) » ụP-IAE), the oxide thickness can be expressed as d = 4Wt

(1.15)

In this regime, the oxidation rate is governed by difiusion of the oxidizing agent through the already existing oxide layer and is characterized by parabolic rate constant (B). Important notes: 1. Thermal oxidation can be performed on selected areas of a wafer and blocked on oth­ ers. Areas which are not to be oxidized are covered with a film of silicon nitride, which blocks difEusion of oxygen and water vapour. The nitride is removed after oxidation is complete. This process cannot produce sharp features, because lateral (parallel to the sur­ face) diffusion of oxidant molecules under the nitride mask causes the oxide to protrude into the masked area. 2. Because impurities dissolve differently in silicon and oxide, a growing oxide will selec­ tively take up or reject dopants. This redisfribution is governed by the segregation, which determines how strongly the oxide absorbs or rejects the dopant, and the diffusivity. 3. The orientation of the silicon crystal affects oxidation. A <100> wafer oxidizes more slowly than a < 1 1 1 > wafer, but produces an electrically cleaner oxide interface. 4. Thermal oxidation of any variety produces a higher-quality oxide, with a much cleaner interface, than chemical vapour deposition of oxide resulting m Low Temperature Oxide layer. However, the high temperatures required to produce High Temperature Oxide (HTO) restrict its usability. For instance, in MOSFET processes, thermal oxida­ tion is never performed after the doping for the source and drain terminals is performed because it would disturb the placement of the dopants.

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1 .7 .2 Deposition of Dielectric Films

In silicon device manufacturing where a dielectric layer is required as final passivating iayw high temperature process may not be suitable. In such cases, silicon dioxide and silicon nibide are deposited by a process known as chemical vapour deposition. Chemical vapour deposi­ tion (CVD) is a chemical process used to produce high-purity, high-performance solid mate­ rials. The process is often used in semiconductor industry to produce thin films. In a typical CVD process, the wafer (subsừate) is exposed to one or more volatile precursors, which react on the substrate surface to produce the desired deposit. ĩypes of chemical vapour deposition

A number of forms of CVD are in wide use and are frequently referenced in the literature. These processes differ in the means by which chemical reactions are initiated (e.g., activation process) and process conditions. • Atmospheric pressure CVD (APCVD) - CVD processes at atmospheric pressiưe. • Low-pressure CVD (LPCVD) - CVD processes at sub-atmospheric pressures. Reduced pressures tend to reduce unwanted gas-phase reactions and ũnprove film uniformity across the wafer. Most modem CVD process is either LPCVD or UHVCVD. • Ultrahigh vacuum CVD (UHVCVD) - CVD processes at a very low pressure, typically below 10-^ Pa (~ 10“* torr). • Plasma enhanced CVD (PECVD) - CVD processes utilize plasma to enhance chemical reaction rates of the precursors. PECVD processing allows deposition at lower tempera­ tures, which is often critical in the manufacture of semiconductors. • Vapour-phase epitaxy (VPE). Substances commonly deposited for ICs

Polysilicon

Polycrystalline silicon is deposited from silane (SÌH4), using the following reaction: S iH 4 -> S i + 2H2

(1.16)

This reaction is usually performed in LPCVD systems, with either pure silane feedstock, or a solution of silane with 70-80% nitrogen. Temperatures between 600 and 650"C and pressures between 25 and 150 Pa yield a growth rate between 10 and 20 nm per minute. An alternative process uses a hydrogen based solution. The hydrogen reduces the growth rate, but the temperature is raised to 850 or even 1050°c to compensate. Polysilicon may be grown directly with doping, if gases such as phosphine, arsine or diborane are added to the CVD chamber. Diborane increases the growth rate, but arsine and phosphine decrease it.

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Silicon dioxide

Silicon dioxide (usually called simply “oxide” in the semiconductor indusừy) may be deposited by several different processes. Common source gases include silane and oxygen, dichlorosilane (SÌCI2H2) and nitrous oxide (N2O), tettaetíiylorthosilicate (TEOS; Si(OC2Hs)4). The reactions are as follows: SÌH4 + O2 -»• SÌO2 + 2H2

(117)

SÌCI2H2 + 2N 2O — SÌO2 + 2N 2 + 2HC1

(1.18)

Si (0 C2H5)4 -♦ SÌO2 + by-products

(119)

CVD oxide invariably has lower quality than thermal oxide, but thermal oxidation can only be used in the earliest stages o f IC manufacturing. Oxide may also be grown with impiirities (doping). This may have two purposes. During further process, steps that occur at high temperature, the impurities may diffuse from the oxide into adjacent layers (most notably silicon) and dope them. Silicon nitride

Silicon niừide is often used as an insulator and chemical barrier in manufacturing ICs. The following two reactions deposit nitride from the gas phase: 3 SÌH4 + 4N H 3 -> SÌ3N 4 + I2H2

(1.20)

3 SÌCI2H2 + 4N H 3 -»• SÌ3N 4 + 6HCI + 6H2

(1.21)

Silicon niteide deposited by LPCVD contains up to 8 % hydrogen. 1.8 MASKING AND LITHOGRAPHY

Semiconductor lithography is a process of drawing patterns on a silicon wafer. The patterns are drawn with a light-sensitive polymer called photoresist. These patterns define various regions in an integrated circuit such as implantation regions, contact windows, etc. To build the com­ plex structures required for an integrated circuit, the lithography and etch-pattem transferring steps are typically repeated 20-30 times. The choice for performing this patterning is opti­ cal lithography. It is basically a photographic process by which the light-sensitive polymer (photoresist) is exposed and developed to form three-dimensional images on the substrate. Ideally, the photoresist image should have the exact shape of the intended pattern in the plane of the substrate. The final photoresist pattern is binary, i.e., parts of the substrate are covered with resistwhile other parts are completely uncovered. This binarypattern isnecessary for patterntransfer as theparts of the substrate covered with resist will be protected from etching, ion implantation, or other pattern transfer mechanisms.

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1.8 .1 Photomask

The photomask is an essential component in semiconductor lithography. It contains the detailed blueprint of the designed circuit. Using the photomask, specific images of detailed devices are transfeưed onto the surface of the silicon wafers by means of photoiitíiography. A photomask is used just like the negative in photography that captures specific images for later reproduc­ tion. In photography, multiple copies of photos are reproduced using the original image ca^>tured on the negative. Likewise, a photomask produces duplicate images or patterns o n to the silicon wafers. A single photomask plate produces identical images on thousands of wafers. As the quality of the finished photograph is determined by the quality of the onginal film, the quality of the photomask determines the ultimate quality of semiconductor chips. The mate­ rial used for building photomasks is a quartz plate upon which detailed images or patterns are formed. The patterns or images are then transfeưed onto the wafer surfaces by shuiing light through the quartz plate as depicted in Fig. 1.12, just as negative film projects images onto photographic paper. Each mask contains only one layer of the circuit. A set masks, each defining one pattern layer, is fed into a photolithography machine and individually selected for exposure to form the desữed pattern on the wafer. Circuit elements (transistors, capacitors and resistors) are cre­ ated by those patterns of many layers.

Light source with wavelength A,

Lenses Pattern on photomask

Pattern on mask \

* Resulting pattern on wafer

Lenses Light Wafer

Fig.1.12 Optical lithography system.

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Procedure for P a ttm i Transfer

: consists of the following basic steps: • Preparation of wafer The wafer is initially heated to a temperature sufficient to drive off any moisture that may be present on ứie wafer Sluface. Wafers that have been in storage must be chemi­ cally cleaned to remove contamination.

^ W aier

o

O xide O xidized w afer Photoresist Photoresist coating

I

u v light Photom ask

A lisii and exposure

D e\elopm ent

Etch oxide

Strip photoresist

Fig. 1.13 Simplified representation of primary steps required for implementation of photolithography and pattern transfer.

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• Photoresist application Photoresist, a viscous liquid polymer, is applied to the top Sluface of the oxidized wafa. The application typically occurs by dropping (or spraying) a small volume of phofaHesist onto a rapidly rotating wafer, yielding a uniformly thin film on the surface. Following spinning^ the coated wafer is soft baked on a hot plate, which drives out most solvents from the photoresist and improves adhesion to the imderlying subsfrate. This is known as pre-baking. • Exposing and Developing The wafers are exposed to ultraviolet light through a mask that contains the layout pat­ terns for a given drawn layer as shown in the Fig. 1.13. After exposiưe the photoresist absorbs the radiation in the exposed areas from the u v beam and changes its chemical structure, i.e., it breaks long chain bonds and become soluble in the developer solution. • Developing A developer solution is a mixture of deionized water and KOH (potassium hydroxide pel­ lets). The wafer is dipped in the developer solution so that the exposed resist areas on the substrate dissolve in ứie developer solution. This process is called as development. • Baking The resulting wafer is then “hard-baked”, typically at 120 to 180°c. The hard bake solid­ ifies the remaining photoresist, to make a more durable protecting layer in future ion implantation, wet chemical etching and plasma etching. • Etching In the etching step, a liquid (“wet etching”) or plasma (“dry etching”) chemical agent removes the uppermost layer of the substrate in the areas that are not protected by photo­ resist. A more detailed discussion about etching is given later in this chapter. • Photoresist removal After a photoresist is no longer needed, it must be removed from the subsừate. This usually requires a liquid “resist stripper”, which chemically alters the resist so that it no longer adheres to the substrate. Alternatively, photoresist may be removed by a plasma containing oxygen, which oxidizes it. This process is called ashing, and resembles dry etching. The three general methods used to expose photoresist are contact, proximity and projection photolithography. 1.8.3 Contact Photolithography

In this type of lithography, the mask is kept in direct contact with the substrate and expo­ sure is done. Contact lithography offers high resolution. But practical problems such as

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lask damage and the resultant low yield make this process unusable in most production nvironments. .8.4 Proximity Photolithography

is similar to contact photolithography method except that there is a small gap of a few Jiicrons between the wafer and mask during the exposure. This results in optical diffraction which results a limit on the resolution. t

1.8.5 Projection Lithography

By far tíie most common method of exposure is projection printing. Projection lithography derives its name from the fact that an image of the mask is projected onto the wafer, as shown in Fig. 1.14. There are two major classes of projection lithography tools: o • Scanning

• Step-and-repeat systems

Light source

Light source

A

Stepper system with reduction Fig. 1.14 Scanner and step-and-repeat projection systems.

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Scanning projection (Fig. 1.14) printing employs reflective optics to project a slit of ligji from the mask onto the wafer as the mask and wafer are moved simultaneously past dỂ slit. Exposure dose is determined by the intensity of the light, tìie slit width, and the speed at which the wafer is scanned. These early scanning systems are 1:1 (the mask and in u ^ sizes are equal). The step-and-repeat system, or stepper for short, exposes the wafer one rectangular section (image field) at a time and can be 1:1 or a reduction and is repeated throughout the wafer. The step-and-scan approach uses a fraction of the normal steppei field and then scans this field in one direction to expose the entire 4X reduction mask. The wafer is then stepped to a new location, and the scan is repeated. The smaller imaging field simplifies the design and manufacturing of the lens, but at the expense of a more compli­ cated reticle and wafer stage. Step-and-scan technology is the technology of choice today for <250 lun manufacturing. In semiconductor lithography, resolution is the smallest feature that can be printed on a wafer with adequate control. It has two basic limits: the smallest image that can be projected onto the wafer and the resolving capability of the photoresist to make use of that image. From the imaging projection side, resolution is determined by the wavelength of the exposed light.

Fig. 1.15 Photolithography machine in yellow room. (Courtesy: Lunds Nanometre Consortium Department ot Solid state Physics, Sweden.)

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hotolithography is carried out in yellow rooms and on dry days generally. Other types of thographic methods include electron beam lithography, X-ray lithography, ion-beam lithogiphy. These topics are discussed very briefly. For the reader to have a practical feel about the hotolithography, a picture is given below (Fig. 1.15). .8.6 Electron Beam Lithography

The most common nanopatteming method out these days is electron beam lithography (EBL). This is a direct analogy with photolithography, where electron beam exposure alters the chem­ istry of the resist instead of light exposure. The most common (positive tone) EBL resist is polymethyl (methacrylate), abbreviated PMMA. EBL can routinely produce lines as naưow as 20-30 nm in PMMA. Smaller features are possible in certain circumstances. Limiting factors include feature broadening from secondary elecứon yields (proximity exposure) and difficulties in developing such small featares. The biggest problem with EBL on the large scale is speed. In photolithography, a whole wafer can be exposed simultaneoxisly, while EBL requừes the e-beam to draw each feature one at a time. It remains an ideal technique for producing small patterns on few-nun sized substrates, EBL Ũ used in fabrication o f masks fo r photolithography. 1 .8 .7 lon-Beam Lithography

lon-beam lithography can achieve higher resolution than optical. X-ray and electron beam lithography because ions have higher mass and therefore scatter less than electrons. By anal­ ogy to electron beam lithography, focused ion-beam lithography scans an ion beam across a surface to form a pattern. The ion beam may be used for directly sputtering tíie sxuface, or may mduce chemical reactions in the exposed top layer. There are two types of ion-beam lithography systems—scanning focussed beam systems and mask beam system. The former system is similar to beam lithography in which the ion source can be Ga'^ or The latter system is similar to an optical 5X reduction projection step and repeat system which projects 100 keV light ions such as through a stencil mask. Most important application is the repair of masks for optical lithography. 1.9 ETCHING

Etching is the process of removal of the substrate from the unmasked regions so that the desired pattern is transferred on to it. Etching is generally done after lithography. Etching is of two types: • Wet chemical etching • Dry etching

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1.9 .1 Wet Chemical Etching

It is used extensively m semiconductor processing. Chemical etchants are used for ìapỊÌa^ and polishing an optically flat, damage free surface. The mechanism of wet chemical etchã^ involves three essential steps: ( 1 ) reactants are transported by diffusion to tìie reacting sưẼKX (2) chemical reaction occur near the surface (3) products from tíie sxuface are removed by dif­ fusion. Wet etching can occur isofropically and anisotropically. Silicon Etching

Wet chemical etching proceeds by oxidation, followed by dissolution of oxide by a chemical reaction. For silicon, the most conunonly used etchants are mixtures of nitric acid and hydro­ fluoric acid in water or acetic acid. Si + 4HNƠ3 ^

SÌO2 + 2H2O + 4NƠ2

(1.22)

Hydrofluoric acid is used tx) dissolve the SÌO2 layer. The reaction is SÌO2 + 6HF ^ H2S1F6 + 2 H2O

(1.23)

Water can dissolve the products. Acetic acid is used as it reduces dissolution of niteic acid. Silicon dioxide is etched in diluted HF solution. The etch rate of silicon dioxide solution etchant concentration, agitation, temperature. For Si, the (111) plane has more available bonds per xmit area than the (110) and (100) planes. Therefore, etch rate is slower for the (111) plane. 1.9.2 Dry Etching

In this type of etching, no wet chemicals are used instead plasma is used hence it can be called as plasma etching. Plasma is ionized gas composed of equal numbers of positive and negative charges and a different number of unionized molecules. It is produced when electric field is applied to a gas, causing gas to break down and become ionized. The process is initi­ ated by free electrons that gain kinetic energy from electric field, collide with gas molecules, and lose energy. The energy transfeưed causes the gas molecules to be ionized (i.e., to free elecữons). Free electrons gain kinetic energy from the field, and the process continues. Plasma etching involves chemical reaction combined with physical ion bombardment. Other names: Ion milling, Spat­ ter etching, Reactive ion etching (RIE), Reactive ion beam etching. Oxygen plasma is gen­ erally used for dry etching in semiconductor device fabrication. Dry etching has less etch selectivity than wet etching. This process involves • Etchant species generated in plasma. • Reactant transported by diffusion to surface. • Reactant adsorbed on the surface.

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Chemical reaction (along with ion bombardment) fonns volatile compounds. Compounds desorbed from surface, dỉíĩused into the bulk gas, and pumped out by vac­ uum system.

1 .1 0 M ETALLIZATION AND INTERCONNECTS

In semiconductor process technology, metal refers to a material with very high electrical con­ ductivity. When voltage is applied at the ends of metal, electrons can move around almost freely within the metal. Due to its high conductivity, metal connects on-chip devices. Metal is evaporated on the subsừate and is patterned into wires wherever a connection is needed on an IC. Aluminium is the most commonly used metal. It is the most process-friendly metal and has low resistivity. Its shortcomings include electromigration and insufficient temperature resistance.

Electromigration

In short channel devices, the corresponding cmrent density becomes larger. High current den­ sities can cause device failure as the transport of mass under theinfluence of cuưent takes place. It occurs by the transfer of momentum from the electrons to thepositive metal ions. When high cuưent passes through the metal wires on the IC metal ions in some regions will pile up and voids will form in other regions. The pile up can short circuit adjacent wires while voids can result in open circuit. Copper is the metal of choice for advanced processes. Its resistivity is the lowest among the metals. Compared to aluminium, it has lower resistivity and lower electromigration. However, it is harder to process. Interconnects in high-density IC chips are formed by mul­ tilevel networks. For a typical 90 nm CMOS process, there could be seven or eight levels of metals. Between any two adjacent metal levels, there is a dedicated layer called via that is used to make the necessary connection between the two metals. A via is a hole etched in the interlayer dielectric, which is then filled with metal, usually tungsten, to provide a vertical connection between stacked interconnect metal lines. These concepts are shown in Fig 1.16. The group of metal layers is comprised of the following: (a) (b) (c) (d) (e) (f) (g) (h)

Metal 1, the first level of interconnect Vial, to connect the metal 1 and metal2 MetaI2, the second level of interconnect Via2, to connect the metal2 and metals Metals, the third level of interconnect Via3, to connect the metal3 and metaW Metal4, the fourth level of interconnect Via4, to connect the metaW and metal5

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Fig. 1.16 Scanning electron microscope image showing various metal layers and vias. {Courtesy: Charted Semiconductors, Singapore.)

(i) (j) (k) (1) (m)

Metals, the fifth level of interconnect Via5, to connect the metals and metal6 Metal6 , the sixth level of interconnect Via6 , to connect ứie metal6 and metal? Metal7, the seventh level of interconnect

w is the metal width, H is metal height, and d is the distance between two adjacent, same-layer metal pieces. For a metal piece of length L, the resistance associated with it can be expressed as = p • {LIA), where p is the metal conductivity and A is the area of the cross-section, or A - w ■H. The minimum allowable metal width w and the mini­ mum distance d (metal pitch) are critical process metrics. They are scaled accordingly as CMOS transistors scale down from generation to generation. The gate density of the process is closely related to these parameters. As shown in Fig. 1.17, in a newer process, the metal width w is reduced. Consequently, the associated R increases. To dimmish this effect, tìie metal height H is increased; this results in the high-aspect-ratio metal cross-section. Along with reduced distance d, these high-aspect-ratio metals form perfect parallel-plate capacitors, which increase crosstalk between the electrical signals travelling through these metal lines.

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Metal wires

<

I

Old process

New process

Fig. 1 .1 7 Metal cross-section and scaling.

o As the semiconductor industry advances to even finer process geometries, the problems asso­ ciated with interconnection will become more difficult. Most challenging for interconnection is the introduction of new materials that meet the requừements of wke conductivity and reduced dielectric permittivity (a measure of the ability of a material to resist the formation of an electric field within it). 1 .1 1 ENCAPSULATION (PACKAGING)

A package is the housing of a semiconductor chip. It protects and preserves the performance of the semiconductor devices from electeical, mechanical and chemical corruption or impair­ ment. It also electrically interconnects the chip with outside circuitry. Further, it is designed to dissipate heat generated by the chip. Package design is becommg increasingly significant as well as difficult as device performance, complexity and fimctionality increase with each generation of technology. Structurally, a package is a plastic, ceramic, lammate, or metal seal that encloses the chip or die inside, as depicted in Fig. 1.22. The package can protect the chip from contamination or damage by a foreign material in the environment. It is a medium to host the chip or die on the printed circuit board (PCB). Packages can be classified into two categories, according to the way in which they attach to the PCB (Fig. 1.18). 1. Pin-through-hole (PTH) packages have pins are inserted into through-holes in the board and soldered in place from the opposite side of the board. The through-hole mounting approach offers a mechanically reliable and sturdy connection. However, this comes at the expense of packaging density.

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2. Suiface-mount-technology (SMT) packages have leads that are soldered directly to the metal leads on tìie surface of the circuit board. SMT packages are generally preferred. Packing density is increased for the following reasons: (1) through-holes are eliminated, which provides more wiring space; (2) the lead pitch is reduced; and (3) chips can be mounted on both sides of the board.

'

'

Fig. 1.18 (a)Through-hole mounting (b) Surface mount.

Rent’s rule The number of connections going off-chip tends to be roughly proportional to the complexity of the cữcuitry on the chip. This relationship was first observed by E. Rent of IBM who trans­ lated it into an empirical formula that is appropriately called Rent’s rule. This formula relates the number of inpuưoutput pins to the complexity of the circuit, as measured by the number of gates. P =KxG^

(1.24)

Where K is the average number of I/Os per gate, G the niunber of gates, p the Rent exponent, and p the number of I/O pins to the chip, p varies between 0.1 and 0.7. Its value depends strongly upon the application area, architecture and organization of the circuit. During the IC packaging process, the following operations are performed: • Die attaching Die attaching is the step during which a die is mounted and fixed to the package or sup­ port structure. • Bonding Bonding is the process of creating interconnections between the die and the outside world. • Encapsulation Encapsulation refers to the die being encapsulated with ceramic, plastic, metal, or epoxy to prevent physical damage or corrosion. This term is sometime used sjmonymously with “packaging.”

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There are two di£ferent approaches for IC bonding: • Wire bonding Wire bonding is the technique of using thin wire and a combination of heat, pressure, and/or ultrasonic energy to make the interconnection between the die and package (Fig. 1.19). The wires are made of gold, aluminium, or copper. Wire diameters start at 15 Jim and may increase to several hundred micromeưes tor high-powered applica­ tions. There are two main classes of wire bonding: ball bonding and wedge bonding. In both types, the wire is attached at the ends using some combination of heat, pressure, and ultrasonic energy to make a weld. Figure 1.20 shows the contact points for both ball and wedge bonding. Wire bonding is generally considered the most cost-effective technology, and it is cuưently used to assemble the vast majority of semiconductor devices. * Flip-chip bonding Flip-chip bonding is the t5^ e of mounting technique that does not require any wire bonds. It is the direct electrical connection between the face-down die and the substrate or cừcuit board, through the conductive bumps on the chip’s bond pads. This idea is depicted in Fig. 1.21. The space between the die and the substrate is filled with a non-conductive underfill adhesive. The underfill protects the bumps from moisture or other environmental

Wire

C ontact

points

Fig. 1.19 A wire bonded package. (Courtesy: National Semiconductors Article.)

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Fig. 1.20 (a) Ball bonding (b) Wedge bonding.

hazards and provides additional mechanical sữength to the assembly. However, its most important piưpose is to compensate for any thermal expansion difference between the chip and the substrate. The underfill mechanically locks together the chip and the sub­ strate so that differences in thermal expansion do not break or damage the electrical con­ nection of the bumps. The advantages of the flip-chip technique include small size, high performance, great flexibility and high reliability. Flip-chip packages are smaller because the package and bond wữes are eliminated, thus reducing the required board area and resulting in far less height. Weight is reduced as well.

,/

U nderfill \

D ie (face dow n)

0

F ig . 1.21 Flip-chip bonding and bumps on the die.

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.1 1 .1 Types of Packages uaNn-Une Package

microelectronics, a Dual-in-line package (DIP), sometimes called a DIL package, is an lectronic device package with a rectangular housing and two parallel rows of electrical coll­ ecting pins, usually protruding from the larger sides of the package and bent downward. A DIP is usually referred to as a DIPn, where n is the total number of pins. Refening to Fig. 1.22, for example, a microcircuit package with two rows of seven vertical leads would be a DIP 14. Two types of DIPS are common-ceramic type and plastic moulded type. Plas­ tic moulded DIPs are cheaper. DIPs may be used for integrated circuits (ICs, “chips”), like microprocessors, or for aưays of discrete components such as resistors. Dual-in-line pack­ ages were invented at Fairchild Corporation in 1965 allowing integrated circuits to be pack­ aged more densely than previous round packages, made it possible to build complex systems 1

o

Fig. 1.22 Dual-in-line package. {Courtesy: Motorola).

Fig. 1.23 The pin grid array.

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such as computers. The package was well-suited to automated assembly equipment; a prmtsl circuit board, etc. DIPs were the mainstream of the microelectronics industry in the 1970s and 80s. Pin Grid Array

In pin grid aưay package more pins are provided on one side of the package (Fig. 1.23). Tlie advantage with PGA is high pin density. Signals are routed through the pins through multi­ level layers in the package. The pins are commonly spaced 2.54 mm (O.r) apart. This type of packaging has 300 to 400 pins. 1.12 DESIGN FOR TESTABILITY

During the chip development process, the designers must not only guarantee the chip’s fiinctionality, but they also must ensure its testability for volume production. The extra effort that designers incorporate into the development process for this purpose is called design fo r test­ ability, or DFT. Design for testability is an essential part of any production chip since the IC manufacturing process is inherently defective. If this extra cữcuitĩy of testability is not presented in tíie design, the chip manufacturer cannot confidently deliver the chip to its customer. If a bad part, or mal­ functioning chip, is delivered to a customer and the customer uses this part to build a system and eventually sell this system to end users, the resultant damage could be significant. In vol­ ume production, if bad parts are accidentally delivered to a customer often and exceed certain levels, profits can vanish. The action o f design fo r testability is to add extra circuitry inside the chip so that the chip can be tested after the manufacturing process. If the chip does not behave as expected, it is scrapped (thrown away). Design for testability targets defects in the chip manufacturing process, as depicted in Fig. 1.24. It is not intended fo r discovering functional bugs. In other words, it focuses on the chip’s structural defects, not on logic flaws. Although design for test­ ability cannot completely guarantee the safety of the chips delivered to the customer, it can significantly diminish the defect part per million (DPPM) level. Before the dies are cut from the wafer and sent to the automated test equipment (ATE) for individual testing, they are sub­ jected to preliminary electrical and bum-in testing. Wafer-level testing (Burn-in)

Bum-in is a temperature/bias reliability stress test used in detecting and screening potential early life failures. This is also called as wafer-level testing. Wafer-level testing employs a wafer probe to supply the necessary electrical excitation to the die on the wafer through hundreds or thousands of ultra-thin probing needles that land on the bond pads, balls, or bumps on the die. During the wafer-level testing and bum-in, the electrical bias and excitation requữed by the devices are delivered directly to the interconnection points of each die on the wafer. The required die temperature elevation is achieved by the wafer probe through a built-in hot plate

VLSI Fabrication Technology

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37

IC design

ICfabrication

Defects infroduced during the fabrication process

IC testing

Fig. 1.24 Fabrication errors and testing.

that heats up the wafer to the correct junction temperature. In bum-in, the units are placed on bum-in boards, which in turn are placed inside bum-in ovens. The bum-in ovens provide the electrical bias and excitation needed by the devices through these bum-in boards. Wafer-level testing/Bum-in is a prescreen test. Only parts that pass his test undergo back-end processing (assembly and final test). They also provide additional information on identifying design and process problems.

1.13 FABRICATION OF PASSIVE COMPONENTS 1.13 .1 Resistors

Resistors have been available for use in ICs for many years. Some of these are made in sili­ con, so they are directly integrated with the rest of the IC processes. Usually, resistors in ICs are characterized in terms of their sheet resistance rather than their absolute resistance value. Sheet resistance, Rsheet, is defined as the resistance of a resistive strip with equal length and width (square) so that R sh ee, = J

(ÍÍ/D )

(1.25)

where p is the material resistivity (ilm) and t its thickness (m). Once R s h e e t is given, the result­ ing resistor value is obtained by multiplying the number of squares that can be accommodated in the strip.

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VLSI Design

Integrated Semiconduđor Resistors

In this category, the existing semiconductor is used as the resistive material. The resistor mof be fabricated at a number of stages during the IC process giving rise to different resistors whh different characteristics. Some of the most common are discussed below. Diffused Resistors

These can be formed during either the base or emitter diffusion of a bipolar process. For an npn process the base diffusion resistor is a p-type of moderate sheet resistivity typically in the range of 100-200 Qm. This can provide resistors in 50-10 k£2 range. The heavily doped n+ emitter diffusion will produce an n+-type resistor with low sheet resistivity of 2 - 1 0 ilm. This can provide resistors with low values in 1-100 Q range. Since a diffusion resistor is based on a p-type base over an n-type epitaxy or an n+-type emitter over a p-type base, it is essential that the formed p-n junctions are always reverse-biased to ensure that current flows in the intended portion of the resistor. The presence of such a reverse-biased p-n junction also introduces a distributed capacitance from the resistor body to the substrate. This will cause high-frequency degradation whereby the resistor value drops from its nominal design value to a lower impedance value due to the shunting capacitance. Pinched Resistors

Variation to the diffused resistor that is used to increase the sheet resistivity of base region is to use the n+-type emitter as a means to reduce the cross-sectional area of the base region, thereby increasing the sheet resistivity. This can increase the sheet resistance to ~1 kilm. In this case, one end of the n+-type emitter must be tied to one end of the resistor to contain all cuưent flow to the pinched base region. Epitaxial Resistors

High resistor values can be formed using the epitaxial layer since it has higher resistivity ứian other regions. Epitaxial resistors can have sheet resistances around 5 kflm. However, epitaxial resistors have even looser tolerances due to the wide tolerances on both epitaxial resistivity and epitaxial layer thickness. MOS Resiston

A MOSFET can be biased to provide a non-linear resistor. Such a resistor provides much greater values than diffused ones while occupying a much smaller area. With the gate short­ ened to the drain in a MOSFET, a quadratic relation between cuưent and voltage e x ists and the device conducts cuưent only when the voltage exceeds the threshold voltage. Under these circumstances, the current flowing in this resistor (i.e., the MOSFET drain cuưent) depends on the width to length ratio of the channel. Hence, to increase the resistor value, the aspect

VLSI Fabrication Tethnology

a -

39

ratio of the MOSFET should be reduced to give a longer channel length and naưoxver chan­ nel width. Thin-Film Resistors

A resistive thin-film layer can be deposited (e.g., by sputtering) on the substrate to provide a resistor with very tight absolute value resistance. In addition, given a large variety of resistor materials a wide range of resistor values can be obtained in small footprints, thereby having very small parasitic capacitances and small temperature coefficients. Some common thin film resistor materials include tantalum, tantalum nitride, and nickel-chromium. Unlike semicon­ ductor resistors, thin-film resistors can be laser trimmed to adjust their values to very high accuracies of up to 0.01%. Laser trimming can increase the resistor value since the fine beam evaporates a portion of the thin-film material. By its nature, laser trimming is a slow and costly operation that is justified when very high accuracy on absolute values is necessary. 1.13 .2 Capacitors

Most integrated capacitors are either junction capacitors or MOS capacitors. Junction Capacitors

A junction capacitor is formed when a p-n junction is reversed-biased. This can be formed using the base-emitter, base-collector, or collector-substrate junctions of an npn structure in bipolar ICs. Of course, the particular junction must be maintained in reverse bias to provide the desired capacitance. Since the capacitance arises from the parallel plate effect across the depletion region, whose thickness in turn is voltage-dependent, the capacitance is also voltagedependent decreasing with increased reverse bias. The capacitance depends on the reverse volt­ age. The base-emitter junction provides the highest capacitance per unit around 1000 pF/mm^ with a low breakdown voltage (~5 V). The base-collector junction provides ~100 pF/mm^ with a higher breakdown voltage (-40 V). M05 Capacitors

MOS capacitors are usually formed as parallel plate devices with a top metallization and the high conductivity n+ emitter diffusion as the two plates with a thin oxide dielectric sand­ wiched in between. The oxide is usually a thin layer of SÌO2 with a relative dielectric constant 8r of 3-4 or SÌ3N4 with Er of 5-8. Since the capacitance obtained is £o£r^/ioxide, the oxide thick­ ness /oxide is critical. The lower lim it o n the oxide thickness depends o n the process yields and tolerances as well as the desired breakdown voltage and reliability. MOS capacitors can pro­ vide around 1000 pF/mm^ with breakdown voltages up to 100 V. Unlike junction capacitors, MOS capacitors are voltage-independent and can be biased either positively or negatively. Their breakdown, however, is destructive since the oxide fails permanently. Care should be taken to prevent overvoltage conditions.

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1 .1 4

VLSi Design

PROCESS FLOW FOR SELF-ALIGNED nMOSFET

Explanation

(a) The wafer siirface is subjected to chemical cleaning process so that all the impurities are removed. A thin layer of silicon dioxide is grown over which another layer of SÌ3N4 is deposited. This layer acts as a buffer and reduces strain on the lattice of the substoate. Photoresist is coated over the surface. (b) The photoresist is patterned so that the active device is protected by it. Active device area is the area where channel exists in the device, i.e., w X L. Boron is implanted to prevent surface inversion in the non channel areas (self aligned channel stop). (c) Boron is implanted in the channel area for threshold voltage adjustment. (d) Good quality thin oxide is grown and polysilicon is deposited and patterned. (e) Arsenic is doped to create source and drain areas. (f) Glass is deposited to create passivating layer on the substrate. (h) Glass is patterned (cut) in source and drain areas. Metal is deposited in source and drain areas and patterned to make contacts from these areas.

A rsenic im plant

c

s

ị Source

(e)

Boron field im plant

V

Drain

- Flow ed P -glass

i l L

n A ctive device area (b) Boron channel im plant

— i t

i —

G ate oxide

- Field oxide , Self-aligned channel stop

(c)

G ate Patterned polysilicon gate

'V—

—C

r~p

m 3

r i

-

Ỉ Source

Drain

—

i

Hn T — 1............

(d) (h)

Fig. 1.25 Process flow for self-aligned nMOSFET.

r -

t

— A ctive device area

VLSI Fabrication Technology

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41

1.15 PROCESS FLOW FOR CMOS FABRICATION-TWIN TUB PROCESS Device Structure and Basic Fabrication Process Steps Complementary MOS (CMOS) was first proposed by Wanlass and Sah m 1963. Although the CMOS process is more complex than ttie nMOS process, it provides both n-channel (nMOS) and p-channel (pMOS) transistors on the same chip and CMOS circuits can achieve lower power consumption. Consequently, the CMOS process has been widely used as an VLSI fab­ rication process. Figure 1.26 shows the structure of a CMOS device. Each “FET” consists of gate electrode, source, drain and channel, and gate bias controls earner flow from source to drain through channel layer. Explanation of process flow (k) The first process step is the formation of p tub and n tub (twin tub or twin well) in silicon substrate. Because CMOS has two types of FETs, nMOS is formed in p tub and pMOS in n tub. (b) Thick field oxide is formed to separate each MOSFET active area in the same tub. (c) After that, impxirity is doped into the channel region to adjust the threshold voltage, Vth, for each type of FET. (d) Gate insulator layer, usually silicon dioxide (SÌO2), is grown by thermal oxidation, because the interstate density between SÌO2 and silicon substrate should be small. (e) Polysilicon is deposited as gate electrode material and gate electrode is patterned by reactive ion etching (RIE). Gate length Lg, is the critical dimension, because Lg

n-channel p-channel Gate elecữode

Field oxide

Fig. 1.26 Cross-sectional view of CMOS.

42

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VLSf Design

determines the performance of MOSFETs Mid it should be small to improve die dtàỉdl performance. (f) Impurity is doped in source and dram regions of MOSFETs by ion implantati
1. The mainstream process technology used in today’s chip design/manufac­ turing environment is complementary metal oxide semiconductor (CMOS) technology. 2. Silicon crystal growth, Wafer cleaning, Oxidation, Photolithography, Diffiision, Ion implantation. Dry etching, Wet etching, Plasma etching. Thermal treattnents (rapid thermal annealing, furnace annealing, and oxidation), Chemical-vapour deposition, Physical-vapour deposition, Molecular beam epitaxy. Electrochem­ ical deposition. Metallization, Chemical-mechanical planarization, Wafer test­ ing, Wafer back grinding, Wafer mounting. Die cutting. Encapsulation are the important steps in fabrication of chips. 3. An IC fabrication requires a clean processing room. 4. Oxidation is done for gate oxide formation, field oxide for isolation, passive layers over the substrate. 5. Photoresist is used in lithographic process to transfer patterns from mask to the substrate. 6 . Diffusion and ion implantation are used to introduce dopants into the semiconductor. 7. Etching is done to remove unwanted areas on the semiconductor surface. 8 . Metallization is done for fabricating wires, contacts, etc. 9. CMOS fabrication is done using n-well or p-well or twin tub process. Various complex steps are involved in the process. 10. Packaging should take care of electrical and mechanical specifications into consideration. 11. Wafer-level testing is done before shipping the chips.

VLSI Fabrication Technology

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43

1. T h e_______ of the VLSI chip ranges from pre-assembly wafer preparation to fabrication technologies for the packages that provide electrical connections and mechanical and envừonmental protection. 2. Through-hole mounting is used in _______package. 3. The process technology presently used in chip design i s ________. 4. In present CMOS technology, ttie type of gate used i s _______ . 5. The second most abundant element available on earth i s _______ . 6 . The type of silicon requữed to fabricate IC i s _______ . 7. Photolithography is done in _______ . 8 . The implantation dose Qo is given by the expression. 9. Common dielectric used for isolation of devices is _ 10. The orientation of the wafer which produces electrically cleaner oxide inter­ face i s _______ . 11. Dry etching is also known a s _______ . 12. Dual-in-line package is sometimes called a s _______ package. 13. In MOS resistors to increase the resistance value the aspect ratio of MOSFET should b e _______ . Answers 1. 2. 3 4. 5. 6. 7.

Packaging Single inline CMOS Polysilicon Silicon Electronic grade silicon Clean rooms 8 Jtlq 9. Silicon dioxide 1 0. <100> 11. Plasma etching 12 DIL 13. Reduced.

Basic Electrical Properties of MOS, BiCMOS Devices

CHAPTER

CHAPTER OBJECTIVES In this chapter, you will be introduced to • • • • • • • • •

Operation and characteristics of MOSFET Threshold voltage of MOSFET Leakage cuưents in MOSFET Transconductance, output conductance and figure of merit of MOSFET Pass transistor logic nMOS inverter and its characteristics CMOS mverter and its characteristics BiCMOS inverters Latch up in CMOS devices

2.1 INTRODUCTION OF MOSFET The rapid strides of the semiconductor industry in recent years are due to its ability to incorpo­ rate more and more devices operating at higher and higher speeds in an IC. Metal Oxide Field Effect Transistor (MOSFET) cừcuits occupy less silicon area and consume less power than theữ bipolar counterparts (BJT) making them ideal choice for VLSI circuits. The MOSFET was the subject of a patent in 1933, but did not reach commercial maturity until about thirty years later. The delay was principally due to a lack of understanding of the importance of the oxide/semiconductor interface, and to the time taken to develop suitable fabrication procedures notably for the growth of the thin gate oxide.

46

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VLSI Design

In fact, the MOSFET is by far the mostly used in fabrication of central processii^ (CPU) and memories in computers, digital signal processors (DSPs) for communicatioii PD*-^ poses and ICs for a variety of other applications. In this chapter, we shall discuss the openl. ing principles of MOSFETs and develop a basic model for theừ current-voltage charactoislks. Later we proceed towards the study of CMOS (Complementary Metal Oxide Semiconductor) technologies. Figure 2.1 shows the symbolic notations of the MOSFET’s. G s—

— D B

nMOS

pMOS

Fig. 2.1 Symbols used at the circuit level.

MOSFET has four terminals out of which three are signal terminals gate (G), source (S), and drain (D) plus the bulk terminal. Basically, there are two types of MOSFET’s • Enhancement mode MOSFET • Depletion mode MOSFET 2.1.1 Physical Structure of a MOSFET (The Enhancement Mode)

Gate Source

Bulk Fig. 2.2 MOS structure.

Bask Electrical Properties of MOS, BiCMOS Devices

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47

Referring to Fig. 2.2, • MOSFET’s are made from ciystallme semiconductor that forms the host structure called the substrate or bulk of the device. Substrate for nMOS is p-type silicon whereas for the pMOS devices it is n-type silicon. • The thin oxide of the transistor electrically isolates the gate from the semiconductor underneath. The gate oxide is made of oxidized silicon foraiing non-crystalline, amor­ phous SÌO2. The gate oxide thickness is typically from near 15 Â to 100 Â. • Drain and soiưce regions are made from crystalline silicon by implanting a dopant with opposite polarity to that of the substrate. In pMOS, boran impurities are doped and in nMOS phosphorous impurities are doped. The gate is fabricated using polysilicon or metal. Since drain and drain dopants are made of opposite polarity to the subsfrate (bulk) they form pn junction diodes that are reverse biased in normal operation of the device. This is shown in the Fig. 2.3. • The gate is the control terminal and the source provides the electrons (nMOS) or holes (pMOS) that are collected by the drain. • The distance from drain to source is a geometrical parameter called channel length (Z,) where the conduction takes place. Another geometrical parameter of the device is transistor channel width (W). These two parameters are set by the circuit engineer. • Other parameters such as oxide thickness, threshold voltage and doping levels depend on the fabrication process and cannot be changed by the design. They are technology parameters. • Complementary Metal Oxide Semiconductor (CMOS) logic cừcuits have both nMOS and pMOS devices which will be discussed later in this chapter.

Drain

Source

Source

Drain

hiầiip^^pé/^ Fig. 2.3 Cross-sectional view of nMOSFET and pMOSFET.

2.1.2 Understanding Enhancement Mode MOSFET Operation: A Desaiptive Approach Transistor terminals must have proper voltage polarity to operate coưectly. In MOSFETs, the terminal voltages are usually reíeưed with respect to the source. The same convention will be followed in this chapter, i.e., the model equations will be developed with respect to Vgs Vds, and VsB- The positive convention cuưent in nMOS (pMOS) device is from drain (source) to the source (drain) and is referred as Ids or I d - When a positive (negative) voltage is a p p lie d to the drain terminal; the drain cuưent depends on the voltage applied to the gate control tenninal.

48

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VLSI Design

2 . 1.2.1 Off State or Non-conducting State

The MOSFET consists of two pn junctions connected back to back. If Vgs is zero, thai m applied drain voltage reverse biases the drain-bulk diode (Fig. 2.3) and there are no ftee charges between the drain and the source. As a result there is no current when V g s = 0 ftp nMOS devices (the same hold for pMOS devices). This is off ơr non-conducting state of fte transistor. That is no channel or conducting path is formed when Vos = 0. 2.1.2 .2 Ohmic or Non-saturated state

• When the gate terminal voltage of an nMOS (pMOS) transistor is slightly increased (decreased) due to the positive charge (negative charge) that is placed on the gate a verti­ cal electric field exists between the gate and the substrate across the oxide. • In an nMOS (pMOS) transistors the holes (elecữons) of the p-type (n-type) substrate which are close to the silicon dioxide interface initially feel this electric field and move away from the interface due to repulsion. As a result, a depletion region forms beneadi the oxide interface for this small gate voltage. The depletion region contains no mobile earners so the application of drain voltage provides no drain cuưent smce the free Cfflriers don’t exist in the channel. If the gate voltage of the nMOS (pMOS) transistor is further increased (decreased), then the vertical electric field is strong enough to attract minority caưiers (electrons in the nMOS transistor and holes in pMOS transistor) from bulk towards the gate. These minority carriers are attracted to the gate but the silicon dioxide as it is an insulator stops them and the electrons (holes) accumulate near the sili­ con oxide interface. They form a conducting sheet of minority mobile carriers near the surface. (Electrons in p-type bulk of nMOS device and holes in pMOS device in n-typc bulk). These caưiers form the inversion region or the conducting channel. Formation of channel is equivalent to a short circuit to the drain/source-bulk diodes. Figure 2.4 shows clearly the depletion region and channel formation.

Fig. 2.4 nMOS transistor for positive V g s , showing depletion region and induced channel.

Basic Electrical Properties of MOS, BiCMOS Devices

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49

2.1.2.3 Threshold Voltage

• Since the drain and source are at the same voltage the channel carrier distribution is uniform along the device. The voltage at which the surface of the semiconductor gets inverted to the opposite polarity is known as Threshold voltage. In nMOS transistor, the surface will be inverted to n-type (remember in nMOS bulk is p-type silicon) and for pMOS transistor the surface will be inverted to p-type (remember in pMOS bulk is n-type silicon). At the threshold voltage condition, the concenfration of electrons (holes) accumulated near the surface in a nMOS (pMOS) is equal to the doping concentration of the bulk doping concentration. Threshold voltage for nMOS is always positive and threshold voltage fo r pMOS is always negative. • An nMOS (pMOS) transistor has a conducting channel when the gate-source voltage is greater than (less than) threshold voltage, i.e., Vgs > v,„ (Vos < Vtp)Let^s discuss in detail about the threshold voltage of an nMOSFET. In a MOSFET since all terminal voltages are applied with respect to the source the thresh­ old voltage is also measured with respect to source. The threshold voltage o f a MOSFET is defined as the value o f gate to source voltage which is sufficient to produce a surface inversion layer when V])S = 0 V. or The voltage at which the surface o f the semiconductor gets inverted to the opposite polar­ ity is known as threshold voltage. VsB is applied to the MOSFET and is always positive or greater than zero. VsB is applied to keep the pn junctions in the MOSFET reverse biased so that no substrate current flows in the device into the bulk/substrate. For a MOSFET the surface is inverted (channel is formed) when the surface potential is Ti = l^B + VsB- The formula for threshold voltage is given by (2 .1)

^OX VfB = flat band voltage equal to (ị)mí ^ms = work function difference between gate and substoate Na = substrate doping concentration ệe = energy difference between the Fermi level and intrinsic Fermi level in the semicon­ ductor (silicon here) or Fermi voltage C ox = oxide capacitance per unit area given by Gox/tox where tox is the thickness of the oxide. The surface gets inverted when the surface potential = 2<^B + VsB in case o f a MOSFET Vth is a function of several components, most of which are material constants such as the differ­ ence in work function between gate and substrate material, the oxide thickness, the Fermi voltage. Apart from them the parameters shown below will also show theừ effect on ứie threshold voltage.

50

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VLSI Design

• If in the fabrication process some charges (sodium ions through human sweat, elcẠ ữapped in ứie gate oxide, threshold voltage is altered as they show theữ reaction to die vdfage applied to the gate. For example, if some positive ions are fixed in the oxide, tbe anMuiit of positive charge required near the gate terminal to mvert the surface decreases, hoiee threshold voltage decreases. If Qf is the charge in the oxide, the amount of extra voltage to be applied to ứie gate to neutealize these charges is given by - (Qf/Cox)• Once the MOSFET is fabricated and if the threshold voltage has to be adjusted (increase or decrease) the only solution is to implant the dopants near the surface. This is known as threshold voltage adjustment implant and is given by Vjj = qDj/Cox- qDi is ứie cbaige implanted in the channel per unit area. • The final expression with the above two effects included is given by , P q N A S s i ( 2 ^ b + ^sb)

Q f

, qD i

v,h = Vfb + 2(Ị)g + ---------- ------------------ —^ + ^ ^OX ^ox ^ox

(2 .2)

Body effect parameter (y) Equation (2.2) shows that when VsB - 0 the threshold voltage reduces for the MOSFET reduces to that for the coưesponding MOS capacitor. The effect of VsB on the threshold voltage can be expressed through the relation (2.3) ầVth = change in threshold voltage due to the application of subsữate bias. Y is called the body effect parameter given by

^OX

,2.4)

From the above equation, we see that the body effect which is change in v,h due to subsưate bias is more pronounced in MOSFETs with higher Na and toxFor a typical longchannel nMOSFET when the channel forms inthe nMOS (pMOS) ứansistor, a positive(negative) drain voltage with respect to the source createsa horizontal elec­ tric field, moving the elecfrons from source towards the drain forming a positive (negative) drain current. If the horizontal electric field is of same order or smaller than the vertical one, the inversion channel remains almost uHifonn along the device length. This happens when Vds < (Vgs- Kn) for nMOS transistor ^DS > {Vgs - Vtp) for pMOS transistor

(2.5)

The above threshold current in MOSFETs is primarily drift cuưent. The inversion layer behaves as a resistance and as Vos is increased initially from 0 V, the drain current IDS mcreases linearly. Note: Threshold voltage is generally denoted by V,, If it is for nMOSFET we denote as Vm and if it is for pMOSFET, we denote by v,p

Basic Electrical Properties of MOS, BiCMOS Devices

a

51

In this condition, tlỉe vertical elecfric field dominates the horizontal one. The transistor is in its linear region and is known as ohmic or non-saturated region. This is shown in Fig. 2.5(a). 2.1.2.4 Saturation Region

Ultimately when V os = Vogat, the voltage across the oxide near the drain end is no longer suf­ ficient to support the channel (inversion layer), i.e., the horizontal electric field becomes spon­ ger than the vertical electric field at the drain end. The conducting channel retoacts from the drain and no longer “touches” diis terminal. When this happens the inversion channel is said to be “pinched off” and the device4s in the saturation region. This is shown in Fig. 2.5(b). In this region the pinch off point moves towards the source as V ps increases. The voltage at the pinch off point remains Vosai- The extra voltage V d s - Vosat is now dropped in the deple­ tion region. The electrons which reach the pinch off point are swept across to the dram by the elecưic field in the depletion region. The curreat in the saturation region remains almost fixed as the voltage across the inversion layer is fixed at VDsat- A small increase in the cuưent is observed due to the shift of pinch off point towards the source end, which effectively reduces the cỉmnnel length of the MOSFET from L to Ư as shown in Fig. 2.5(c). The conditions for pinch off is - Vt„)

for nMOS transistor

V ds < {V g s - Vip)

for pMOS transistor.

Vd s > {Vg s

■5

Vos
Id

/ Depletion region (a) ^c.v

(2.6)

'Vds

Ự - y

Depletion region (b)

Depletion region

Fig. 2.5 Various regions of operation of MOSFET (a) ohmic region (b) onset of saturation region (c) saturation region.

52

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VLSI Design

The behaviour of MOS transistor in different operation regions is best understood by anaỊyn sis of its cuưent voltage characteristics. The following chart in Fig. 2.6 shows tìie bdi3viov of an nMOSFET whose channel length L is 10 fim. 6

10-'*

Vas=2.5V ^' s *^ // / Saturation

Vds- Vgs5 4

Resistive

y

Fc,= 2 .ov

/

^DS 3

/

2

Kc5=1.5V

/

1 0

0

Ka5 = l o V 0.5

1.5

2.5

Fig. 2.6 l-V characteristics of long channel nMOSFET for various Vfis values.

All the derived equations hold for ứie pMOS transistor as well. The only difference is that for pMOS devices, the polarities of all voltages and currents are reversed. This is illustrated in Fig. 2.7, which plots ứie I d s - V d s characteristics of a minimum-size pMOS transistor of L = 0.25 Jim process. The curves are in the third quadrants I d s , V d s , and Vos are all negative.

''DS Fig. 2.7 l-V characteristics of long channel pMOSFET for various I^GSvalues.

Basic Electrical Properties of MOS, BiCMOS Devices

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The mobility of holes in silicon is typically lower than that of the electrons. This means that pMOS fransistors provide less current ứian nMOS transistors of comparable size and hence are slower. 2 . 1.2.5 Current Equations ofMOSFET in Various Regions of Operation

Let us discuss a first order (ideal Shockley) model relating the ciurent and voltage for an nMOSFET in ohmic or nonsaturated regions. • In a cut-off region (Vos < Vi„) there is no channel and almost zero cuưent flows from drain to source. • In other regions, tíie gate attracts carriers (electrons) to form the channel. The electrons drift (drift current means current under the influence of the electric field) from source to drain at a rate proportional to ứie electric field between tíiese regions. Thus, we can compute ứie currents if we know ứie amount of charge m ữie channel and tìie rate at which it flows. We know that the charge on capacitor’s plate is Q = cv. Thus, the charge in the channel Q chcm nel

IS ( 2 .7)

Q c h a n n e l= C g { V G C -V t„ )

Cg is capacitance of gate to the channel; Vac - Vm is the amount of voltage attracting charge to the channel beyond threshold voltage. If the source is at Vs and drain is at Vp, the average is (2 . 8) Let us do a small calculation, i.e., addmg and subtracting Vs r s + V s - Vs*Vo ‘^

(2 .9 )

2

2

Therefore, the mean difference between gate and channel potentials is Vac = Vg c = V g - V c = Vg -

Vs +

= Vg -V s -

Vd s '

2

Vgd)/2

from (2.9)

Vd^ 2

= Vg s - ^

(2 . 1 0 )

We can model the gate as a parallel plate cqjacitor with capacitance proportional to area over ứiickness. If the gate has length L and width w and oxide thickness is tox, the capacitance is given by ^ WL C g= £ox^ ^OX

(2 . 1 1 )

where &0 X= 3.9 £o for silicon dioxide and Eo is the permittivity of free space which is 8.85 X 10^ F/cm.

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VLSI Design

Consider the Fig. 2.8 given below. Polysilicon gate

__ SiOj gate oxide (good insulator, £ =3.9) Fig. 2.8 MOSFET.

Each carrier in the channel (here electrons) is accelerated to an average velocity propor­ tional to the lateral electric field, i.e., lateral electric field between the source and the drain. The constant of proportionality is known as mobility of the carriers. As electrons are caniets here, we write |J. as JI;, (2.12)

The electric field E is the voltage difference between drain and source channel length. Vds £ =■

Vd s

divided by the (2.13)

The time required for the carriers (electrons) to cross the channel is the channel length divided by the carrier velocity. t = L lv

(2.14)

Therefore, the cuưent between drain and source Vos is the total amount of charge in the channel divided by the time required to cross the channel Id s

=

ỈDS =

Ổ cbannel

(2.15)

^ ch an n el

(2.16)

L /v

We know Qchannei - Cg (Voc~ Vin) and substituting the value of V g c in the equation, and substituting the values of we obtain L and V from equations 2.11 and 2.13 we obtain the below expression for Id s DS/

Vd s

(2.17a)

Basic Electrical Properties of MOS, BiCMOS Devices

a

55

The equation can be rewritten as I ds =P Vg s - V ^ - V ds/

w

Vd s

where p = \L„Cox -J -

(2.17b)

Eqiiation 2.17(a) describes the linear region of operation for V g s > Vtn h\ii Vds is very small. I d s increases almost linearly with just like an ideal resistor. The geometry and tech­ nology parameters are sometimes merged into a single factor. This symbol is not the same as symbol used for ratio of collector to base current in a bipolar ừansistor. When V ds is further increased, at the value of Vds = V g s - Vtn the drain cuưent begins to become constant. This voltage is known as saturation voltage Vosat- At this point the IR drop m the device equals the effective gate to channel voltage at the drain. If Vos is further increased beyond V o sa h Id s becomes constant. The channel pinches off from drain towards source with the increase of Vos beyond V osat- Substituting the value of V d sm = V g s - f w in equation 2.17(b). I ds = P

o

Vgs - Vt„ - Vdsoí/

^Dsat (2.18)

P. It is sometimes convenient to define i.e., V g s = V d s = V d d (supply voltage)

lo sat

as the cuưent of the transistor that is fully ON,

(2.19)

lD S = \ { V D D - V , n f

SUMMARY: Shockley 1st order transistor models 0 Ids -

VGS-Vrn-Vosỵ^ ^ {Vgs

- v,„ f

Vg s Vd s

< Vt

^d s < Vosat

Vds

^ Vosat

cutoff linear

(2 .20 )

saturation

2.1.3 Understanding the Depletion Mode MOSFET Operation Depletion mode MOSFET is normally continuous ON device. The depletion mode MOSFET has a naưow n-channel buried between the source and drain near the surface (in case of nMOSFET), i e n-types dopants are unplanted near the surface. Free elecứons are available in the channel area. With Vos = 0 a negative gate voltage attracts holes from the bulk into the channel near the surface. The recombination of induced holes with the existing elecứons (from the buried channel) causes depletion of majority carriers. This action is responsible for its name as depletion mode MOSFET. If the gate voltage is made more negative majority carriers can be vừtually depleted and channel is eliminated. The device is off in this condition. Under ứiese cữcumstances drain

56

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VLSI Design

current is zero. The least negative value of Vos for which channel is depleted is known as tfnesfaold voltage Vth of the MOSFET. • With V g s = 0 the application of positive Fx)5 produces appreciable drain current ghm by Jds- As Fgs decreases downwards the threshold the drain cuirent decreases. At a fixed Vgs increasing values of Vũs cause the drain cuưent to saturate as the channel is pinched off. The reasons for this are similar to what causes saturation in enhancement devices. Because of the potential drop along the channel due to ỈŨS the region of the channel near the drain is depleted more than the region near the source. Depletion mode MOSFET exhibit both ohmic and saturated regions. In depletion nMOS V(„ is negative. • The cuưent equations are same as those for enhancement mode device in both ohmic and saturation regions (akeady as discussed above in this chapter). • A depletion mode MOSFET can also be used in enhancement mode. It is only necessaiy to apply a positive gate voltage so that the negative charges are induced in the channel enhances the number of majority carriers already implanted in the channel area. Thus, for positive Fas the drain cuưent is more than the current in enhancement mode device. This is shown in the following Fig. 2.9.

Note: channel exists when ^C5=0

n-type impli impurities

Fig. 2.9 Depletion mode MOSFET.

c 2

Q

Drain-to-Source Voltage (F^,) V Fig. 2.10 l-V characteristics.

Basic Electrical Properties of MOS, BiCMOS Devices

o

57

^ What is channel length modulation? When the drain voltage exceeds Vpsat the pinch off point (also called as velocity saturation point) moves from the drain towards the source and a depletion layer exists between ứiis point and the drain. This movement is referred as channel length modula­ tion. Considering channel length modulation, the drain cuưent is given by the relation Id = |(F g s - Kmf (1 + XV d s )

(2 .2 1 )

where X is channel length modulation parameter. ^ When the channel is pinched off near the drain end, there is no physical channel between the pinch off point and drain end. But the current remains constant. How does it happen? Alứiough there are no inversion charges at the drain end of the channel at the pinch oif point, the drain region is electrically active. Carriers drift from the source and move under the effect of the horizontal electric field. Once they anive at the pinch off point of the channel they fravel from that point to the drain driven by the high electric field of the depletion region. This is drift cuưent in the device which is almost constant. ^ Write down the importance of threshold voltage in a MOSFET and how is it dependent on oxide thickness, and doping concentration of the substrate. The threshold voltage of a MOSFET is usually defined as the gate voltage where an inversion layer forms at tíie interface between the insulating layer (oxide) and the substrate (body) of the transistor. It is given by

^OX Threshold voltage depends on the choice of oxide and on oxide thickness. Usmg the formulas above, Vt„ is directly proportional to y, and tox, which is the parameter for oxide thickness. Thus, the thinner the oxide, the lower the threshold voltage. The threshold voltage increases with the ũicrease in the N a since the potential drop across oxide and surface both increase. ► What is subthreshold leakage current? Subthreshold leakage or subthreshold conduction or subthreshold drain cur­ rent is the current that flows between the source and drain of a MOSFET when the transistor is in the subthreshold region, i.e., for gate-to-source voltages below the threshold voltage.

58

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VLSI Design

In the past, the subthreshold conduction of ữansistors has been veiy small, but as transistors have been scaled down, leakage from all sources has increased. For a tech­ nology generation with threshold voltage of 0.2 V, leakage can exceed 50% of total power consumption. The amount of subtìireshold conduction is set by the threshold voltage, which sits between ground and the supply voltage, and so has to be reduced along with the supply voltage. Subthreshold conduction varies exponentially with gate voltage and becomes more and more significant as MOSFETs shrink in size.

2.1.4 Leakage Current Problem in the MOSFET Power consumption is now the major technical problem in the semiconductor industry. There are two principle sources of power dissipation in today’s CMOS-based VLSI cừcuits: dynamic and static power. Dynamic power, which results from transistor switching and repeated charg­ ing and discharging of the capacitance on the outputs of millions of logic gates on chip, is the energy consumed by the chip to produce a useful outcome. Static power refers to the leak­ age cuưent that leaks through transistors even when they are turned off. It is the power ứiat is dissipated through transistors without producing any useful operation. Until very recently, only dynamic power has been a significant source of power consumption. However, as process geometries continuously shrink, smaller channel lengths have exacerbated the leakage prob­ lem. In particular, as process technology advances to the sub 0.1 fim regime, leakage power dissipation increases at a much faster rate than djTiamic power. Consequently, it begins to dominate the power consumption equation. For deep submicron MOSFET fransistors, there are six short-channel leakage mechanisms, as illusttated in Fig. 2.11.

Source

Drain

Fig. 2.11 The leakage current mechanisms in MOSFET transistors.

Basic Electrical Properties of MOS, BiCMOS Devices

• • • • • •

a

59

II is the reverse-bias p-nj\mction leakage. is the subthreshold leakage or die weak inversion cuưent across the device. 13 is the gate leakage or the tunnelling cmrent through the gate oxide insulation. 14 is the gate current due to hot-carrier ữỹection. 15 is gate-induced drain leakage (GIDL). 16 is the channel punch through ciirrent.

12

Among these currents, 12,15, and 16 are off state leakage mechanisms since they only exist when the transistor is in off state. II, 13, and 14 can occur on both on and off states. The leakage currents are influenced by threshold voltage, channel dimensions (physical), channel/siirface doping profile, drain/soxirce junction depth, gate oxide thickness, and VddCmxently, the two principle components of static power consumption are the subthreshold leakage 12 and gate leakage Ỉ3. Most of the operations of modem VLSI chips can be classified into two modes; active and standby. During the active mode of cữcuit operation, the total power dissipation includes both the dynamic and static portions. While in the standby mode, the power dissipation is due to only the standby leakage cmrent. Dynamic power dissipation consists of two components. One is the switching power due to the charging and discharging of load capacitance. The other is short-circuitmg power due to tìie non-zero rise and fall time of input waveforms. The static power of a CMOS cữcuit is only determined by the leakage cuưent through each transistor. In other words, dynamic power is related to the circuit switching activity. In contrast, static power is proportional to the total number of transistors in the circuit regardless of their switch­ ing activities. In general, dynamic power dissipation is expressed as Pdyn = afCVpD^, where a is the cữcuit switching activity, / is the operation frequency, c is the load capacitance, and Vdd is the supply voltage. In the past several decades, as CMOS devices scaled down, supply voltage Vdd also been trimmed down to keep the power consumption under control (since the power usage has quadratic dependence on Vdd, according to the equation). Accordmgly, the toansistor ứưeshold voltage has to be commensurately scaled to mamtain a high drive current and achieve performance unprovement. However, this threshold voltage scaling also results in a substantial increase in subửureshold leakage current. Consequently, leakage power becomes a sigjiificant component of ứie total power consumption in both the active and standby modes of operation. To suppress the power consiunption in deep-sub micrometre cữcuits, it is nec­ essary to reduce the leakage power in botìi the active and standby modes of operation. The reduc­ tion in leakage current can be achieved using both process-level and cừcuit-level techniques. At the process level, leakage reduction can be achieved by controlling the dimensions (length, oxide thickness, and junction depth) and doping profile in transistors. At the circuit level, threshold voltage and the leakage current of transistors can be effectively controlled by controllmg the voltages of different device termmals (drain, source, gate,, and body or sub­ strate). In practice, several circuit design techniques have been suggested for leakage reduction in digital circuits (logic and memory), such as transistor stacking, multiple Vfh, dynamic VthIf care is not taken, leakage power can lead to dramatic effects that may cause a circuit to fail to function properly. Large leakage ciưrent can increase the standby power dissipation to an imacceptable level or it can lead to excessive heating, which consequently requires complicated

60

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VLSI Design

and expensive cooling and packaging techniques. In the beginning, only leading edge mionprocessors were affected by this leakage current problem, but now leakage current has becone a critical design parameter for all ứie nanomefre chips. In summary, for modem VLSI chqi design, the issue of confrolling leakage cvurent has moved from backstage to centre stage. 2.1.5 A.C. Properties: Transconductance, Output Conductance and Figure of Merit of a MOSFET Definitions The incremental resistances, transconductance and capacitances govern the a.c. properties of theMOSFET. The ừansconductance is defined by Sm =

constant Vds aVos The small signal conductance or output conductance g j is given by BIds Sj at constant Fas

(2.23)

(2-24)

Linear region parameters and their importance in circuit performance When the MOSFET is biased in linear region where Vds is small the conductance g j is obtained by differentiating equation 2.24 with respect to Vds We know that I ds = ịínCox Y u c

Therefore, g j = ^

(2.25)

w

^ — i^GS - K r , - ^DS) and in linear region Yds «

{Vos - fm) the above

equation simplifies to g ,= ^ ^ ^ ^ ^ {V G S -V ,„ -V o s)

(2.26)

Present day VLSI circuits are MOSFET based as already discussed. The performance of the circuit depends on switching speed which in turn depends upon the parameter known as ON resistance given by

To decrease the Ron the width of the transistor has to be increased but that increases the area of the chip in return. The transconductance defined above in equation 2.23 is obtained by differentiating with respect to Vos-

(2 .28)

Basic Electrical Properties of MOS, BiCMOS Devices

The transconductance in tìie linear region is independent of

V os

as long as

Vgs

a

is above

61 Vị„.

Saturation Region Parameters and their Importance in Circuit Performance The drain resistance in saturation is defined as Rds

= —^

at

is constant

(2.29)

oI d s

The transconductance in the saturation region is obtained by differentiating equation of cur­ rent in saturation region, i.e.,

w

s.

_ I d s ..V ^ n C o x W

,

(2.30)

-~ ts =KVGS-Vtr.)

o

The transconductance decides the cuưent driving capability of a MOSFET for a given input voltage swing. Higher transconductance gives the ability to charge the capacitive loads at the input of next stage in the integrated circuit. The capacitive load in the integrated cừcuits also arise from the routing capacitance of the interconnection or wire. Higher values can be achieved by reducing the channel length. Note that the benefits of increasing by increasing w are nullified by a corresponding increase in the input capacitance whereas reduction in the channel length not only increases the g but it also reduces the input capacitance. Figure of merit

Wo-’

Cg

L

Xsd

<2.31)

Inferences Switchmg speed is dependent on 1. Gate voltage above the threshold. 2. Carrier mobility. Carrier mobility is more on 100 surfaces than 111 surfaces due to the density of atoms on its plane. Hence, 100 is preíeưed. 3. Inversely as square of channel length. This supports CMOS scaling, i.e., when channel length is reduced for a process the speed of the cừcuit increases by V2 times. 2.1.6 Pass Transistor Logic MOSFETs can also be used as switches in series with lines canying logic levels as in the case of relay contacts. Such kind of logic is known as pass fransistor logic. Pass transistors pass the signal between the drain and source terminals. They require less area and wiring but cannot pass the entire voltage range. When choosing between both type of MOSFETs, nMOSFETs are

62

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VLSI Design

prefeưed for this application since the larger elecfron mobility implies faster switching than pMOSFETs. The basic nMOSFET pass transistor circuit is shown in the Fig. 2.12. The swit<^ is controlled by V g s - If V g s = 0 then the transistor is off and there is no connection betweetf the input and output. Placing a high voltage V g = V d d drives the nMOSFET active andtiHTeot flows. For a logic 1 transfer, we use an input voltage Vi„ = V d d -

''d d

D

'om D ''DD

X

y..

B ''ss X = A.B.C (BECAUSE OF VOLTAGE DROP LOGIC 1 = V dd~ K ) Fig. 2.12 Pass transistor logic.

~

Fig. 2.13 nMOS inverter.

2.1.7 nMOS Inverter The basic inverter circuit has a depletion mode MOSFET (coupled in series with the enhaacement mode MOSFET). The depletion mode MOSFET acts as a pull up transistor as it pulls the output logic from 0 to 1 and enhancement MOSFET acts like a pull down transistor as it pulls the output voltage from logic 1 to logic 0. The gate of the depletion mode MOSFET is shorted to its source, i.e., Vcs = 0 to make it a continuous ON device. The depletion mode MOSFET acts like a resistive load. The output is taken from the drain and the input applied between the gate and the ground. Figure 2.13 gives the circuit for nMOS inverter. Operation of nMOS Inverter • When Vi„ = logic 0, the pull down ừansistor (nMOSFET) is off and Vj)D appears near the Ku, • When Vj„ = logic 1 and voltage is more than the threshold voltage of the enhancement mode MOSFET current begins to flow and Vout decreases and output is logic 0.

Basic Electrical Properties of MOS, BiCMOS Devices

a

63

To obtain the fransfer characteristics of ứie mverter, Ave superimpose the Vcs = 0 deple­ tion mode characteristics curve on ứie family of curves for enhancement mode device. The points of intersection of the curves gives points on the transfer characteristics and is shown in the Fig. 2.14. The point at which Vi„ = Voul is denoted by Vinv or switching threshold. The transfer characteristics (Fig. 2.15) and Vi„y can be shifted by changing the ratio of pull up to pull dovra impedances Z p,u !Z p,d. (impedance z is denoted by ratio of length to width ratio of the fransistor). Dissipation is high since rail to rail current flows when Vi„ = Logical 1. Switching of output from 1 to 0 begins when Vi„ exceeds v,„ of pull down device. When switching the output from 1 to 0, the pull up device is non-saturated initially and pull down device moves to saturation.

Vdd

K s - 0 .6 V^o

DD

Fig. 2.14 Derivation of nMOS inverter transfer characteristics.

Vin^y) Fig. 2.15 nMOS inverter transfer characteristics.

64

D

VLSI Design

2.7.7.1 Determination of Pull up to Pull Down Ratio ữpa/Zpđ for an nMOS Inverter Driven by Another Inverter The below shown arrangement is known as cascading of inverters. In order to cascade the inverters without degradation of the voltage levels, the required condition is ^in ~ ^out ~ f^inv

Fig. 2.16 One nMOS inverter driving another nMOS inverter. For equal margins around the switching threshold Vj„y, in the fransfer characteristics, we set Vj„v = 0.5 V ũD - At this point both the transistors are in saturation. The saturation cuưent equation is given by (2.32)

ỈDS=V^nCo.ịị{Vcs-V,Ỵ For the depletion mode pull up transistor Wp.u 2

(2.33)

L

In the case of enhancement mode pull down transistor Id s

= ụ^nCox

- v,rif

Z L p .d

since V g s

= Vi„

(2.34)

Since the cuưents are same, equating the above equations M-nCo.

Wp.u 2 L'P-U

Z L p .d

(2.35)

Wp_u, Wpd, Lpu, Lpd are width and lengths of the pull down and pull up ữansistors respectively. 1

_ Wp.u

1

^Wp.d

^ p .d

L p .d

Basic Hectrical Properties of MOS, BiCMOS Devices

a

65

We have

<2-3«)

= ệ - } y u ~ - v « 'f

i,p.u

£jp.d

=

(2.37) ■^Zp.u/ Zp.d

If we substitute the typical values in the above equation, Vm = 0.2V dd\ Vfd - -0.6F dd', Vinv = O.SVdd

for equal margins

We get, Zpji/ Zpjỉ

=

4/1

• An inverter driven dữectly from the output of another should have Zp.u/Zp.d ratio of '>4/1. • Similarly an inverter driventhrough one or more pass transistors asshown in the Fig. 2.17should have Zp.u!Zp.d ratio of >8/1 (Derivationis not given here)

ir

Inverter 2

Fig. 2.17 Pull up to pull down ratios for inverting logic by pass transistors.

2.1.8 CMOS Technology Complementary metal oxide semiconductor (CMOS) is a major class of integrated cữcuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic cữcuits. CMOS technology is also used for a wide variety of analog cữcuits such as image sensors data converters, and highly integrated ứansceivers for many types of communications. In CMOS technology ckcuits, both n-type and p-type transistors are used to realize logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example, transistor-transistor logic (TTL) or nMOS logic which uses all n-channel devices without p-channel devices. These features allow inte­ grating many more CMOS gates on an IC than in nMOS or Bipolar technology resulting in much better performance. The following Fig. 2.18 shows the CMOS logic circuit.

66

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VLSI Design

PUN

Pull-up: make a connection from F ự n [ ,I n ^ ,...ỉn ) = \

to F when

-o F(/n,, Iriỵ,... Jn^) PDN

Pull-down: make a connection from

to

when

Fig. 2.18 CMOS logic circuit.

2.1.8.1 The CMOS Inverter An mverter cữcuit converts a logic high-input voltage, such as 1 V, to a low logic voltage of 0 V (or 0 V to 1 V). The Boolean statement is Vout = Vin-

DO

T <

h Fig. 2.19 CMOS inverter.

Figure 2.19 shows the cữcuit diagram of a static CMOS inverter. Its operation is readily understood with the aid of the simple switch model of the MOS transistor, i.e., the ttansistor is nothing more than a switch with an infinite off resistance (for I Fes I < 1Vt\), and a finite onresistance (for I V g s \ > I Vt\). The nMOS and pMOS transistors of the CMOS inverter act as complimentary switches. • When Vi„ is high and equal to V d d , the nMOS ừansistor is on, while tibe pMOS is off A direct path exists between Vout and the ground node, resultmg in a steady-state value of 0 V. • When Vị„ is low and equal to 0 V, the pMOS transistor is on, while the nMOS is off. A direct path exists between Vdd and Vout, resulting in a steady-state value of Vdd-

Basic Electrical Properties of MOS, BiCMOS Devices

a

67

Only transistor is ON connecting the output terminal Vout to one of the power rails, and there is no cuưent in the circuit since the other transistor is off, thus eliminating a DC path between the rails. A capacitor load C l is shown in Fig. 2.19 and it is unavoidable in any cir­ cuit. The capacitance is from transistor node and wiring capacitances.

K,„(V)

Fig. 2.20 Transfer characteristics of CMOS inverter.

The nature and the form of the voltage-fransfer characteristic (VTC) can be graphically deduced by superimposing the cuưent characteristics of the nMOS and the pMOS devices. Such a graph is shown in the Fig. 2.20. Figure 2.21 shows current versus Vi„ in the CMOS inverter.

Fig. 2.21 CMOS inverter— current versus

Vjn.

68

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VLSI Design

Regarding to the Figs. 2.20 and 2.21, we can conclude that CMOS inverter has five distinct regions of operation. Region 1. We have stable logic 1 for Vị„ = logic 0. pMOS transistor is completely ON whfle nMOS transistor is completely OFF. A good logic 1 is observed near the output. Region 2: The input voltage has increased beyond the threshold voltage of the nMOSFET. The fransistor conducts and has a large voltage between source and drain. Hence, it is in satu­ ration. The pMOSFET is also conducting with small voltage across it, hence it is in unsatu­ rated ohmic or resistive region. Region 3: In this region the inverter exhibits gain and both transistors are in saturation. Region 4: nMOSFET is in linear or resistive region and pMOSFET is in saturation. Region 5: We have stable logic 0 for Vi„ = logic 1 nMOS transistor is completely ON while pMOS transistor is completely OFF. A good logic 0 is observed near the output. When analyzing region 3, both transistors are in satiưation and cuưent in each device must be same since both the transistors are in series, i.e., Current through n-channel pull-down transistor (2.38) Cuưent through p-channel pull-up transistor (2.39) At logic threshold, Idsn

= Idsp

2

(Vi. -V m f=

(2.40)

We can express Vị„ in terms of p ratio and other circuit voltages and currents as

Vdd + V ^ + K K„=-—— r ' in

(2.41)

1+ Vi„ is

also known as switching threshold.

Since both transistors are in saturation they act as current sources so that the equivalent circuit in this region is two cuưent sources in series between Vdd and Vss with output voltage coming from the common point.

Basic Electrical Properties of MOS, BiCMOS Devices

Vdd

a

69

(2.42)

Conclusion: Change over is symmetrically disposed about ứie point at which Vi„ — Voul — ữ.5VDD. When|5„-|ip,

(2.43)

=

\^n For a particular process, length of pMOS and nMOS are equal. Hence, w ~ "n M-p But we know \1 „ = 2.5ịtp, hence, pMOS teansistors are made 2.5 times wider than nMOS ừansistors. 2.1.9 BiCMOS Inverters As iii nMOS and CMOS logic, the basic logic element is the inverter circuit in BiCMOS logic family. The MOS transistors are used to implement the logic, while bipolar transistors drive the output loads. The following Fig. 2.22 shows the simple BiCMOS inverter.

Fig. 2.22 A simple BiCMOS inverter.

The inverter consists of two bipolar transistors Ĩ 3 and Ĩ 4 and one nMOS transistor Ti and one pMOS transisstor Ĩ 2 . Both MOSFET transistors are enhancement mode transistors. • When Vi„ = 0 volts Tị is turned OFF, hence Ĩ 3 is also OFF. Ĩ 2 is ON and supplies cur­ rent to the base of T4. T 4 conducts and acts as cuưent source to charge load Q towards Vdd- Kut rises to Vdd - Vbe (of 74). Pull up bipolar transistor turns off as the output approaches 5 V - Vbe (of 7 4 )-

70

a

VLSI Design

Note: Vb e (of 24 ) is base emitter voltage of 7 4 . • When Vj„ = Vdd, Ti is OFF. Therefore, T4 is non-conducting. T\ is on and supplies cw rent to the base of Ti. T3 conducts and acts as a current sink to discharge load Cl towaidi Vou, falls to 0 V + VcE^at (of h ). Note: VcEsat (of Ti) is saturation voltage from 7 3 collector to emitter. The steengths of BiCMOS inverter are • • • • •

7 3 and T4 present low impedances when turned on into saturation and load Cl will bi charged or discharged rapidly. Output logic levels will be good and will be close to rail voltages since VcEsat is quite small and Vbe ~ 0.7 V. Therefore, inverter has high noise margins. Inverter has high input impedance, i.e., MOS gate input. Inverter haslow output impedance. Inverter has high drive capability but occupies a relatively small area.

Drawbacks of tíie above design are • When Vin = V d d , T2 is OFF and no conducting path to the base of T4exists and whenVj„ = 0, T\ is OFF and no conducting path to the base of T-Ì exists. This willslow down the action of the circuit. • There is DC path between Vdd and GND through and T\. Due to this there will be significant static current flow when Vi„ = logic 1. Improved Version

’ DD

Fig. 2.23(a) An alternative BiCMOS inverter with no static current flow.

Basic Electrical Properties of MOS, BiCMOS Devices

a

71

In this version, the DC path between T\ and Ts is eUminated (Fig. 2.23a) but Ae output volt­ age swmg is now reduced since output cannot fall below the base to emitter Vbe of 7 3 . The dischaige paths for 74 and T i are net still there in this design. The conventional BiCMOS Inverter Two additional enhancement-type nMOS devices have been added (7s and Jg) to ứie existing design (Fig. 2.23b). These ứansistors provide discharge patiis for ứansistor base currents during tum-ofif. V^tfaout Ts, the ou^ut low voltage cannot fell below die base to emitter voltage Vbe of Ts. DD

h :

Fig. 2.23(b) An improved version of BiCMOS inverter using MOS transistors for base current discharge.

1. When Vi„ = 0 Ti is off, therefore Ti is nonconducting. Ĩ 2 is ON and supplies ciurent to base of T4 . 74 base voltage is set to Vdd- Ts is turned ON and clamps base of Tỉ to GND. Tị is turned OFF. T4 conducts and acts as current source to charge load Q towards VpD- Kuf rises to Kod - Vbe (of TÀ). 2. Vi„ = Vdd T2 is OFF. T\ is ON and supplies current to the base of Ty Tf, is turned ON and clamps the base of T4 to GND. T4 is turned off. 7 3 conducts acts as a current sink to discharge load Cl towards 0 V. Vout falls to 0 V + VcEsat (of 7 3 ). Properties of BiCMOS inverter • Large drivmg capability of BiCMOS inverter is one of the most significant advantages over convenrional CMOS buffer circuits. • BiCMOS logic gate doesn’t dissipate any significant amount of static power during steady state operation. • BiCMOS logic family has about same power delay product as conventional CMOS but the gate delay is smaller.

2

a

VLSI Design

1.1.10 Latchup in CMOS ■t Vby-product of the Bulk CMOS structure is a paữ of parasitic bipolar transistors. The coUecor of each BJT is connected to the base of the other ứansistor in a positive feedback structuie Fig. 2.24). A phenomenon called latchup can occur when (a) both BJT’s conduct, creating 9 ow resistance path between Vdd and GND and (b) the product of the gains of the tw o traiH istors in the feedback loop, Pi X P2, is >1. The result of latchup is at the minimum a circBit

GND

' DD

Vertical PNP

Lateral NPN

Fig. 2.24 Cross-section of parasitic transistors in Bulk CMOS,

/ Qi

GND Fig. 2.25 Equivalent circuit of latchup.

Basic Electrical Properties of MOS, BiCMOS Devices

a

73

malfunction, and in the worst case, the destruction of the device. The equivalent circuit is given in Fig. 2.25. Latchup may begin when Vout drops below GNĐ due to a noise spike or an improper circuit hookup (Ị^„, is the base of the lateral NPN Q2 ). If sufficient current flows through R-sub to turn on 0 2 (I R-sub > 0.7 V), this will draw cuưent through R-well. If tìie voltage drop across R-well is high enough, Qi will also turn on, and a self-sustainmg low resistance path between the power rails is formed. If the gams are such that Pi X P2 > 1, latchup may occur. Once latchup has begun, the only way to stop it is to reduce the current below a critical level, usu­ ally by removing power from the cừcuit. Preventing latchup 1. Fab/Design Approaches ■ Reduce the gain product Pi X p2. ■oMoving n-well and n+ source/drain farther apart increases width of the base of Q2 and reduces gain p2 > also reduces circuit density. ■ Buried n+ layer in well reduces gain of Q ị . 2. Reduce the well and subsừate resistances, producing lower voltage drops ■ Higher substrate doping level reduces R-sub. ■ Reduce R-well by makmg low resistance contact to GND. ■ Guard rings around p- and/or n-well, with frequent contacts to tíìe rings, reduces the parasitic resistances (Fig. 2.26). n+guarding i-well

GND

DD

nMOS Transistor

pMOS Transistor

Fig. 2.26 Guard rings for eliminating latchup.

1.

Metal Oxide Field Effect Transistor (MOSFET) cữcuits occupy less silicon area and consume less power than thek bipolar counterparts (BJT) making them ideal choice for VLSI cữcuits.

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2. Threshold voltage is the voltage at which the concentration of surface becomes equal to concentration of the bulk but of opposite polarity. 3. In a cut-off region iV.Gs< there is no chaimel aad almost zero cunatf flows from drain to soxirce. 4. In linear region channel is formed and drain current increases Unearly when potential is mcreased between source Mid drain. 5. At saturation voltage the MOSFET acts like a constant cuưent source and channel gets pinched off. The pinch off point moves closer to source when drain to source voltage is increased. 6 . Depletion mode MOSFET is an always ON device and can be used as a load resistor. 7. As the device dimensions shrink leakage current problems needs to be coỉìcen-trated more. Cữcuit level as well as process level techniques are requừẹd for leakage power reduction. 8 . Complementary Metal Oxide Semiconductor (CMOS) is a major class of inte­ grated cừcuits. Two important characteristics of CMOS devices are higb noise immunity and low static power consumption. 9. The MOS transistors are used to implement the logic, while bipolar ttansistors drive the output loads in BiCMOS inverters.

^

Fill in the Blanks

1. A MOS transistor which has no conducting channel region at zero gate bias is called •. 2. ______ ^ load in the nMOS invertor makes HIGH OUTPUT logic less by IF,. 3. The soxirce of nMOS and pMOS Ũ1 CMOS inverter always connected to . 4. _______ is the input voltage of a CMOS invertor in which both pMOS and nMOS in saturated region. 5. The speed of CMOS logic is less, when compared to other technologies due to ________, 6 . If packaging density area and performance are the constraints, power dissipa­ tion is not a constraint, the technology prefeưed is . . : 7. The state of pMOS and nMOS transistor in region 4 of V4„ ys ch^cteristics i s _______ . 8 . The parameter which affect the propagation delay is 9. Advantages on silicon on insulator CMOS process is 10. Working of MOSFET depends o n ________ .

Basic Electrical Properties of MOS, BiCMOS Devices

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11. The width of the channel is dependent o n _______ . 12. The ratio of g jc g gives_______ . 13. An inverter driven dữectly from the output of another should have a ZpJZpd = ______

14. The product of electron mobility witíi elecfric field gives_______ . 15. In BiCMOS logic BJTs are used near output to drive high_______ . Answers

^

1. 2. 3. 4. 5. 6. 7. 8. 9.

Enhancement mode Satoated GND,K/,o V d d !2

High input capacitance nMOS Saturation, linear Load capacitance, doping densities, channel length Absence of latchup problem

10. Vd s

11. 12. 13. 14. 15.

V gs

Figure of merit >4:1 Velocity Cuưents.

1. Determine the bias state for the three conditions in figure below if Fft, = 0.4 V. ẹ 2.5 V

0.5 V V ẹẹ 0.5

ẹ# 0.5 V

1.9 V

I (a)

-2.3 V (b)

i

-2.5 V

(c)

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Solution: • The nMOS saturated bias condition: Vos > Fas - K or V g s < • The nMOS ohmic condition: Fũs < - K or Fgs > Kds +

+ K

(a) Fgs = 1.9 V, Vds = 2.5 V, and = 0.4 V, therefore Vos = 1.9 v < 2.5 V + 0.4 V = 2.9 V. Fgs< ^ ds + Vt„ is satisfied, and the transistor is m the satu­ rated state. (b) Vgs =F g - V s = 2 . 2 V - (-2.3 V) = 4.6 V. ^DS = F ^ - V s = 0 .5 V - (-2.3) = 2.8 V. Therefore, Fes = 4.6 V > 2.2 V + 0.4 V = 2.6 V. Fes > + F/ is satisfied, and the transistor is in the nonsaturated state. (c) Fgs =F g - V s = 0.9 V ~ (-2.5 V) = 3.4 V. Fos = V o -V s = 0 . 5 V - (-2.5 V) = 3 V. Therefore, Fas = 3 . 4 V = Fds + Vt = 3 V + 0.4 V = 3.4 V, and the transistor is at the boundary of the saturated and ohmic regions. 2. Calculate Ip and V/)S if = 100 ụ.AN'^, v,„ = 0.6 V, and WIL = 3 for transis­ tor Ml in the circuit in figure. 5V

I 15ki2

1.5 V

M, 1

The bias state of M l is not known, so we must initially assume one of the two states, solve for bias voltages, and then check for consistency against that transistor’s bias condition. Initially, assume that the transistor is in the satu­ rated state so that Id = K„{W!L){Vgs - v,hf where K„ = ịi„Co, = (100 nA) (3) (1.5-0.6)2 = 243 ịiA Using KirchhofF’s voltage law (KVL): V- I dR = 5 -(2 4 3 ^A)(15kfí) = 1.355 V

Vd s =

Basic Electrical Properties of MOS, BiCMOS Devices

a

We assumed that the transistor was in saturation, so we must check the result to see if that is true. For saturation, VGS
1.5 v < 1.355 v +0.6 V So the fransistor is m saturation, and our assumption and answers are coưect. 3. Repeat the above example, finding I d and Assume a transistor saturated state and

Vd s

if Vg=

1. 8

V.

Id = (100 mA)(3)(1.8 - 0.6)2 = 432 ịiA ^/>5=5-(432 ^A)(15kD) = -1.48 V This value for Vos is clearly not reasonable since there are no negative poten­ tials in the cữcuit. Also, the bias check gives Vgs > Vds + Vt„

1.8 F > -1.48 v + 0.6 V

The initial saturated state assumption was wrong, so we repeat the analysis Iismg the ohmic state assiunption; Id = K„ iWIL) [2(Vgs - V,h) Vds - Vd ỉ ] = ( 1 0 0 nA) (3) [2 ( 1.8 - 0 .6 ) Vos- Voi] = 300

[2.4 V d s - V

d ỉ -]

This equation has two unknowns, so another equation must be found. We will use the KVL statement, V dd - ỉd R + V ds

I d = {V d d - V d s )IR

= (5 - Vd s ) ! \ 5 k£i

The two equations can be equated to theữ Id solution, giving (5 - V d s ) ! \ S k n = 300 ị i A (2.4 V o s - V d s ^)

After some algebra, this reduces to Vos^-2.622F d s + 1.11 = 0

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The two quadratic solutions are Vũs = 0.531 V, 2.09 V The valid solution is Vps = 0.S3Ỉ V, smce this satisfies the nonsaturation condi­ tion that was used in its solution:

1.8 v > 0.531 v +0.6 V I d = {V dd - Vds ) ! \5 k í2

= (5 V - 0.531 V)/15kQ

= 298 ^A

CHAPTER

VLSI Design Flow

CHAPTER OBJECTIVES In this chapter, you will be introduced to • • • • • • • • • • •

VLSI design process Architecture specifications and design constraints HDL capture and RTL coding Logic simulation Logic synthesis Logic optimization Formal verification Static timing analysis (STA) Floor planning Placement Routing

3.1 INTRODUCTION The process of developing a chip from concept to silicon is divided into the following four tasks: design, verification, implementation and software development. (a)

Design often starts with marketing research and product definition and is followed by system design. It ends with RTL coding (a detailed discussion about RTL is discussed later in the chapter).

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(b) Verification is a means of ensuring that the chip can perform faith&lly in functioiialfl according to its design specifications. It mcludes verification at the system, RTL, gm gate levels, and sometimes even at the ữansistor level. This bug-finding sttiỉggỉe co^Bi ues until the chip is ready for production. (c) Implementation is the process of actually creating the hardware, which results in an that one can see and feel. It includes both the logical and physical implementatioiis. (d) Software development is the process of programmmg the brain of the chip (die am chip processors), or arming the chip with mtelligence. To discuss in detail about the design flow and various phases in it, we need to considCT die design flow diagram. Before discussing about the design flow, let us know about the engmeen needed for the chip design project. 1. System or architect engineers who define the chip at the system level. 2. IC design engineers who compose the RTL codes for the digital blocks and design tiie circuits for analog components. 3. Verification engineers who verify the functionality at both the block and chip level. 4. Design-for-testability engineers who ensure that the chip is testable for volume production. 5. IC implementation engineers to turn the design from a paper plan into real hardware. 6 . Software engineers to make the bare silicon chip into a useful electronic device. 7. Application engineers to build the reference design for customers. 8 . Test engineers to write testing programs for production tests. 9. Product engineers are needed during the chip’s volume production tocoordinate the operations between the design and manufacturing facilities and, generally, to ensure the smooth flow of chip production. In most cases, a project manager is also assigned to a chip project to coordinate the design, test, production, and marketing activities of the entire project, s/he creates and tracks project milestones to keep the project on schedule and witilin budget. If necessary, s/he also consults with business managers to adjust the milestones based on market conditions and design status and sometimes to acquire additional resources. One of the key figures in a chip project is the design leader. The role of the design leader is to lead the design team from a technical, not a business or administrative, perspective. The design leader is not obligated to know, or be expert at, every detail of the technical aspects of building the chip. However, s/he must have a solid understanding of the major aspects of IC design. 3.2VLSI CIRCUIT DESIGN PROCESS Design process An iterative process that refines an IDEA to a manufacturable device (chip) through at least five levels of design abstraction.

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Abrtraction A very effective means of dealing with design complexity creating a model at a higher level of abstraction involves replacing details at low level with sunplifications. A system behaviour should be understood from its top level (chip as a whole) to ứie 'sừnple transistor level in the IC design process. System’s behaviour is the high-level abstraction, while transistor’s functionality is the lowest level of absừaction. Basically, there are five levels of absừaction: 1. 2. 3. 4. 5.

Functional or architectural Register transfer level (module or fimctional block) Logical design Cữcuit design Physical design.

In VLSI design process, there are three distinct design domains, namely: • Behavioural domain which specifies the software implementation of the system’s functionality. • Structural domain which specifies how modules are connected together to affect the prescribed behaviour. • Physical domain which specifies the layout used to build the system according to the architect’s idea from transistor level. All three domains aun in common to achieve tìie specified behaviour of die system meeting the customer requkement. Engineers work in all domains at various abstraction levels in the project. Let us understand the design process using Y-chart and the tabular form shown below in Fig. 3.1 Behavioural domain

Structural domain

Application O.SN

SC processor Addeis, gates^ịegisters

/ _PhysicalYTi^vSÌstors / \ abstract \ CircuK, level \absttacrx^ Transistors Logic 'slevel abstraction \ level Modules

Architectural abstraction level

Chips Boards Boxes Physical domain

Fig. 3.1 Y-chart.

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Architectural abstraction

Logical abstraction

Circuit abstraction Physical abstraction

3.3

Physical Domain

Structural Domain

Behavionnd

Architecture of ICs, PCBs used, packages used to build tíie system (hardware) Various units in the architecture (memory imits, conứoller units, etc.) Cells used (standard cells or semi-custom) Transistors in the cells

PC (total system)

Software code of entữe system

Types of processors (RISC or CISC) used to build the system

Operating systems, pro­ grams written to mala tìie system run

Adders, registers, multi­ plexers, etc. Transistor layouts

Subroutines or fimcdoo! in the programs Instructions (basic level in the program)

DESIGN FLOW

A design flow is a sequence of operations that transform the IC designers’ intention (usually represented in RTL format) into layout GDSII data. A well-tuned design flow can help designers go through the chip-creation process relatively smoothly and with a decent chance of error-free implementation. And, a skilful IC implemen­ tation engineer can use the design flow creatively to shorten the design cycle, resulting in a higher likelihood that the product will catch the market window. The design flow for a typical IC project is shown in Fig. 3.2. 3.3.1 Concept and Market Research A detailed research about the tools available for designing the IC according to the specifica­ tions given in the requirements documents is done thoroughly. 3.3.2 Architecture Specifications and Design Constraints The design idea refined into a set of requirements is known as specification. The general spec­ ifications are 1. 2. 3. 4.

What does the chip do? How fast it need to operate in order to be competitive in market? How much power will it consume? How big will it be?

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5. How much time it takes to design the chip? 6 . How effectively it can be tested? The parameters that impose the design constraints are speed, power and area. Design is a continuous trade off to achieve the adequate results for all specifications. 3.3.3 HDL Capture and RTL Coding The design of integrated circuits (ICs) is an art. During a half century of IC development it has gradually become clear that there is a need for a computer language to describe the

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structure and function of integrated circuits, or for describing an entire electronic the 1980s, ứie need for such a hardware description language (HDL) finally drew the of the government, the electronics industry, and universities. As a result, two HDL Verilog and VHDL, have been standardized and have emerged as the tools for IC desiga An HDL is created to meet a number of needs in the IC design process. 1. HDL allows the description of the structure of a hardware system. 2. HDL can be used to describe how the system is decomposed into building blocks aiỉ how those building blocks are mterconnected. 3. It allows the specification of the system functionality by using tíie form of familiar pntgranuning language. 4. The design of a system can be simulated before being manufactured so that designcli can quickly compare alternatives and test for coưectness widiout the delay and expow of hardware prototyping. 5. It allows the detailed structure of the design to be synthesized from a more abstraet specification, allowing the designers to concentrate more on strategic design decisions. This automatic synứiesis process also helps reduce design implementation time. Overall, the use of HDL can benefit tíie IC design process in following aspects: documentmg the design, simulating tìie behaviour of the design, and directly synthesizing the design into real hardware. In integrated circuit design. Register IVansfer Level (RTL) description is a way of describing the operation of a synchronous digital circuit. In RTL design, a circuit’s behaviour is defined in terms of the flow of signals (or fransfer of data) between hardware registers, and the logical operations performed on those signals. Register transfer level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations o f a circuit, from which lower4evd representations and ultimately actual wiring can be derived. The following example of a simple circuit in Fig. 3.3 with a toggling output gives an idea about RTL coding or description. A synchronous circuit consists of two kinds of elements: registers and combinational logic. Registers (usually implemented as D flip-flops) synchronize the circuit’s operation to the edges of the clock signal, and are the only elements in the circuit that have memory properties. Combinational logic performs all the logical fiinctions in the circuit and it typically consists of logic gates. For example, a very simple synchronous circuit is shown in the Fig. 3.3. The inverter is connected from the output of a register to the register’s input, to create a circuit that changes its state on each clock edge. In this circuit, the combinational logic consists of the inverter. When designing digital integrated circuits with a hardware description language, tbe designs are usually engineered at a higher level of abstraction than transistor or gate level. In HDLs the designer declares the registers (which roughly coưesponds to variables in com­ puter programming languages), and describes the combination logic by using constructs diat

VLSI Design Flow

Combination logic

a

»5

Register

Fig. 3.3 The inverter forms the combinational logic in this circuit, and the register holds the state.

are familiar from programming languages such as if-then-else and arithmetic operations. This level is called register transfer level. The term refers to the fact that RTL focuses on describ­ ing tìie flow of signals between registers. As an example, the cừcuit mentioned above can be described in VHDL as follows: o process(clk) begin if rising_edge(clk) then Q < not Q; end if; end process: Using an EDA tool for synthesis, this description can usually be dừectly translated to an equiv­ alent hardware unplementation file for an ASIC or an FPGA. The synthesis tool also performs logic optimization (synthesis and logic optimization are discussed later in this topic in detail).

>• A digital circuit can be described at gate level, behaviour level and register transfer level. But RTL is the preferred why so? Using an HDL to describe a hardware system is carried out on three levels: the gate level, the register-transfer level (RTL), and the behavioural level. The behavioural-level description does not pay any attention to the implementation aspects of the design. It simply describes the behaviour, or functionality, of the design by using a higher level of abstraction (system level), with no information or direction on how the design will be implemented. While the gate level describes a system in a purely structural fashion, by decomposing the system into basic building blocks (logic gates) whose functionalities are well defined and whose structures are fixed. It is not easy to exừact the functional sense by just reading gate-level HDL since it only con­ tains components and tíieữ interconnections. Gate-level description is primarily used

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in the last stage of IC implementation to precisely describe tihe physical sttucture of the design, with little or no attention paid to its functionality. The RTL level of description is somewhere in between. It defines the system behaviour by describing how the data, or information, is transfeưed and manipu­ lated inside the system. It implies the system sttncture by refemng dừectly to die data storage elements and describing how the data should be manipulated between those storage elements. Compared to gate-level description, RTL-level descnptíoo describes a design at a higher level of abstraction. It encourages the designer to focus on the functionality of the design rather than on its implementation, while leaving the automatic synthesis tool to realize and optimize the fimctionality specừìed. In other words, RTL allows the designer to describe “what” the design does, and lets the synthesis tool decide “how” the design should be implemented in order to create the optimal implementation. As a matter of fact, the specific HDL coding style reqwred by Synopsys’ synthesis tool (e.g., Design Compiler) is refeưed to as RTL coding.

3.3.4 Logic Simulation Simulation is the use of a computer program to simulate the operation of a digital cừcuit. Logic simulation is the primary tool used for verifying the logical correctness of a hardware design. In many cases logic simulation is the first activity performed in the process of taking a hardware design from concept to realization. Modem hardware description languages are both simulatable and synthesizable. Designing hardware today is really writing a program in a hardware description language. Performing a simulation is just running that program. When the program (or model) runs coưectly, then one can be reasonably assured that the logic of the design is coưect, for the cases that have been tested in the simulation. • Simulation is completely general. Any hardware design can be simulated. The only limits are time and computer resources. • Prospective way to accelerate logic simulation is using distributed and parallel computations.

*

w m iai ► Why should be the design simulated in the early stage of the design process? The level of effort required to debug and then verify the design is proportional to the maturity of the design. That is, early in the design’s life, bugs and incoưect behav­ iour are usually found quickly. As the design matures, it takes longer to find the errors. This is beneficial early in the design process. It becomes more problematic later.

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Some well-known applications used to simulate digital logic are Verilog (Technically VerĨ is an HDL or Hardware Description Language), Model Sim, Logic Sim and Logisim. The St famous of which is Verilog, some variations of Verilog are Veriwell, and Icarus Verilog.

.4.1 RTL Simulation s logic coưectness of the RTL description is checked by simulation by applying test vectors or by running test bench program. Parallel to this stimulus is applied to the function specifica­ tions (manually). If the results match, the RTL simulation is successful tíie design flow pro­ ceeds to the next level.

*

► What is a test bench program? A test bench is an entity constructed in HDL, such as VHDL and Verilog, or in some other higher-level languages. It stimulates the module (device) under test and observes its behaviour.

Device under test w > c Q Results

Stimulus

Test bench Fig. 3.4 Test bench.

The test bench is the driver that provides the stimulus to activate the device. It also captures the behaviour of this device under this set of stimuli to evaluate its performance. If the test result does not agree with what is expected, then there are potential functional errors, or bugs. The test bench has become an integral part of the IC design process. Its aim is to ensure that the HDL module is sufficiently tested or no known bug exists, before it can be implemented in hardware.

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3.3.5 Logic Synthesis L o g ic s y n th e s is is t h e p r o c e s s o f tr a n s la t in g a n a b s tr a c t f o r m o f d e s ir e d c ir c u U b e h a m r n ( ty p ic a lly in R T L ) in to a d e s ig n im p le m e n ta tio n in te r m s o f lo g ic g a te s . This process is Ciu^ ried out by automatic synthesis tools with sophisticated algorithms. The oiUcome of ứiis logic synthesis is the netlist or schematic. The quality of a logic synứiesis task is highly depended upon the ASIC libraiy used, the algorithms embedded m synthesis tools and the CPU, and the memory configuration of die computer that carries out the synthesis task. Synopsys’s Design Compiler (from now on termed as, DC) is the standard and by ứie most popular synthesis tool in ứie ASIC industty today. DC reads the RTL code of die design and using the timing constraints, synthesizes the code to structural level, thereby pro­ ducing a mapped gatelevel netlist. A schematic, or netlist, is the real circuit representation of

► What is an ASIC Ubrary? An ASIC library is a group of standard cells glued togeứier as a package. Typi­ cally, an ASIC library contains a sufficient number of combinational cells to perfoim any logic operation requữed by commonly used design styles with decent efficiency. It should also have many types of sequential cells to meet any storage requữements. A typical modem ASIC library could have more than several hundred different stan­ dard cells. Those cells are categorized into groups by theữ functionality, such as INV, BUF, NAND, NOR, AND, OR, XOR, Boolean functions, flip-flop, and scan flip-flop. Withm each functional group, there are a certain number of cells with different drivability. For example, in the inverter group of INV, there are usually a Ix drive cell INVl; a 3x drive cell INV3; and INV5, INV7, and INV9 cells. Diflferent drivability cells within one group provide flexibility to the synthesis tool so that tìie optimal result can be achieved. ► What are the optimization targets for Logic synthesis? The optimization targets of a logic synthesis task are speed, area, and power. For successful implementation into real circuits or logic gates, a circuit produced by HDL synthesis must meet certain speed requirements defined by clock frequency. Otherwise, it is less effective, if not totally useless. Another obvious goal of logic synthesis is that the resultant circuit should occupy as little silicon area as possible to maximize profit margins. The third concern in logic sjmthesis is power consume tion. Nowadays, as more and more IC designs are targeted for mobile applications, a chip’s power usage has become a very sensitive issue. However, as process geơnh efries keep getting smaller, the leakage cuưent problem becomes more severe and starts to gradually move from backstage to cenừe stage. In other words, lower and

VLSI Design Flow

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lower power consumption is desữed on one hand, yet power management becomes tougher and tougher on the other hand. As a result, optimizing for power is a more serious and challenging logic synthesis issue than ever before. These three optimi­ zation targets are not isolated, but related to each other. During the optimization process, trade-offs are often made among these targets. For example, to achieve higher circuit speed, more silicon area might be requữed and more power needed. To achieve better power control, more gating cữcuitry might be requữed, which, in turn, requừes more area.

an electronic design. It consists of the basic cữcuit elements {instances), their interconnections (wires), between them. The functionality of this netlist should agree with what is described in the ongmal RTL code. Logic synthesis is one major aspect of electronic design automation. Soiâe of tíie synthesis tools available in the market are • • • • •

Design Compiler by Synopsys Blast Create hy Magma Design Automation LeonardoSpectrum and Precision (RTL/Physical) by Mentor Graphics SynpUfy (PRO/Premier) by Synplicity BlastFPGA by Magma Design Automation, etc.

3.3.6 Logic Optimization Logic optimization a part of logic synthesis, is the process of finding an equivalent repre­ sentation of the specified logic circuit under one or more specified consừaints. Generally, the cừcuit is constrained to minimum chip area meeting a prespecified delay. With the advent of logic synthesis, one of the biggest challenges faced by the EDA industry was to find the best netlist representation of the given design description. Today, logic optimization is divided into Vfflious categories based on two criteria: Based on circuit representation 1. Two-level logic optimization 2. Multi-level logic optunization ' Based on circuit characteristics 1. Sequential logic optimừation 2. Combinational logic optimization While two-level circuit representation of circuits strictly refers to the flattened view of the circuit in terms of sum-of-products (SOPs>—more applicable to PLA implementation of design—multi-level representation is a more generic view of the cữcuit in terms of arbiừarily

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connected SOPs, POSs (product-of-sum), factored form, etc. Logic optimization a lg o rit^ generally work either on the structural (SOPs, factored form) or functional (BDDs, ADDi| representation of the circuit. Two-level versus multi-level representations If we have two functions F\ and FiF ị = A B + A C + AD

F2 = ÃB +ẨC +ẨE The above two-level representation takes six product terms and 24 ttansistors in CMOS Rep. A functionally equivalent representation in multi level can be: P =B + C Fx=AP + AD F2 = ÃP + Ẵ E

While the number of levels here is 3, the total number of product terms and literals reduce because of the sharing of the term B + c. Similarly, we distinguish between sequential and combinational circuits, whose behaviour can be described in terms of finite-state machine (FSM) state tables/diagrams or by Boolean functions and relations respectively. In short, optimization aims and minimizing o f number o f transistors thereby saving the area and later power consumption o f the chip. 3.3.7 Formal Verification Verification is the process of checking the design’s functional correctness. This process can consume over 60% of the total design resource in today’s ' arge, complicated chip designs. Formal verification techniques perform validation of a design using mathematical methods without the need for technological considerations, such ail timing and physical effects. They check for logical functions of a design by comparing it against the reference design. A number of EDA tool vendors have developed the formal verifica ion tools. However, only recently, synopsys also introduced to the market its own formal verification tool called Formality. The main difference between formal methods and dynamic simulation is that former tech­ nique verifies the design by proving that the structure ard functionality of two designs are logically equivalent. Dynamic simulation methods can only probe certain paths of the design that are sensitized, thus may not catch a problem present eisewhere. In addition, formal melhods consume negligible amount of time as compared to dy lamic simulation. The purpose of the formal verification in the design f ow is to validate the RTL against RTL, gate-level netlist against the RTL code, or the com])arison between gate-level to gatelevel netlists. The RTL to RTL verification is used to validate the new RTL against the old

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functionally correct RTL. This is usually performed for designs that are subject to frequent changes in order to accommodate additional features. When these features are added to the source RTL, there is always a risk of breaking the old functionally correct feature. To prevent this, formal verification may be performed between the old RTL and the new RTL to check tíie validity of the old functionality. The RTL to gate-level verification is used to ascertain that the logic has been synthesized accurately by DC. Since the RTL is dynamically simulated to be functionally coưect, the for­ mal verification of the design between the RTL and gate-level netlist assures us that the gatelevel also has the same functionality. In this instance, if we were to use the dynamic simulation method to verify the gate-level, it would have taken a long time (days and weeks, depending on the size of the design) to verify the design. In comparison, the formal method would take a few hours to perform a similar verification. The last part involves verifying the gate-level netlist against the gate-level netlist. This too is a significant step for the verification process, since it is mainly used to verify—^what has gone into the layout versus what has come out of the layout. What comes out of the layout is obviouSly the clock free inserted netlist. This means that the original netlist that goes into the layout tool is modified. The formal technique is used to verify the logic equivalency of the modified netlist against the original netlist.

3.3.8 Static Timing Analysis (STA) Static timing analysis (STA) is a method of computing the expected timing of signals inside a digital cừcuit without using simulation. In a synchronous digital circuits, data is supposed to move in lockstep, advancing one stage on each tick of the clock signal. This is enforced by synchronizmg elements such as flip flops or latches, which copy their input to theữ out­ put when instructed to do so by the clock. Two kinds of timing eưors are possible in such a system: • A hold time violation, when a signal arrives too early, and advances one clock cycle before it should. • A setup time violation, when a signal anives too late, and misses the time when it should advance. The time when a signal aưives can vary due to many reasons—the input data may vary, the circuit may perform different operations, the temperature and voltage may change, and there are manufacturing differences in the exact construction of each part. The main goal of static timing analysis is to verify that despite these possible variations, all signals will aưive neither too early nor too late and hence proper circuit operation can be assured. Hence, the static timing analysis, to some extent, is the most important step in the whole ASIC design process. STA is capable of verifying every path, apart from helping locate setup and hold time violations; it can detect other serious problems like glitches, slow paths and clock skew.

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Static timing analysis plays a vital role m facilitating tìie quick and reasonably measurement of circuit timing. It is not designed fo r verifying the design*s functionai { redness, but to check its timing validity. It locates the worst-case delay of the cưcuit 0 V«J possible input combinations. There are huge numbers of logic patiis mside a chip of < design. The advantage of STA is that it performs timing analysis on all possible paths. In cHỉiệ words, unlike simulation, which only checks timing on given paths, STA is a complete timw^ check that covers all of the paths, whether they are real or potential false paứỉS. However, it is worth noting that STA is not suitable for all design styles. It has provea efficient only for fully synchronous designs. Since the majority of chip design is synchronoBS^ it has become a main stay of chip design over the last few decades. Fiuthermore, the Fqxnt can also contain other debugging mformation like the fanout or capacitive loading of eaeft net. PrimeTime is the Synopsys’s static timing analysis tool that is capable of perfonnii^ extremely fast static timing analysis on full chip-level designs. The static timing is performed both for the pre and post-layout gate-level netlist. Pre-Layout Static Timing Analysis In the pre-layout mode, PrimeTime uses the wire load models specified in the library to estit mate the net delays. During this, the same timing consữaints that were fed to design compile (DC) previously are also fed to PrimeTime, specifying the relationship between the primaiy I/O signals and the clock. If the timing for all critical paths is acceptable, then a constraints file may be written out from PrimeTime or DC for the piưpose of forward annotation to the layout tool. This constraint file in SDF format specifies the timing between each group of logic that the layout tool uses, in order to perform the timing driven placement of cells. Post-Layout Static Timing Analysis In the post-layout mode, the actual extracted delays are back annotated to PrimeTime to pro­ vide realistic delay calculation. These delays consist of the net capacitances and interconnect RC delays. Similar to synthesis, static timing analysis is also an iterative process. It is closely linked with the placement and routing of the chip. This operation is usually performed a num­ ber of times until the timing requirements are satisfied.

3.3.9 Floor Planning As the name suggests, the layout tool generates the layout and performs the placement and rout­ ing. Floor planning is the first major step in physical design. The key tasks in this step include analyzing the die size, selecting the package, placing the I/Os, placing the macro cells (e.g., memory cells, analog cells, and special function cells), planning the distribution of power and the clocks, and partitioning the hierarchy. Die size estimation often starts from the gate count of the netlist (available from the logic synthesis process) plus the physical size of the I/O’s. A design can be characterized as I/O limited, core limited, block limited, or package lim­ ited. The die size of an I/O-limited design is determined by its number of I/O’s. The foil placement of the prime input and output cells will dominate the physical size of this chip, to

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a core-limited design, the size of the chip is governed by the core area or the number of stan­ dard m d macro cells used. In tìứs case, there is probably room to compensate for a few more I/O signals without increasing the chip size. In a block-limited design, there usually are a significant number of large blocks, or subchips, and the chip size is dominated by the sizes of those blocks. For a package-limited design, the chip size is driven by the available package. Package selection is another major issue that affects the physical design. The selection is based on a number of factors, such as the number of I/O’s, the die size, the chip power con­ sumption, and the price. After the package has been fixed, the next crucial stq) is to aưange the prime input and output cells. I/O configuration has a dừect impact on the quality of physi­ cal layout since the placement of the rest of the standard cells and macros depend on the I/O locations. The routability of the chip is also closely tied to the I/O configuration. Among many issues, one of the key issues in I/O configuration is ứie placement of the power and ground pins. These pins, which could amount to up to one-thừd or more of the total number of I/Os, are placed carefully to reduce or eliminate any IR drop or EM (elecưomỉgration) problem. In a VLSI chip, every smgle transistor needs power to perfonn. The requữed power is deliv­ ered to transistors through a power disừibution network. This network is called the power plan, or power structure, of the chip. This power network must deliver the appropriate voltage level to the ứansistors within the chip for theữ entừe lifetime. The two most critical problems associated with a power network are the IR drop and EM. When the effective resistance of the power network is beyond a certain level (such as that caused by naưow metal lines), the volt­ age drop (/ -R) from tíie source to the destination could be higher than what is tolerable. In such cases, the destination fransistors might not function coưectly. This is the IR drop problem. In addition to IR drop, the cuưent flowing through the metal line is constantly pushing and mov­ ing the metal atoms. The magnitude of this action is proportional to the cuưent density. After a lengthy period of such action, the metal structure can become damaged, and opens or shorts may resuit. This is the elecfa-omigration (EM) problem. The EM problem will negatively affect a product’s lifespan. In today’s chip operation, almost every action inside the chip is operat­ ing on some clock signal. All of the storage elements (flip-flops, latches, and memories) are switched on and off by various clocks. Undoubtedly, the entữe chip operation is coordinated by clocks. Delivering the clock signals reliably to the needed elements is a necessity m physical design. This task is conunonly called clock tree synthesis (CTS). This is done after placement. After the placement of cells, the clock tree is inserted in the design by the layout tool. Figure 3.5 is one floor plan example of a real chip. In this chip, there are almost 400 I/Os, which are located on the chip periphery. About one-third of them are power and ground pins. • There are five PLL (phase locked loop)’s, one DLL (delay locked loop), one high-speed DAC, one large, hard macro on-chip processor, and more than 80 SRAM memories in this mixed-signal chip. • The central area is reserved for standard cells. • The five on-chip PLLs are placed carefully with plenty of space in between. This con­ figuration can effectively reduce interference among the PLLs. • The large hard macro is placed in the lower right-hand comer to minimừe the impact on the chip’s overall routability.

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The analog DAC is also located in one comer to achieve maximum isolation from the rest of the digital blocks. All of the analog blocks (DAC, PLLs, and DLL) have guard rings (see latchup topic) embedded in the cell-level layout to minimize noise coupling from die digital circuitry. Moreover, to fiirther reduce noise coupling, each analog cell has its own ground, which is not metal-connected to the chip’s main digital ground (substrate). This floorplan is the starting point for the subsequent place and route steps. 3.3.10 Placement Placement is a key step in physical design. As the name suggests, placement is the process of placing the cells, or searching for the appropriate location within the chip floor plan for each cell in the netlist. It is a crucial task because poor placement consumes more area. Moreover, it can impair the chip’s speed performance. Poor placement generally leads to a difficult, sometimes impossible, routing task. A more rigorous definition of the term placement fol­ lows: given an electrical circuit (a netlist) consisting of a fixed number of components (cells) and the interconnections that describe the interconnecting terminals on the periphery of these cells and on the periphery of the circuit itself, construct a layout indicating the positions of the cells such that the nets are routed and the total layout area is minimized. A further object of high-performance design is minimizing the total delay of the circuit by minimizing the

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wire length of the critical paths. The quality of placement work is judged primarily by three factors: the layout area, the completion of the routing, and the circuit performance (timing). Optimal cell placement location, not only speeds up the final routing, but also produces supe­ rior results in terms of timing and reduced congestion. The timing driven placement method forces the layout tool to place the cel is according to the criticality of the timing between the cells. After the placement of cells, the clock free is inserted in the design by the layout tool. Users may opt to use more traditioual methods of routing the clock network, for example, using fishbone/spine structure for the clocks in order to reduce the total delay and skew of the clock. As technologies shrink, the spine approach is getting more difficult to implement due to the increase in resistance (thus. RC delays) of the interconnect wires. At this stage an additional step is necessary to complete the clock tree insertion. As men­ tioned above, the layout tool inserted the clock ừee in the design after the placement of cells. Therefore, the original netlist that was generated from DC (and fed to the layout tool), lacks the clock tree information ^essentially the whole clock tree network, including buffers and nets). Therefore, the clock tree must be reinserted in the original netlist and formally verified. Some'layout tools provide direct interface to DC to perform this step. Figure 3.6 is a placement example. There are 129 standard cells and 15 I/O pins in this small design block. The designer first manually places the I/O pins based on his or her understanding of the particular block. Then the placement engine finds the optimal locations for the rest of the standard cells based on the

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locations of these pins and design consừaints. The key optimization taigets are meeting tmmy constraints and minimizing total wừe length. As seen in the figure, the area used for placemogt is split into horizontal rows, which are refeưeđ as cell rows. The standard cells in a libraiy aie often laid out with the same height, as mdicated by ứie height of the cell row, so that they are placed and aligned together. The small rectangular-shaped blocks are various standard cells (d' different widths). The amount of 62% in the figure is the utilization rate, which is calculated as the ratio of the area used by standard cells and the total usable cell row area. From the figure, it seems tìiat the utilization rate should be 1 0 0 % since there is no empty space left in the cell row area. The reason that it is actually 62%, not 100%, is due to the filler cells. There is indeed a certain amount of empty space available after the placement process. However, the empty space is filled with 55 filler cells (the small, naưow cells in the figure) for better manufactuiability. The placement work takes more than 30 hours with a 2 GHz CPU, 16 G byte machine.

3.3.11 Routing After the placement step, the exact locations of the cells and theừ pins are fibced. The next step is to physically complete the interconnections defined in the netlist. This implies using wires (metals) to connect the related terminals within each net. The process of finding the geometaic layouts for the nets is called routing. As a requữement, the nets are routed within a confined area. Additionally, nets must not be short-circuited. In other words, the nets must not electrically intersect each other. The objective of the routing process depends on the nature of the design. In general-purpose designs, it is sufficient to mimmize the total wữe length while completing the connections. In high-performance designs, it is crucial to route each net so that it meets its tight timing target. Special-purpose nets, such as clock, power, and ground nets, requừe special treatment. A VLSI chip might contain millions of transistors. As a result, millions of nets need to be routed to complete the layout. In addition, for each net, there may be hundreds of possible routes. Finding the best possible route is very difficult computationally. The layout tool generally performs routing in two phases—global routing and detailed routing. After placement, the design is globally routed to determine the quality of placement, and to provide estimated delays approximating the real delay values of the post-routed (after detailed routing) design. If the cell placement is not optimal, the global routing will take a longer time to complete, as compared to placing the cells. Bad placement also affects the overall timing of the design. Therefore, to minimize the number of synthesis-layout itera­ tions and improve placement quality, the timing information is extracted from the layout, after the global routing phase. Although, these delay numbers are not as accurate as the numbers extracted after detailed routing, they do provide a fair idea of the post-routed timing. The estimated delays are back annotated to PrimeTime for analysis, and only when the timing is considered satisfactory, the remaining process is allowed to proceed. Detailed routing is the final step that is performed by the layout tool. After detailed route is com­ plete, the real timing delays of the chip are extracted, and plugged into PrimeTũne for analysis. Figure 3.7 shows the global route boxes for the placed design of last figure. The entữe lay­ out area is divided into 100 (10 X 10) small regions that are called global routing boxes. The

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Fig. 3.8 The finished detailed route showing all layers.

global router’s task is to plan the routing configuration in each region such that each cell’s pins in this region are assigned a plan for being connected to the appropriate nets. However the actual metal routing is not accomplished in this step; it is finished in later detailed routing. Figure 3.8 shows the finished routing of this small design block with all of the metal layers shown.

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Fig. 3.9 A detailed route, zoom-in view.

Figure 3.9, which is the zoom-in view of part of Fig. 3.8, shows the six levels of metals in detail. Metal 1, metal3, and metals are used in the horizontal direction, whereas metal2, metal4, and metal 6 are for vertical connections. These steps are iterative and depend on the timing margins of the design. If the design fails timing requirements, post-layout optimization is performed on the design before undeigoing another iteration of layout. If the design passes static timing analysis, it is ready to undergo LVS (layout versus schematic) and DRC (design rule checking) before tape-out. 3.3.12 Design Verification Tools: Layout Versus Schematic (LVS) Layout versus schematic is the process of validating that the layout matches the netlisưschematic. A chip layout consists of millions of geometries of many layers. Certain types of extraction tools are needed to extract the circuit components from these pure geometties. These extraction tools depend solely on specific rules to compose the circuit components from those polygons. Those rules insttaict the extraction tool on how to recognize p and N transistors, capacitors, and resistors from the geometries configuration. LVS is this exttaction process; it ensures that the circuit resulting from the layout agrees with the netlist/schematic. LVS eưors (in which the schematic/netlist does not match the layout) can be very difficult to debug. This is especially true for large chip designs in which there are millions of components on board. It is extremely important for each component used in the chip to be LVS clean at

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the transistor level. Otherwise, the top-level LVS task would become a disaster. Unlike the DRC check, which might allow some unresolved violations, being LVS clean (free of viola­ tions) is an absolutely necessary condition before a design can be sent to manufacturing. Ỉ.3.13 Design Rule Check (DRC) Design rule check is the process of checking that the finished layout complies with the manu­ facturing rules associated with this process and agrees with the schematic/netlist. It focuses on the physical aspects of the design. This verification process has nothing to do with tìie timing or logic aspects of the design. The logic aspects of the design are verified by simulation or hardware emulation. The timing aspect of the design is guaranteed by gate-level simulation with back-aimotated parasitic delay or by static timing analysis. In DRC, a set of design rules check the design’s manufacturability. If design rules are vio­ lated, the design may not fìinctíon. Design rules are a series of parameters provided by semiconduỡtor manufacturers that enable the designer to verify the physical coưectness of the design. Design rules are specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts operate coưectly. Design rules are often specified in terms of a scalable parameter, X, so the geometric dimen­ sions in a design may be defined as integer multiples of x. These rules are called Lambda-based rules. Physical verification software takes a layout in the GDSII standard format as input and produces a report of design rule violations that the designer may or may not choose to coưect. To improve die yields, physical verification has evolved from simple measurement and Boolean checks to more involved rules that modify existing features, insert new features, and check the entữe design for process limitations such as layer density, etc. DRC is a computationally intense task. Unlike in some of the previous implementation steps, at this stage all the detailed informa­ tion is included in the design database since this is the final layout that will be sent to fabrica­ tion. In most designs, the check must be run several times prior to completing the design. For example, the following rules apply to almost all CMOS processes: • • • • • •

Active-to-active spacing Well-to-well spacing Minimum channel length of the transistor Minimum metal width Metal-to-metal spacing Metal fill density.

3.3.14 Tapeout Tapeout is the final step of chip design. It is the time at which the design is fiilly qualified and ready for manufacturing. After the physical design is finished, the functionality of the netlist is

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verified, and the tuning analysis is satisfied, the final layout, usually in GDSn tbimat, IS son til mask shop to generate photomasks. The resultant masks will be used to dữect the manuâctuie of this chip. The term tapeout originally refeưed to the action of writing the final data file dial describes the circuit layout onto magnetic tape. This term is still used today even thougji mag­ netic tapes are now rarely used for this process. More precisely, this process should be calfed pattern generation (PG). As we know, semiconductor device fabrication is a multíple-step sequence of photographic and chemical processing in which electeonic circuits are graduỉdly created on a wafer made of pure semiconductor material. Each of the steps requữes photo­ masks, which are created during the pattern generation process, to guide the operation.

3.3.15 Yield After being fabricated, the semiconductor devices are subjected to a variety of elecừical tests to determine if they can function properly. In general, the fraction of devices that are capable of performing properly is refeưed to as the yield. In detail, there are three types of yield: • Process yield (}p): The percentage of wafers that survive the manufacturing process. • Test yield ( F t ) : The percentage of dies that pass the electrical test. • Assembly yield (}a); The percentage of devices that pass the packaging assembly line. The overall yield is given by y = }p • ỈX • J a-

► In VLSI design what is the difference between digital design and analog design? IC design is the process of building miniaturized electronic components (transis­ tors, capacitors, resistors, diodes, and inductors) on a monolithic semiconductor sub­ strate by photolithography. When properly mterconnected, these components can fonn complicated electrical networks for achieving desữed functions. In general, IC design is divided into the categories of digital and analog design. 1. Digital design produces components such as microprocessors, memories, and digital logics. In digital designs, the main focus is the logical correctness of a design, along with its density, speed, and power usage. 2. Analog designs, on the other hand, are more concerned with the physics of the devices, such as the gain, matching, power dissipation and resistance. Analog design typically refers to the design of such components as op-amps, linear regulators, phaselocked loops, oscillators and active filters

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► Explain the importance of verification ill tìie VLSI design flow. The task of verification must be carried out throughout chip development: during system design stage, during the logic design stage, after logic synthesis, and after the place and route stage. Verification can be performed at different levels dxuing these stages: system level, RTL level, gate level, and even fransistor level. In summary, verification is a very significant aspect of the chip development proj­ ect. It is a never-ending process canied out xmtil the chip is ready for production. In some cases, functional bugs are continually foxmd even after the design is aừeady being used in the field as a qualified product. More than one-half of the chip develop­ ment effort in large VLSI projects is often spent on verification. ► What is timing verification? Timing verification is tìie process of checking that the finished chip layout can operate up to the speed defined in the product definition. Unlike functional verifica­ tion, which addresses chip functionality, timing verification focuses on chip timing or speed. A reliable product must run at the designed speed with wealc/strong ttansistors, high/low metal and via resistance and capacitance, high/low temperatures, and high/ low power supply voltages. Before the design is sent to manufacturing, the chip’s tim­ ing behaviour under all combinations of these conditions needs to be checked against design consừaints. Timing verification is earned out by either gate-level simula­ tion or static timing analysis. In both cases, the impact of parasitic components must be included in the process.

3.4 THE DESIGN INTEGRITY ISSUES Some of the design integrity issues to be taken care in the design process are discussed below: 1. The cữcuit speed depends more on interconnecting wire delay than on logic gate delay. As process geometry gets smaller, the interconnecting wires correspondingly get closer. Thus, the cross coupling through the coupling capacitance between the wires has become more severe. This interference between different signal paths certainly degrades signal quality. For example, interference can make the device operate incoưectly, more slowly, or even fail completely; and it can create yield problems. This crosstalk problem is ứie most crucial issue in the design integrity arena. 2. Electromigration (EM) is another design integrity issue. It is the unwanted transport of material caused by the gradual movement of the ions in a conductor (such as the cop­ per and aluminium used in ICs) due to the momentum transferring between conducting electrons and diffusing metal atoms. Electromigration decreases the reliability of ICs. It leads to the eventual loss of one or more circuit connections and, consequently, the fail­ ure nf the entire cữcuit. Because layout geometries are smaller now, the ciưrent densities

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inside wires are correspondingly higher. As a result, the practical significance of flie, electromigration problem increases. 3. For any chip to function coưectly, the logic cells inside the chip must be ^ovided WÍÉ adequate power supply voltage. This task of power distribution over the chip is achieved by the power grid (made of metals) on the chip. When electrical current flows throu^ a metal (which behaves as a resistor), it produces a voltage difference between the en& of this metal. This voltage difference is referred as the IR drop. The degree of IR drq» over the power grid must be within a certain limit so that an acceptable voltage level can reach the cells on the chip. Otherwise, the chip performance degrades. Since there are often large cuưents present in the power grid geometries, the power buses are especially sensitive to IR drop, as well as to EM. 4. Anotìier design integrity issue is associated with the gate oxide of a ữansistor and is referred as gate oxide integrity (GOI). A GOI check is a method of checking that none of the on-chip MOS transistor gates experience voltages higher tìian they are designed for, for extended periods. Such occurrences could damage the gate structure and cause the chip to fail. 5. Electrostatic discharge (ESD) also is a serious issue in solid-state electronics. It is the sudden and momentary electric current that occurs when an excess of electric charge finds a path from an object at one electrical potential to another object at a different potential. ESD events occur only among insulated objects that can store electric charge, not among conductors. Because transistors within IC chips are made from semiconduc­ tor materials of silicon and insulating materials such as silicon dioxide, they can suffer permanent damage when subjected to the high voltages of ESD events. Manufacturers and users of integrated circuits must take precautions to avoid this problem. During IC design and the implementation stage, special design techniques are employed so that device input and output pins, which are exposed to the outside world and subjected to ESD events, are not damaged from such events. 6 . The problem of latch-up also falls into the design integrity category. It is the unintended creation of a low impedance path between the circuit’s power supply rails. Such an occurrence of a low impedance path can trigger certain parasitic devices within the cir­ cuit structure, which then act as a short circuit and lead to failure. Worst of all, this large short-circuit current can lead to a circuit’s destruction. Thus, during the design phase, a c irc u it is d e sig n e d to be latch u p resistan t. L ay e rs o f in su la tin g o x id e s th a t surround

both the nMOS and the pMOS transistors can break the parasitic structure between these transistors and thus prevent the latchiip. T h e se p ro b le m s are th e m a jo r issu es in th e d esig n in te g rity arena. T h e se d e sig n in te g rity prob­ lem s e ith e r cau se th e ch ip to m a lfu n c tio n im m e d ia te ly o r im p a ir th e life sp a n o f th e chip. T hey

are among the reasons that make today’s VLSI circuit design veiy challenging. 3.5 THE ROLE OF EDA TOOLS IN 1C DESIGN D u rin g the v ery e a rly y ears o f IC d e sig n , the ch ip s w ere b u ilt b y m a n u a lly lay in g o u t every

transistor of the circuit on a drawing boarc It is unimaginable how many man-years would be

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equữed to design modem chips in this outdated way. It is the elecfronic design automation EDA) tools that fundamentally changed the IC design and made today’s multimillion gate lesigns possible. In today’s chip design envửoiunent, there are many EDA tools to help designers perform heứ work. Each of them targets a ispeciiic application. The synthesis tool raises the design abstraction level from device/transistor to RTL, which s the single most significant factor ứiat makes modem VLSI design feasible. The most commonly used EDA tools in today’s IC design envữonments include: 1. Simulation tools at the transistor level, switch level, gate level, RTL level and system level. 2. Synthesis tools that translate and map the digital RTL code to real library cells. 'i. Place and route tools, which perform the automatic layout based on various design consfraints. o 4. Logic verification tools, which include formal verification tools and simulation tools. 5. Tĩme verification tools, which verify the design’s timing quality. 6.

Physical verification tools, which verify the design’s layout against manufacturing rules.

7. Design fo r testability tools, which integrate testability into design and generate test patterns. 8.

Power analysis tools, which perform power dissipation analysis and IR drop analysis.

9. Design integrity tools, which check a design’s reliability-related issues, such as ESD, latchup, EM, GOI, and antenna. 10. Extraction tools, which exfract the design’s parasitics for back annotation. 11. Rule checkers for checking the design’s logical and electrical compliance with coưesponding rules. 12. Package design and analysis tools. As the integration level rises and chip size decreases, the requirements for EDA tools have been pushed in the directions of faster and larger. In other words, to perform a specific task on a large VLSI design, the corresponding EDA tool must have the capability of handling the necessary data as one integral part (without separating it into smaller pieces) and finish the task within a reasonable time schedule. With continuous innovations from the EDA industry and aided by ever-improving computing hardware, EDA tools have kept pace with the design complexity explosion reasonably well. In summary, EDA tools make up the foundation of today’s IC development activities. By utilizing these tools, engineers create miraculous wonders that are changing our world.

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What is Parasitic Extraction in design process? After the cells are placed, the real electrical connections are achieved metal wứes. The cells and the wires have resistance and capacitance that affect IỈK cuưent travelling through them. As a consequence, they impact tìie signal pn^)agiH tion timing. Parasitic extraction is the process of extracting tìie exact resistance and capacitance values associated with each metal segment so that theừ impact on signal delay can be precisely determined the layout is composed of many metal segments. After the parasitic exttaction process, the metal connections are represented by an RC network. In the past, when process geometry was much larger than what we are usiog today, the impact of parasitic R and c were not as crucial since the signal ừaveỉlỉng time was primarily dominated by the cell’s delay. As process geometty contim i^ shrinks, parasitic delay has gradually become a dominant factor. >■

Explain how delay calculation is done for a circuit in the design process. After the parasitic extraction process, the interconnecting metal wừes are trans­ formed to an RC network. Eventually, the impact of this RC network on signal propa­ gation delay must be converted to a delay number to determine the operatmg speed of the chip. This conversion process is called delay calculation. Delay calculation has two parts: the calculation of the delay of a logic gate and the calculation of the del^ caused by the wires attached to it. >■

^ What is Back annotation? Back annotation is the process of adding the extra delay caused by the paiasitic components back into the original timing analysis, which only has the timing from the cells’ delay. Gate-level simulation and static timing analysis (STA) are the two most commonly used approaches in verifying a chip’s timing performance. BoÉ of the methods can verify the chip’s operating speed against the design specification. In practice, they can be used only with the gate delay information (without the parasitics), as is often done by designers in early design phases. However, in later design stages, when the place and route step is finished and the physical information is avail­ able, simulation and timing analysis must be earned out by reading the back-anno­ tated SDF file into the design. Back-annotated static timing analysis is a step that must be performed before the chip can be taped out for manufacturing. ► Gate-level verification is very important before the design is sent to the tape out why? Gate-level logic verification is the last verification step before the design is shipped for manufacturing. When the design is in its early stages, it is verified by simulation at the system and RTL levels. After logic synthesis, the design presents itself as a gate-level netlist. This netlist will be physically implemented in layout and eventually

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sent to a manufacturing facility for production. Therefore, the functional correctness of this netlist is very important since ứiis is the logic entity that will be turned into silicon chip. A high degree of confidence in the netlist is requừed before it can be sent to manufacturing. Gate-level verification is the last chance to check for any func­ tional problems. Gate-level verification can be performed by gate-level simulation, preferably with back-annotated parasitic components (RC network delay discussed in the previous topic).

3.6 DESIGN STRATEGIES There are foiư structured design strategies in chip design they are: o 3.6.1 Hierarchy The other name for Hierarchy is “divide and conquer”. A VLSI structure should be divided into modules. Again modules are divided into sub-modules. This process is repeated until the basic building blocks are reached so that they can be designed and analyzed independently of the rest of the circuits. We already studied that a design can be expressed in terms of these domains namely structural domain, behavioural domain and physical domain. Let the basic building block be a simple adder. This adder can be modelled as a subroutine (function) in behavioural domain, as a gate connection diagram in structural domain and as a layout in physical domam. This work can be carried out in parallel with domain-to-domain comparison ensuring that the representations are consistent. 3.6.2 Regularity Hierarchy can divide the system into basic level but does not solve the problem complexity. We are left with different sub-modules. Each sub-module is standardized. It can be used as basic unit that can repeated in the circuit. The use of the standardized regular structures simplifies the design process. For example, at circuit level, uniformly sized ttansistors can be used instead of manually optimizing each tran­ sistor. This manual work consumes lot of time similarly at logical level, a gate is standardized and similar gates are used. At the system level it may consist of identical processors. Methods for formally proving the correctness of a design may be aided by regularity. Regularity allows an improvement in productivity by reusing specific designs in the number of places; thereby reducing the number of different designs that need to be completed. Regularity needs to identify the common operations at a higher level and repeat the stan­ dardized architecture. Regularization can reduce the number of different modules that need to be designed and verified.

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•3 Modularity

)dularity ensures that sub-modules have well defined functions and interfaces. Interfeces are iware subroutmes. If they are designed well, proper conuniinicátỉon witii other modules is ỉsible. In IC world cells are to be placed side by side (concàtenàtion), repetition of tiiese Is as an array in memory (iteration), selecting only a set of transistors while progranuning a i*LA (conditional section) is done. Hence, concatenation, iteration and conditional selection are important constructs in structured programming. Modularity helps the designer to clarify and document an approach to a problem and allows a design system to more easily check die attributes of a module as it is constructed. 3.6.4 Locality Locality should be more for a design. For instance increasing locality means local common clock, and hence synchronous timing methods apply. The first way of ensuring time locality is to pay attention to clock generation and its distribution network. Next step is to concentrate on critical paths in each module, i.e., concentrate on an issue from highest level of point of view and try to minimize the eưors in each next level of the system. These four properties are sttuctured design strategies for designing an IC.

1. In VLSI design process, there are three distinct design domains, namely Behav­ ioural domain which specifies the software implementation of the system’s functionality. Structural domain which specifies how modules are connected together to effect the prescribed behaviour. Physical domain which specifies the layout used to build the system according to the architect’s idea from ttansistor level. 2. The design idea refined into a set of requirements is known as specification. 3. HDL allows the description of the structure of a hardware system. 4. Register transfer level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a Cttcuit, from which lower-level representations and ultimately actual wuing can be derived. 5. Logic simulation is the primary tool used for verifying the logical coưectness of a hardware design. 6 . The logic correctness of the RTL description is checked by simulation by applying test vectors or by running test bench program. 7. Logic synthesis is the process of translating an abstract form of desired cừcuit behaviour (typically in RTL) into a design implementation in terms of logic gates.

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8.

The optimization targets of a logic synứiesis task are speed, area, and power. 9. Static timing analysis (STA) is a method of computing the expected timing of signals inside a digital circuit without using simulation. 10. The layout tool generates the layout and performs the placement and routing. 11. Placement is the process of placing the cells, or searching for the appropriate location within the chip floor plan for each cell m the netlist. 12. Routing is related to physically complete the interconnections defined m the netlist.

1.

___________allows the description of the structure of a hardware system. 2 . ___________is the primary tool used for verifying the logical coưectness of a hardware design. 3. __________ is the process of teanslating an abstract form of desired circuit behaviour into a design implementation in terms of logic gates. 4. The optimization targets of logical synthesis are_____________ . 5. _____________is a group of standard cells glued together as a package. 6 . Logic optimization aims a t_____________ of silicon area. 7. _____________ is process of checking the designs fiinctional correctness. 8 . ___________ is the method of computing the expected timing of signals inside a digital circuit using simulations. 9 . ____________ network must deliver the appropriate voltage level to the tran­ sistors witiiin the chip for their entire lifetime. 10. Delivering the clock signals reliably to needed elements on the chip is known a s _____________________________________ . Answers 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

HDL Simulation Synthesis Speed, Area, Power ASIC library Reduction Verification Static timing analysis Power Clock trees synthesis

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VLSI Circuit Design Process

CHAPTER OBJECTIVES In this chapter, you will be introduced to • • • • • •

MOS layers Stick diagrams Layout Design rules CMOS scaling Scaling parameters

4.1 MOS LAYERS In the final step of VLSI design process, design specifications are converted into masks for sili­ con processing. MOS cữcuits consists of four basic layers—n-dififijsion-diffiision, polysilicon and metal. Each of these layers are isolated from one another by insulating material like silicon dioxide. VLSI design aims to ữanslate circuit concepts onto silicon. This is done by using stick dia­ grams and layouts. 4.2 STICK DIAGRAMS As already discussed, a VLSI circuit may be viewed as a 3-dimensional set of patterned mate­ rial layers. Stick diagrams provide a top view of the patterns. A stick diagram can be thought

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s a simplified version of layout. Stick diagrams are useful fo r planning the iạyouí and n§f. rtg o f integrated circuits. In a stick diagram, every line of a conducting material layer is rạ. esented by a line of a distinct colour. The colours allow us to trace signal flow paứis tfarougjh he conducting layers in a complex integrated circuit. Planning a physical design using stick liagrams before going to CAD tool can save lot of time and energy. Other properties of stick diagram include • • • • •

A stick diagram acts as an interface between symbolic cữcuit and the actual layout. It does show all components/vias. It shows relative placement of components. Goes one step closer to the layout. Helps plan the layout and routing.

A stick diagram does not show • • • •

Exact placement of components. Transistor sizes. Wữe lengths, wire widths, tub boundaries. Any other low level details such as parasitic, etc.

Hence, a stick diagram is a cartoon o f a layout. Stick diagrams are often used to solve routing problems. In our study, we will use the basic colour coding as shown in Fig. 4.1. Rules for drawing Stick Diagrams Rule 1 When two or more ‘sticks’ of the same type cross or touch each other that represents elecừical contact (Fig. 4.2). Rule 2 When two or more ‘sticks’ of different type cross or touch each other there is no elec­ trical contact. (If electrical contact is needed we have to show the connection explicitly) (Fig. 4.3). R ules When a poly crosses diffusion (i.e., red over green) it represents a MOSFET. This is consis­ tent with a top view of the transistor. Note: If a contact is shown, then it is not a transistor. Figure 4.4 shows the stick diagram for nMOS transistor. A pFET is described by the same “red over yellow” coding, but the crossing point is con­ tained within an n-well boundary (Fig. 4.5). For a depletion mode MOSFET implantation is shown in Fig. 4.6.

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Metal 1 Polysilicon n-difiiision p-difiiision Fig. 4.1 Colours for various layers in stick diagrams.

Fig. 4.2 Electrical contact.

Fig. 4.3 No electrical contact.

Fig 4.4

MOSFET.

Fig. 4.5 pMOSFET.

Fig. 4.6 Depletion Mode MOSFET.

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4.2.1 nMOS Design Style Following are the steps to draw stick diagram of nMOS logic: Step 1: Draw the metal (blue) VpD and GND rails in parallel leavmg sufficient space for ofllit circuit components between them. Step 2: Thinox paths (green) are drawn between the rails for inverters and inverter based logic circuits. Remember nMOS logic consists of depletion mode nMOSFET as the pull up device and nMOS logic network as pull down in the circuit. Hence, n-dififiision (for source and drain regions of the MOSFETs) is earned out in common for both pull up and pull down network. This is represented by a green line (representation for n-diffusion) known as thinox line. Step 3: Connect polycross over thinox wherever transistors are reqmred. Note: Don’t forget the implants for depletion mode fransistor and writmg L:W ratio near each transistor. Signal paths are switched with pass transistors and long signal paths are fabricated with metal wires (blue). Example 1: Let us draw the coloured stick diagram of a simple nMOS inverter (Fig. 4.7). The equivalent layout diagram for nMOS inverter can be drawn from its stick diagram. (For help refer CMOS layout diagram discussed m the next topic.)

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► Draw the stick diagram for Y = AB + CD using nMOS design style (Fig. 4.8).

''DD

Đ

D

Fig. 4.8 Stick diagram for AB + CD.

ầ ã ã CMOS Design Style 1. In CMOS a demarcation Ime is drawn to avoid touching of p-diff with n-diff. All pMOS (red or yellow) must lie on one side of the Ime and all nMOS (red on green) will have to be on the other side. 2. To create CMOS logic gates, we start with the V d d and GND lines. We will use a hori­ zontal orientation for the lines. Remember that stick diagrams only deal with the rout­ ing. Widths and spacings are not important. 3. Dififiision (yellow and green) paths must not cross the demarcation line and n-difiRision and p-diffusion wires must not join. The n and p features are normally joined by metal wherever a connection is needed. Crossed are to be placed on Vd d and GND lines to mdicate the substrate and P-well connection respectively. «

► Draw the stick diagram of a simple CMOS inverter (Fig. 4.9). T h e ex am p le in Fig. 4 .1 0 sh o w s th e d raw in g o f stick diagram ©f 2-input N O R gate. D ra w the stick d iag ram f o r /== ((A -B ) + C ) (Fig. 4.11a).

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''DO

OUT

Fig. 4.10 Stick diagram for 2 input NOR gate.

f=(A+B)4C ''DD

Vdd

Out

A B GND

Ground Fig. 4.11(a) stick diagram for N ((A B)+C).

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4.3 LAYOUT Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the repre­ sentation of an integrated cừcuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semicondiictor layers that make up the components of the integrated cứcuit. A layout engineer’s job is to place and connect all the components that make up a chip so tìiat they meet all criteria. Tj^ical goals are performance, size, and manufacturability. The layout must pass a series of checks in a process known as verification. The two most common checks in tíie verification process are Design Rule Checking (DRC), and Layout Versus Sche­ matic (LVS). When all verification is complete the data is ữanslated into an industry standard fonnat, typically GDSII, and sent to a semiconductor foundry. The process of sending this data to the foundry is called tapeout due to the fact the data used to be shipped out on a magnetic tape. The foundry (IC fabricating mdustry) converts the data into another format and uses it to generate the photomasks used in a photoliứtogrãphỉc process of semiconductor device fabrica­ tion. Modem IC layout is done with the aid of IC layout editor software, or even automatically usiag tools, including place and route tools or schematic driven layout tools. Figure 4.11(b) shows the layout diagram of CMOS inverter along with ứie schematic.

(tubs not shown) out

Fig. 4.11(b) CMOS inverter layout diagram with schematic.

What is a tub tie? A tub tie is the connection made from the device layer to the tub to apply the bias. Figure 4.12 shows the layout of 2-input NAND gate. Figure 4.13 shows the layout of 2-input NOR gate.

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b—

Fig. 4.12 Layout and schematic of 2-input NAND gate.

Fig. 4.13 Layout and schematic of 2-input NOR gate.

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AA DESIGN RULES Design rules allow the translation of cữcuit design concepts in symbolic form into actual geometry in silicon. Design rules are a series of parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of his or her mask set. Design rules are specific to a particular semiconductor manufacturing process. Design rules are the effective interface between the cừcuiưsystem engineer and fabrication engineer.

4^.1 Design Rule Checking Software The main objective of design rule checking (DRC) is to achieve a high overall yield and reli­ ability for the design. If design rules are violated, the design may not be functional. To meet this goal of improving die yields, DRC has evolved from simple measurement and Boolean checksfto more involved rules that modify existing features, insert new features, and check the entừe design for process limitations such as layer density. A completed layout consists not only of the geometric representation of the design, but also data that provides support for the manufacture of the design. While design rule checks do not validate that the design will oper­ ate coưectly, they are constructed to verify that the structure meets the process constraints for a given design type and process technology. DRC software usually takes as input a layout in the GDSII standard format and a list of rules specific to the semiconductor process chosen for fabrication. From these it produces a report of design rule violations that the designer may or may not choose to correct. Carefully “stretching” or waiving certain design rules is often used to increase performance and compo­ nent density at the expense of yield. DRC is a very computationally intense task. If run on a single CPU, customers may have to wait up to a week to get the result of a Design Rule check for modem designs. Most design companies require DRC to run in less than a day to achieve reasonable cycle times since the DRC will likely be run several times prior to design completion. With today’s processing power, full-chip DRCs may run in much shorter times as quick as one hour depending on the chip complexity and size. Some example of DRCs in IC design include: • • • • • • •

Active to active spacing Well to well spacing Minimum channel length of the transistor Minimum metal width Metal to metal spacing Metal fill density (for processes using CMP) BSD and I/O rules

• L a m b d a b a s e d d e sig n ru les.

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»

-MSHISBL ^ What are the various elements on ICs? 1. Conducting layers which form wữes • Many layers of wires (4-5 metal layers) which has electrical properties sudi as resistance and capacitance • Contacts and insulators between layers 2. Transistors • MOS transistors and Bipolar transistors (when BiCMOS is used) 3. Passive elements like resistors, capacitors and inductors.

4.4.2 Design Rules for N-well According to the Fig. 4.14, ROl—Minimum well size is 12A, R02—Minimum well to well spacing is 11A, R03—Minimum surface area of the well is 144A.^ 4.4.3 Design Rules for n-Diffusion and p-Diffusion R201—Minimum n^-diff and width is 2X R202—Minimum spacing between two n^-diff and p'^-diff is 3A. R203—Extension of n-well after is 6 X R204—Minimum spacing between n'^-diff and n-well is 6 Ằ R205—Border of well after n+ bias in n^-well is 2Ầ R206—Distance between n-well and p^-bias is 6 Ằ See Fig. 4.15. R102:12X

Fig. 4.14 [ ỉsign rules for N-well.

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Fig. 4.15 Design rules for n-diffusion.

4 4 4 Design Rules for Wires (Conduction Paths) These design rules specify ứie minimum distances and widths of ứie wừes (or conduction paths) to be followed in fabrication. 1. For Metal 1, ininimum widtii should be 3Ằ, and tninimum separation from another metal 1 wừe is 3X2. For Metal 2, Tninimum width should be 4X and minimum separation from another metal 2 wữe is 4A~ 3. For polysilicon w e ứie minimum width is 2k and minimum separation from anoứier polysilicon wữe is 2X. This separation is also called as poly-poly separation. 4. If the wừes are p- and n-difíìision wừes, minimiun width of each wữe is 21. and mini­ mum separation between n-diffiision wke and another n-difiRision wữe is 3^. Same is valid for p-diflfusion wừes also. 5. The Ttiinimiim separation between n-difiusion/p-diffusion wữe and poly silicon wire is IX. The above rules are shown in Fig. 4.16.

AA,5 Basic Construction Rules for Transistor The smallest transistor is of widdi 2k and lengứi 2k. Figiire 4.17 shows the layout diagrams of nMOS (enhancement mode and depletion mode) and pMOS (enhancement mode) transistors.

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Fig. 4.16 Design rules for wires.

nMOSFET (Enhancement)

pMOSFET (Enhancement)

nMOSFET (Depletion)

Fig. 4.17 Construction rules for transistors.

Consider the layout of nMOSFET of depletion mode shown in Fig. 4.18. Note: From here after all rules are referred as Rl, etc., implying R stands for “rule”. 1. R1—separation from contact cut to transistor is 2A.. 2. R2—implant for an nMOS depletion mode transistor has to extend in all directions. 3. R3—separation from implant to another transistor is 2X.

from the channel

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R1,R2

R2 R3

Fig. 4.18 Layout of nMOSFET depletion mode.

For better understanding of the layout, consider the following figure of the layout of CMOS inverter. Consider the following transistor layout shown in Fig. 4.19: 1. R4—diffusion should not decrease in width at least before 2Ằ, from the polysilicon. 2. R5—^polysilicon should extend from diffusion at least by 2X. 4.4.6 Design Rules for Contact Cuts Contact cuts are also known as via cuts. Cuts are 2X and 2X in dimension. They are used to connect two wires on different layers. The material on both layers to be connected extends lA, in all directions making total contact size 4A, X 4X. (Fig. 4.20.) Available contact cut types are a) b) c) d)

n/p diffusion to polysilicon polysilicon to metal 1 n/p diffusion to metal 1 metal 1 to metal 2

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Fig. 4.19 Transistor layout rules.

4X

7k <---------- ►

4X Fig. 4.20 Design rules for contact cuts.

Contact between polysilicon and diffusion wires Let us study briefly about various possible approaches to connect polyslicon and difiiision wires. There are 3 possible approaches to do the contacts. 1. Polysilicon to the metal and then metal to polysilicon 2. Buried contact 3. Butting contact The detailed explanation about each is given below. 1. Polysilicon to the metal and then metal to polysilicon Oxide is removed from 2k X 2k contact cut down to the underlying polysilicon wữe. Then metal is poured (deposited). It flows through the oxide etched area to the polysilicon area. Then polysilicon is deposited on the surface, which acts as the conduction path.

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I. Buried contact Before starting the process, ứiere is oxide layer on the silicon surface, oxide is etched to expose tìie underlying silicon and polysilicon is deposited on the surface. In the next step, diữiision is carried out into the exposed surface. When diffiision takes place impurities will difiiise into polysilicon as well as difiused area withm tiie contact area. This ensures a satis­ factory connection between polysilicon and difiusion. Buried contacts are smaller than butting contacts discussed in the next section. The figure for butting contact is given in Fig. 4.21. 3. Butting contact Butting contact is a complex process. A 2k X 2k contact cut is made down to each layers to be jomed. Layers are butted together so that two contact cuts become contiguous. The

Difilision Wừe

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polysilicon and diffusion outlines the overlap and thin oxide under polysilicon acts ỊU|j mask in the diffusion process. Polysilicon and diffused layers are butted together. The C(»> tact between two layers is then made by metal overlay as shown in Fig. 4.22. 4.5 DOUBLE METAL MOS PROCESS RULES In this process a second metal layer is used so that Vdd and Vss (GRND) rails in tìie system are distributed much more flexibly on the chip vias are used to establish connection betweoi metal 2 to other layers through metal 1 this is shown in the following Fig. 4.23. The contacts between metal 1 and metal 2 are known as vias rather than contact cuts.

► What is the use of metal 2 in the fabrication process? Second level metal is used for global distribution of Vdd and GND and for clocklines while the first metal is used for local distribution of power and signal lines. The two metal layers are orthogonal to each other wherever possible. ► What are certain problems in design rules if the spacing and width between! different layers is too small? If wire widths are very small it is possible that discontinuities occur in the line which appear as open circuits. If different wires in the same layer are placed too close together, it is possible that they merge at some places and contributes for short circuit. They may also cause interference of signals flowing in the wires.

4.6 CMOS LAMBDA BASED RULES The rules for n-well (for pMOS transistors), p-wires and special substrate contacts are added to the existing nMOS rules, which we have discussed till now. The rules are readily translated to an n-well process. Although CMOS rules in total seem difficult to comprehend for new designer once use has been made of simpler nMOS rules the translation to CMOS is not hard to achieve. 4.7 DESIGN RULES FOR METAL 3 1. Minimum metal 3 width is 6 A, and minimum separation is AX from metal 2. 2. Available via from metal 3 is to metal 2. Connections from metal 3 to other layers must be made by first connecting to metal 2 then to metal 3 .

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INTRODUCTION: CMOS SCALIN6

Over the past three decades, CMOS technology scaling has been a primary driver of tíie elec­ tronics industry and has provided a paứi toward boứi denser and faster integration. The ưansistors manufactured today are 2 0 times faster and occupy less than 1 % of ứie area of tfiose built 2 0 years ago. The number of devices per chip and the system performance has been improvmg exponen­ tially over the last two decades. As the channel length is reduced, the performance improves, ứie power per switching event decreases, and ứie density improves. But ứie power density, total cữcuit^ per chip, and the total chip power consumption has been increasmg. The need for more performance and integration has accelerated the scaling breads m almost every device parameter, such as lithography, effective channel length, gate dielectric ứiickness, supply volt­ age, device leakage, etc. Some of these parameters are approaching fundamental limits, and alternatives to the existing material and structures may need to be identified in order to con­ tinue scaling. Q Original Device

Scaled Device

Vdd!^

I

p-Substrate, Doping Fig. 4.23 MOSFET scaling.

T h e b a s ic id e a o f s c a lin g a s s h o w n in th e F ig . 4 .2 3 is t o r e d u c e th e d im e n s io n s o f th e

Thus, the arrangement on the right side as the figure is scaled down in size from that on tìie left by reducmg all dimensions by a factor a.

M O S tr a n s is to r s a n d w ir e s ( in te r c o n n e c ts ) c o n n e c tin g th e m in th e in te g r a te d c ir c u its .

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There are three scaling models: 1. Constant field scaling All tìie parameters in the MOSFET are scaled by ứie factor a excq)t supply voltage Fdb and gate oxide thickness tox1 . Constant voltage scaling The supply voltage VpD and gate oxide thickness t o x are scaled down by p. 3. Combined voltage and dimension scaling model This is combined model of constant field and constant voltage scaling. W h e th e r i t K a lp h a o r b e ta , s c a lin g r e d u c e s t h e d im e n s io n s o f t h e tr a n s is t o r s o ih a t m m d e v ic e s a r e p a c k e d o n th e c h ip a n d in r e tu r n th e p e r f o r m a n c e in c r e a s e s .

Let ÌÌS look at the thừd scalmg model of constant voltage and dimension model of scaling. The MOS transistor works on the principle of modifymg ứie electric field in tìie siiicon substtate underneath ứie gate m such a way to conữol the flow of current between die source and drain. Scaling achieves same electric field in the smaller ữansistor by reducmg the applied voltage and thickness of the oxide by p along with all key dimensions by a. Let us look at die scaling of certain parameters. 4.9SCALING PARAMETERS Gate area

Ag = L x w A g is c a le d ) = ư x W '

=k a

K a

a?

Gate capacitance per lulit area

Z)/p

= PQ Gate capacitance C g —Co x A g

VLSI Circuit Design Process

Cg {scaled) = C o {scaled) X Á g {scaled)

rge in channel (when MOSFET is turned on) Qo„ (charge/unit area) = C o X V g s Q on

{scaled) = p C o

X

—^ = Qg„

Channel resistance R on R on= ^~

w ot

a is the conductivity t is the channel thickness L L= JL _ i_ w ơt ~w ổo„n R,„(scaled) = ^ - ^ w / a Qo„\i —Ron Transistor delay Td — Ron XCg Tj(scaled) = Ro„Cg — = \ t, a? Maximum operating frequency /m

Td

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VLSI Design

Transistor cuưent T

_

C o ịíW

2

L~^

’

, ,...., „ _ { ĩ c M ”'i»)(ros I^(scaled)= 2(i/o) u _ Ids p Switching energy

E(scaled) = ^ - ^ C g 1

Power dissipation per gate - static power - dynamic (switching) power Static p ,-=Ym_ P Ps{scaled) = ^p2- -;ị = ^p2 Dynamic

=— P

r, pj

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Power dissipation per unit area

a

129

oc —

scales to

Ag/a^ „2

Scaling factor is — p' Power-delay product scales by 4 r ~

=

Note: ỉ'or constant field scaling a = p and for constant voltage scaling p = 1. 4.10 DIFFICULTIES ARISING DUE TO MOSFET SCALING Producing MOSFETs with channel lengths much smaller than a micromeữe is a challenge, and tìie difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated cừcuit technology. In recent years, the small size of the MOSFET, below a few tens of nanometres, has created operational problems. They are 1. 2. 3. 4. 5. 6. 7.

Higher sub-threshold conduction Increased gate-oxide leakage Increased junction leakage Lower output resistance Interconnect capacitance Heat production Process variations

4.10.1Higher Sub-TKreshold Conduction Because of small MOSFET geometries, the voltages that can be applied to the gate must be reduced as well to maintain reliability. As threshold voltage is reduced as well, the transistor cannot be completely turned off. The transistor operates in a weak-inversion mode, with a sub-threshold leakage between source and drain. The standby power of a CMOS chip due to source-to-drain sub-threshold leakage is given by ỉọ ff- = ^ lo i V d d

I off

= W,ot Vd d lo

exp ' - q V t ^ m kT,

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where Wtot is the total tumed-off device width with Vd d across the source and drain, IqgfísỀI^ average off-cuưent per device, lo is the extrapolated current per width at ứưeshold voltage, é is a dimensionless ideality factor, and Vt is the threshold voltage. The ofif-state leakage cunai would increase by about ten times for every 0.1 V reduction of Vf. For a chip with an integtation level of 1 0 0 million transistors, the average leakage current of tumed-ofif devices shoidd not exceed a few times 10“* A. This consữaint holds the threshold voltage to a minimum of about -0.2 V at the operating temperature (100°c worst case).

4.10.2 Increased Gate-Oxide Leakage The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor ỈỈ on and to reduce sub-threshold leakage when the ttansistor is off. However, with current gsfe oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantoi mechanical phenomenon of electron tunnelling occurs between the gate and channel, leadfflg to increased power consumption. Insulators (refeưed to as high-k dielectrics) that have a larger dielecttic constant than silic^' dioxide, such as group IVb metal silicates, e.g. hafriium and zirconium silicates and oxidạ' are being used to reduce the gate leakage from ứie 45 nanometre technology node onwaall^ Increasing the dielectric constant of the gate dielectric allows a thicker layer while maW taining a high capacitance. (Capacitance is proportional to dielectric constant and inversd^ proportional to dielectric thickness.) A higher dielectric thickness reduces the quantum tiiimeiling cuưent through the dielectric between the gate and the channel. On the other hand, 4e barrier height of the new gate insulator is an important consideration; the difference in conduc­ tion band energy between the semiconductor and the dielectric (and the coưesponding difference in valence band energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 eV. For many alternative dielecfrics the value is significantly lower, tending to increase the tunnelling cuưent, somewhat negating Ée advantage of higher dielectric constant. 4.10.3 Increased Junction Leakage To make devices smaller, junction design has become more complex, leading to higher doping levels, shallower junctions, etc., to decrease drain-induced banier lowering. Drain Induced Barrier Lowering Drain induced baưier lowering or DIBL is a secondary effect in MOSFETs referring origi­ nally to a reduction of tíireshold voltage of the transistor at higher drain voltages. This can be understood by the Yau charge-sharing model. The combined charge in die depletion Tcpoa of the device and that in the channel of the device is balanced by three electrode changes: the gate, the source and the drain. As drain voltage is increased, the depletion region of Ihe p-n junction between the drain and body increases in size and extends under the gate, so the

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Length Fig. 4.24 Drain induced barrier lowering.

drain assumes a greater portion of the burden of balancing depletion region charge, leaving a smaller burden for tìie gate. As a result, the charge present on the gate retains charge balance by attíạcting more carriers into the channel, an effect equivalent to lowering the threshold voltage of the device. In effect, the channel becomes more attractive for electrons. In other words, the potential energy barrier for electrons in the channel is lowered. Hence, the term “barrier lowering” is used to describe these phenomena. Barrier lowering increases as channel length is reduced, even at zero applied drain bias, because the source and drain form p-n junc­ tions with the body, and so have associated built-in depletion layers associated with them that become significant partners in charge balance at short channel lengths, even with no reverse bias applied to mcrease depletion widths. As channel length decreases, the barrier ỘB to be surmounted by an electron from the source on its way to the drain reduces. This unplies the leakage current even when the device is switched OFF. The lowered poten­ tial makes elecừons to move towards source end. As the depletion region below the gate is large, the electrons are drifted towards drain and contribute for OFF state leakage cuưent.

4.10.4 Lower Transconductance The teansconductance of the MOSFET decides its gain and is proportional to hole or elec­ tron mobility (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the ttansconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the cuưent and the transconductance. 4.10.5 Interconnect Capacitance Traditionally switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip,

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interconnect capacitance (the capacitance of the wữes connecting different parts of the < is becoming a large percentage of capacitance. Signals have to travel tíưough the intencoaneGl which leads to increased delay and lower performance.

4.10.6 Heat Production As more transistors are mtegrated on a chip to enable more functions and a higher frequrac is used to obtain an increased performance, the total power consumption increases and resultg , in more heat. The active power of a CMOS chip (crossover currents are usually negligible), is given by Pac = C,o,VDD^f

where Ctoi is the total node capacitance being charged and discharged in a clock cycle, and / is the clock frequency. As CMOS technology advances, clock frequency goes up. The total switching capacitance is likely to increase as well, as one tries to integrate more cừcuits into the same or an even larger chip area. The active power of today’s high-end microprocessors is aừeady in the 50-100 w range. Integrated circuits operate slower at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling methods are now required for many integrated circuits including microprocessors.

«

► Explain the benefits of scaling. The steady downscaling of MOSFET devices dimensions over the past two decades has been the main stimulus to the growth of CMOS integrated cữcuits. Scaled MOSFETs are desừable for a few main reasons. Scaled MOSFETs allow more onrent to pass. Conceptually, MOSFETs are like resistors in the on-state, and shorter resistors have less resistance. Furthermore, since scaled MOSFETs have lower gate capacitance, and since the amount of charge on a gate is proportional to its capacitance, logic gates incorporating scaled MOSFETs have less charge to move. Indeed, these two factors combined contribute to lower switching times, and thus higher operating speeds. Another important reason for MOSFET scaling is a reduced area, leading to a reduced cost. Scaled MOSFETs can be packed more densely, resulting in either smaller chips or chips with more computing power in the same area. Smce tìie cost of fabricating a semiconductor wafer is relatively fixed, the cost of producing integrated circuits is mainly related to ứie number of chips ứiat can be produced per wafer. Hence, smallo' integrated cừcuits allow more chips per wafer, reducing the price per chip.

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^ What is punch through in a MOSFET and what is to be done to avoid it? As tíie channel length is scaled down the edge of the dqjletion region around the soiirce comes closer to that around the drain. This situation is kBown as punch through. When this occurs the charge earners in tìie channel will be drifted from source to drain by the eiecttic field in the merged depletion region. Gate loses its controlling capability, i.e., the MOSFET cannot be switched OFF. In order to prevent punch through and maintam transistor action the channel length L must be at least be 2 d, where d is the width of the depletion layer. ^ When the device dimensions are scaled down how does the depletion regions around the source and drain is affected. In the MOSFET, there are two pn junctions around sowce and drain areas. The width of the depletion region is given by V

V

qNs

Nb = Substrate doping V = Applied voltage across the jixnction (built-in voltage esi = Relative permittivity of silicon (12) Go = Permittivity of free space (8.85 X lO"*"* F/Cm)

Vb +

supply voltage

Vdd )

Note: Compared to supply voltage, built-in voltage is very small and is hence neglected and v= Vdd. In general, the depletion regions around source and dram junctions should be kept separated else when the device is scaled down they meet. This situation is known as punch through and the gate terminal looses its control over the channel. Hence, the depletion regions should be scaled down by a, according to our scaling principles. To achieve this V should be scaled down by p and hence Nb will be scaled by aVp. If we consider constant field scaling (P = 1) the doping concenữation of the substrate should be increased by aĩ but this arises a problem. When the doping concentration is increased to avoid the punch through condition, the amount of gate voltage required to invert the surface in the formation of the channel increases, i.e., threshold voltage mcreases. Again this is m conữast to our scaling principles. Hence, the doping con­ centration is increased only near the source and drain junctions and kept as usual in the channel area. Again if doping concenfration near the source and drain regions is mcreased the e le c tric al field in the junction might reach its critical value and may break down. This leads to tunnellmg across the junctions. Hence, a proper limit for increasing the dop­ ing should be realized for a particular process technology.

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>■ Explain quantitatively how the number of circuits can be increased IB a given chip area with no increase in total power dissipation. 1. The density of the chip increases by as the lengtíỉ and widdi are decreased by a and the intercoiuiects are also scaled. 2. The speed which is related to g j c improves by the factor a because the capacitance of the shorter (scaled) wữes and smaller wữes is reduced by p/a^. The ữansconductance gm remains unchanged (as length and width are both scaled by a). 3. The power dissipation per cữcuit is reduced by a factor because of reduced voltage Vdũ and cuưent lj)s in each device with important result that power density is constant. Thus, the increased number of cữcuits in a given chip area can be accommodated with no mcrease in the total power dissipation.

4.10.7 Limits of Interconnect and Contact Resistance The wiring required to interconnect transistors must scale at the same rate as the ừansistors in order to take advantage of the improvements in size and speed. The traditionally switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, the capacitance of the wires connecting different parts of the chip is becoming a large percentage of capaci­ tance. Reducing the wiring resistance and the inter-layer film capacitance is crucial to propa­ gating the high-speed pulses generated in a CMOS device with little delay and waveform distortion. Despite these major changes in materials, there is a concern that owing to higher resistivity and capacitance, the exữemely small wires will be unable to support performance enhancements. Solutions: 1. Use multilayer interconnections with thicker, wider conductors and thicker separating layers. This will reduce both R and c and also reduce size. 2. Use cascaded drivers and repeaters to reduce the effects of long interconnects. 3. Use optical interconnection techniques. To use these techniques optical fibres, laser diodes, receivers and amplifiers must be included in the integrated circuit. 4. As the dimensions of the interconnect structures continue to shrink, aluminium-based interconnects are being replaced by lower-resistance copper metallurgy, which can decrease both the wiring resistance and the capacitance. A research is also underway to move from the CVD oxide/nitride interlayer dielectrics between wmng levels to various low-dielectric-constant insulators, which can further decrease the wuing capacitance.

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1. MOS cừcuits consists of four basic layers—^n-diffiision p-dififusion, polysili­ con and metal. Each of these layers is isolated from one another by insulating material like silicon dioxide. 2. Stick diagrams are useful for planning the layout and routing of integrated circuits. 3. When a poly crosses diffusion (i.e., red over green) it represents a MOSFET. This is consistent with a top view of the transistor. 4. Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geomet­ ric shapes which coưespond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. 5. A tub tie is the connection made from the device layer to the tub to apply the bias. 6 . Design rules are a series of parameters provided by semiconductor manufac­ turers that enable the designer to verify the coưectness of his or her mask set. Design rules are specific to a particular semiconductor manufacturing process. 7. The need for more performance and integration has accelerated the scaling trends in almost every device parameter, such as lithography, effective channel length, gate dielectric thickness, supply voltage, device leakage, etc. 8 . The basic idea of scaling is to reduce the dimensions of the MOS transistors and wires (interconnects) connecting them in the integrated circuits.

1. 2. 3. 4. 5. 6.

The colour of polysilicon gate is The colour of metal 1 in stick diagram i s ______________ . ____ are useful for planning the layout and routing in integrated circuits. The colours allow to trace____________ ^through conducting layers. An nFET is formed whenever____________ crosses_____ ■ In self-aligned gate process, the polysilicongate pattern and field oxide ac as _________ ^to the or drain/source implant. 7. Widths and spacings are not important in ____________. 8 . A stick diagram is schematic representation of circuit at ■ 9. Minimum spacing between well-to-well is____________. 1 0 . ___________ is used to run FoD and ground lines. 11. The separation from implant to another transistor is

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Answers 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

Red Blue Stick diagrams Signal flow paths Red, green Mask Stick diagram Physical design level lú Metal 2

11. 2Ằ

Gate Level Design

CHAPTER OBJECTIVES In ứiỉs chapter, you will be introduced to • • • • • • • • • •

CMOS logic gates and other complex gates Basic cừcuit concqjts Sheet resistance Unit capacitance Delay unit Inverter delays Driving large capacitive loads Super buffers BiCMOS drivers Propagation delays

5.1 CMOS LOGIC GATES AND OTHER COMPLEX GATES 5.1.1 CMOS Static Logic Static, fixlly complementary CMOS gate designs using inverter, NAND and NOR gates can build more complex functions. These CMOS gates have good noise margins and low static power dissipation at the cost of more transistors when compared with other CMOS logic designs. CMOS static complementary gates have two transistor nets (nMOS and pMOS) whose topologies are related. The pMOS transistor net is connected between the power supply and

ts

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VLSI Design

le logic gate output, whereas the nMOS transistor topology is connected between die o u ^ ad ground (Fig. 5.1). We saw this organisation with the NAND and NOR gates, but we point ut this topology to lead to a general technique to convert Boolean algebra statements to MOS electronic cữcuits.

Inputs

Output

GND Fig. 5.1 Standard configuration of a CMOS complementary gate.

The transistor network is related to the Boolean function with a straightforward design procedure: 1. Derive the nMOS transistor topology with the following rules: • Product terms in the Boolean function are implemented with series-connected nMOS transistors. • Sum terms are mapped to nMOS transistors connected in parallel. 2. The pMOS transistor network has a dual or complementary topology with respect to ứie nMOS net. This means that serial transistors in the nMOS net convert to parallel ttansistors in the pMOS net, and parallel connections within the nMOS block are translated to serial connections in the pMOS block. 3. Add an inverter to the output to complete the function if needed. Some functions are inherently negated, such as NAND and NOR gates, and do not need an inverter at the output state. An inverter added to a NAND or NOR function produces the AND and OR function. The examples below require an inverter to fulfil the function. This procedure is illustrated with three examples. Example 1: Design a complementary static CMOS XOR gate at the transistor level. The XOR gate Boolean expression F has four literals and is F = xy+ xỹ. F is the sum of two product terms. The design steps are: 1. Derive the nMOS transistor topology with four transistors, one per literal in the Boolean expression. The transistors driven by X and y are connected in series, as well as die

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devices driven by X and ỹ . These transistor groups are connected in parallel, since they are additive in the Boolean function. The signals and theừ complements are generated using inverters (not shown). The nMOS transistor net is shown in Fig. 5.2. out

Fig. 5.2

2. Implement the pMOS net as a dual topology to the nMOS net. The pMOS ừansistors driven by X and y are connected in parallel, as are the devices driven by X and ỹ (Fig. 5.3). These transistor groups are connected in series, since they are parallel connected in the nMOS net. The out node now implements F.

pMOS net

Fig. 5.3 3

Finally, add an inverter to obtain the function F, so that F = out.

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Example 2: Oesign the nMOS transistor net for a Boolean function F = X + ị ỹ ’ [z + (i • i^]}. We desip [his gate with a top-down approach. The nMOS transistor network is connected between tbe Jutput and ground terminals, i.e., the lower box in Fig. 5.4(b). The higher-level function F is Ì sum of two terms: F = X + {operation A} where operation A stands for the logic within the brackets of F. The ưansistor version of this sum is shown in Fig. 5.4(a).

Serial connection A 4

I I I

y • { Operation B }

nMOS net Fig. 5.4(a)

Fig. 5.4(b)

Hence, the design topology is a transistor conữolled by input ỹ in series with a thừd box that will implement operation B, as shown in Fig. 5.4. We then design the topol­ ogy of box B. This is a transistor controlled by input z, in parallel with two teansistors connected in series; one controlled by input t, and the other by input w. The complete nMOS network is shown in Fig. 5.4(b). Once the nMOS block is designed, we build the pMOS block with a dual topological structure and then connect an inverter to its output, as shown in Fig. 5.6. 5.1.2 Transmission Gate Logic A transmission gate is an electronic element. It is a good non-mechanical relay, built widi CMOS technology. Sometimes known as an analog gate, analog switch or electronic relay depending on its use. It is made by the parallel combination of an nMOS and a pMOS ưansistor with the input at the gate of one transistor being complementary to the input at the gate of the other. Cuưent can flow through this element in either direction. Depending on whether or not there is a voltage on the gate, the connection between the input and output is either low-resistance or high-resistance, respectively. Ron =100 ohm and R o ff> 5 megaohm. The operation can also be understood this way; when the gate input to the nMOS ưansistor is ‘O’, and the complementary ‘1’ is gate input to the pMOS, both are turned off. However,

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A

Ả IN —

— OUT

Fig. 5.5 Basic transmission gate.

o when gate input to the nMOS is ‘1’ and its complementary ‘0’ is the gate input to the pMOS, both are turned on and passes any signal ‘ r or ‘0’ equally well without degradation. The use of ừansmission gates eliminates the undesừable tìưeshold voltage effects which give rise to loss of logic levels in pass-ừansistors. The above logic was invented as a solution to problems of earlier CMOS logics. It enables certam logic functions to be implemented wiứi fewer ttansistors than possible using odier CMOS logic. This logic can be used to design multiplexers. It would seem that ã transmission gate could be constructed using simply a single pMOS or nMOS teansistor. If only an individual nMOS transistor were to be used, and there was a high voltage out the OUT and a low voltage on the IN and we are trying to transmit the zero to the OUT, then the nMOS will drain some of the voltage but not all of it leaving the OUT some­ where m the ‘no mans’ voltage region of digital cữcuits. Adding the pMOS gate in parallel allows all the voltage to drain after the nMOS shuts off before all the voltage is drained. This also solves the problem when transmitting a high voltage to OUT. 5.13 Tri-State Gates Many logic gates require a tri-state output—high, low, and high-impedance states. The highimpedance state is also called the high-Z state, and is useful when connecting many gate out­ puts to a single line, such as a data bus or address line. A potential conflict would exist if more th a n one gate output tried to simultaneously control the bus line. A controllable highimpedance-state circuit solves this problem. There are two ways to provide high ũnpedãtice to CMOS gates. One way provides tristate output to a CMOS gate by connecting a transmission gate at its output (Fig. 5.7). The con­ trol signal c sets the ữansmission gate conducting state that passes the non-tristated inverter output ÕŨĨ to the tti-stated gate output out. When the transmission gate is off (C = 0), then its gate o u tp u t is in the high-impedance or floating state. When c = 1, the transmission gate is on and the o u tp u t is driven by the inverter.

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A ữansmission gate connected to ứie output provides tri-state capability, but also consumes xinnecessary power. The design of Fig. 5.7 conữibutes to dynamic power each time that the input and output (out) are switched, even when the gate is disabled m the tri-state mode. Parasitic capacitors are charged and discharged. Since the logic activity at ứie input does not conbibute to the logic result while the output is in tri-state, ứie power consumption related to ứiis switching is wasted. This can be avoided by putting a transmission gate “inside” the inverter (Fig. 5.8).

Fig. 5.7 Inverter with a transmission gate to provide tri-state output.

The pMOS and nMOS transistors of the transmission gate are in series wittiin the conduct­ ing path between the power and ground rails and the inverter ừansistors. When ứie gate is in the tri-state mode, the ũiner transistor source nodes float, and the output is isolated from supply and ground. The activity at the inverter output signal node does not consume power as long as the gate is in the high-Z state (C = 0). A tri-state capability adds delay independent of the configuration, due to the extra resistance and capacitance of the traasistors driven by the tri-state control signal.

Gate Level Design

In

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Out

Fig. 5.8 Schematic and symbol. The transmission gate “inside” the inverter provides tri-state output.

5.14 Pass Transistor Logic o There are many pass ưansistor (pass gate) logic subfamilies, and we shall describe a few. Pass transistor logic uses ừansistors as switches to cany logic signals from node to node, ũistead of connecting oulput nodes dứectly to Vdd or ground. If a single fransistor is a switch between two nodes, then voltage degradation equal to Vị for the high or low logic level is obtamed, depend­ ing on tíie nMOS or pMOS teansistor type. CMOS fransmission gates avoid these weak logic voltages of single-pass ừansistors at the cost of an additional transistor per transmission gate. Advantages are the low number of ữansistors and the reduction in associated interconnects. The drawbacks are the limited driving capability of these gates and tíie decreasing signal strength when cascading gates. These gates do not restore levels since theừ outputs are driven from the inputs, and not from Vdd or ground. A typical CMOS design is ứie gate-level multiplexer (MUX) shown in Fig. 5.9 for a 2-to-l MUỊX. A MUX selects one from a set of logic mputs to connect wiứi the output. In Fig. 5.8, tìie logic signal c selects eiứier ứ or Ốto activate ứie oulput {out). Figure 5.9(b) shows a MUX design with ttansmission gates. The complementary CMOS gates (Fig. 5.9(a)) reqinre 14 teansistors (four transistors for each NAND and two transistors to complement the conttol signal), whereas the trans­ mission gate design requứes only six devices (more tìian 50% reduction). Each ừansmission gate has two transistors plus two more to invert die control signal.

— Out Out

Fig. 5.9 (a) standard 2-Ỉ0-1 MUX design, (b) Transmission (pass) gate-based version.

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A

Out

B

Fig. 5.1Ũ 8-transistor XOR gate and truth table.

Another pass gate design example is the XOR gate that produces a logic one output when only one of the inputs is logic high. If both inputs are logic one or logic zero, then the output is zero. Figure 5.10 shows an 8 -ừansistor XOR gate having a tti-state buffer and teansmiặ sion gate with their outputs connected. Both gates are controlled by the same input through a complementary inverter (A-input in this case). The XOR gate of Fig. 5.10 is not a standard complementary static CMOS design since tìiere is no nMOS transistor network between the output and ground, nor is there a pMOS transistor net between the output and the power rail. The XOR standard CMOS design built previously requires fourteen transistors, whereas the design in Fig. 5.10 requires only eight. 5.1.5 Dynamic CMOS Logic Previous sections showed conventional static CMOS circuit design techniques and designs based on tri-state gates and pass transistors. These designs are static, since they do not requừe a clock signal for combinational cừcuits. So, if cữcuit inputs are stopped (elapsed), then the cữcuits retain their output state (all cữcuit nodes remain at their valid quiescent logic values) as long as power is maintained. Dynamic CMOS logic families do not have this property, but do have the following advantages: 1. They use fewer transistors and, therefore, less area. 2. Fewer transistors result in smaller input capacitance, presenting a smaller load to previ­ ous gates, and therefore faster switching speed. 3. Gates are designed and iransistors sized for fast switching characteristics. High perfor­ mance circuits use these families. The logic transition voltages are smaller than in static circuits, requiring less time to switch between logic levels. The disadvantages of dynamic CMOS circuits are 1. Each gate needs a clock signal that must be routed tìirough the whole cữcuit. This requires precise timing control. 2. Clock circuitry runs continuously, drawing signiiicant power.

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3. The circuit loses its state if the clock stops. 4. Dynamic circuits are more sensitive to noise. 5. Clock and data must be carefully synchronized to avoid eưoneous states. Dynamic CMOS Logic Basic Structure A dynamic CMOS gate implements the logic with a block of transistors (usually nMOS). The output node is connected to ground through an nMOS ừansistor block and a single nMOS evaluation transistor. The output node is connected to the power supply through one precharge pMOS toansistor (Fig. 5.11). A global clock drives the precharge and evaluation transistors. The gate has two phases: evaluation and precharge. During precharge, the global clock goes low, turning the pMOS transistor on and the evaluation nMOS off. The gate output goes high (it is precharged) while the block of nMOS transistors float. In the evaluation phase, the clock is driven high, turning the pMOS device off and the evaluation nMOS on. The input signals detennine if there is a low or high impedance path from the output to ground since the global cl(ftk turns on the nMOS evaluation teansistor. This deisign eliminates the speed degradation and power wasted by the short-circuit cuưent of the n- and p-channel transistors during the transition of static complementary designs. If the logic state determined by the inputs is a logic one (Vdd) then the rise time is zero. The precharge and evaluation transistors are designed to never conduct simultaneously. Dynamic circuits with an «-mput gate use only n + 2 transistors mstead of the 2« devices requứed for the complementary CMOS static gates. Dynamic CMOS gates have a drawback. If the global clock in Fig. 5.11 is set high, then the output node could be in high-Z state wiứi no electtical path to Vd d or ground. This exposes the node to noise fluctuations and charge sharing within the logic block, thus degrading its voltage. Also, the output load capaci­ tor will slowly discharge due to transistor off-state leakage currents and lose its logic value. This limits the low-frequency operation of the circuit. The gate inputs can only change dur­ ing precharge, since charge redistribution from the output capacitor to internal nodes of the nMOS logic block may drop the output voltage when it has logic high. Finally, dynamic gate

Global clock

Precharge fransistor Out

Evaluate transistor Fig. 5.11 Basic structure of a dynamic CMOS gate.

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cascading is challenging since differences in delay between logic gates may cause a slow gaH to feed an eưoneous logic high (not yet evaluated to zero because of the dday) to die iwtf gate. This would cause the output of the second gate to be erroneously zero. Different clai. ing strategies can avoid this, as shown next. 5.1.6 Domino CMOS Logic Domino CMOS was proposed in 1982 by Krambeck et al. It has the same steucture as dynamic, logic gates, but adds a static buffering CMOS inverter to its output. In some cases, ứiere is also a weak feedback ữansistor to latch the internal floating node high when die output is iow (Fig. 5.12). This logic is the most common form of djmamic gates, achieving a 20%-50% per­ formance increase over static logic. When the nMOS logic block discharges the ÕŨĨ node dur­ ing evaluation (Fig. 5.12), the inverter output out goes high, turning off the feedback pMOS. When out is evaluated high (high impedance in the dynamic gate), then the inverter outpiừ goes low, turning on the feedback pMOS device and providing a low impedance path to Fpo, This prevents the out node from floating, making it less sensitive to node voltage drift, nois^ and ciurent leakage. Domino CMOS allows logic gate cascading since all inputs are set to zero during Ịnecharge, avoiding eưoneous evaluation from different delays. This logic allows static operation from the feedback latchmg pMOS, but logic evaluation still needs two subcycles: precharge and evaluation. Domino logic uses only non-inverting gates, making it an incomplete log^ family. To achieve inverted logic, a separate inverting path running in parallel with the noninverted one must be designed. Multiple output domino logic (MODL) is an extension of domino logic, taking mterad nodes of the logic block as signal outputs, thus saving area, power, and performance. Com­ pound domino logic is another design that limits the length of the evaluation logic to prevent charge sharing, and adds other complex gates as buffer elements (NAND, NOR, etc. instead

Latch

Global clock

r 1 transistor Out

Evaluate ừansistor Fig. 5.12 Domino CMOS logic gate with feedback transistor.

Gate Level Design

J

GC -

r L

D

147

GC n

r

i

L

i

Fig. 5.13 NORA CMOS cascaded gates.

of inverters) to obtain more area compaction. Selfrresetting domino logic (SRCMOS) has eaclbgate detect its own operating clock, thus reducing clock overhead and providing high performance. NORA CMOS Logic. This design alternative to domino CMOS logic elinunates the out­ put buffer witfiout causing race problems between clock and data that arise when cascading dynamic gates. NORA CMOS (No-Race CMOS) avoids these race problems by cascading alternate nMOS and pMOS blocks for logic evaluation. The cost is routing two complemented clock signals. The cascaded NORA gate structure is shown in Fig. 5.13. When the global clock (OQ is low (ỠC high), the nMOS logic block output nodes are precharged high, while outputs of gates with pMOS logic blocks are precharged low. When the clock changes, gates are in the evaluate state. 5,1J Other CMOS u^ic Families Dynamic cừcuits have a clock disừibution problem, since all gates must be functionality syn­ chronized. Self-timed circuits are an alternative to dynamic high-performance cừcuits, solv­ ing the clock distribotion by not requiring a global clock. This simplifies clock routing and mmimizes clock skew problems related to clock; distribution. ITie global clock is replaced by a specific self-timed communication pròtocol between circuit blocks in a request-acknowledge scheme. Although more robust than dynamic circuits, self-timed logic requires a higher design effort than other families. These gates implement self-timing (i.e., derivation of a completion signal) by using differential cascade voltage switch logic (known as DCVS) based on an extension of the domino logic. The DCVS logic family (Fig. 5.14) uses two complementary logic blocks, each similar to the domino structure. The gate inputs must be in the true and complementary form. Since out­ put ttue and output negated are available, they can activate a completion signal when the out­ put is evaluated. Since the gate itsedf signals when the ou^ut is available, DCVS cán operate at the maximum speed of the technology, providing high performance asynchronous circuits. T h e m a j o r drawbacks are design complexity and increased size,.

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a

VLSIDesigR

ì R ì .5 l 1 4 Basic DCVS logic gale.

Sã M S K Q K V I T C M N B T S S J .1 S h M C le s is ta M iU y

The sbcct resstasce is a measore of resistance o f tfain films that have a unifonn thktona It is ccHnmonly used to dtaracterize materials made by semiconductor doping, mâaỉ dquMftin^ resistive paste jHinimg, and glass cootiog. Exan^)ies of these processes are: defied scmieaedDctcH- regicns (e.g., sflkxn w polysilkxn), and die resiskMS. Sieet resistance is qipbcable to tw«M&iiensi(Hial systems where t e diin film is c n iiiliicd to be a two-dimoisioaid entity. It is aoadogous to resistivity as Iised in three-dimaiãaBal ^ terns. WhCT ứie teim dieet resistance is used, the cmrent must be flowing along die pbne of the sheet, not petpendiciilar to it Conàda' a unifonn dab of c
w,

_ p L .__

K_4g = — onm

wiiere A is area of ooss-secticm. Thus, Rab = R.4B

pL

ohm i Consider a case in which L — w that is square o f ứie resistive maienal ữien Rab = - = Rs whCTC R, is <*ni per sqoare or dieet resistaiice.

Thos,

Rf

= — ohm per square.

dũdoiess

t

Gate Level Design

a

149

Fig. 5 .15 Sheet resistance model.

From the above equation Rs is independent of the area of the square. For example, a 1 Jim per side square slab of the material has exactly same resistance as a 1 cm per side square slab of the same material if the ứiỉckness is same. Hence, the resistance of the MOS layers depend on the thickness and the resistivity of the material of ứie layer. The thickness of the metal and the polysilicon dqjosited is known by measuring using four probe method. The resistivity of the diffusion layers is measured by measiuing the peneứatíon deptíi of the diffusion regions. Sheet RtsistaB itCoM tplApiriM to M M Capacitanaiiể Inverters

Consider ứie following transistor structures shown in ứie Fig. 5.16. The active area of the device is L x w, where L is the length of the channel and w is the widtii of ứie channel. For Polysilicon. N-difiRision

R g . 5.16 Resistance calculations for transistor channels.

ISO

o

VLSI Design

the given values 0Í expressed as

L

= 2X

and

ỈV = 2X,

the active device area is a square. Resistance Cffli I I

Ji = 1 square X Rs ———= iỉí = 10^ Q square The value of Rs for various MOS layers is given in the following Table 5.1. Table 5.1 Rg ( o h m / s q u a r e )

(5 fim process)

L ayer

suicide

0.03 1 0 -5 0 2 -4

Polysilicon N-transistor Channel P-transistor Channel

15-100 10^ 2.5 X lo'*

Aluminium N Diffusion

Resistance can also be defined in terms of impedance z, i.e., L ! W . Consider the Fig. 5.17 (b) z = LIW = 4, thus the channel resistance is /?= Z R s =

ARs

= 4 X10^ Q

(value of R s frpm the table is lo'* ohm/square). Another way of looking at this is to think of tíie channel as four squares in series each 2A. X 2X, in dimension. This method is useful when we need to calculate the resistance o f com­ plex polygon shapes. 5.2.3 Calculation of ON Resistance of a Simple inverter Consider the simple nMOS inverter in Fig. 5.17(a), V,DD 'D D

8X;2X

4X-AX

- 0

2X:2X

Vss

(a)

''ss

(b) Fig. 5.17 Inverter resistance calculations.

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151

• For tiie pull-up transistor (depletion mode MOSFET) the L:W value is 4:1, hence tíie value of 2 is 4. Ron = 4 and value of on resistance is ARs, i.e., 4 X 10^ = 40 kí2. • Similarly, for the pull down ừansistor (enhancement mode MOSFET) the L:W value is 1:1 hence the value of z is 1. /?0„ = 1 and value of resistance is IRs, i.e., 1 x10^ = 10 kí2. • Zp,u to Zpj = 4 :1 hence the ON resistance between Vdd and K55’ is the total series resis­ tance, i.e., 40 kí2 + 1 0 k£2 = 50 kfí. Consider the simple CMOS inverter in Fig. 5.17(b), • For the pull-up transistor (p-enhancement mode MOSFET) the L:W value is 1:1, hence, the value of z is 4. Ron = 4 and value of on resistance is 4 Rs, i.e., 1 X 25 X lo'* = 25 kí2 (from the table value of Rs for p-chaimel transistor is 2.5 X 10^ ohm/square). • Similarly, for the pull down fransistor (n-enhancement mode MOSFET) the L:W value is 1:1 hence the value o f z is

Ỉ. Ron =

1 and value o f resistance is 1 R s , i.e., 1 X 10"*= 10 kí2.

•oin this case, there is no static resistance between Vdd and Vss since at any point of time only one transistor is ON, but not both. • When Vi„= 1, the ON Resistance is 10 k£l, when Vi„ = 0 the ON Resistance is 25 k£2. 5.2.4 Area Capacitances of Layers From the concept of the fransistors, we studied, it is apparent that as gate is separated from the channel by gate oxide an insulating layer, it has capacitance. Similarly, different interconnects run on the chip and each layer is separated by silicon dioxide. For any layer knowmg ứie đielecừic ứiickness, we can calculate ứie area capacitance as follows: D where A is area of the plates and D is thickness of the silicon dioxide. Egio = permittivity of msulator or dielectric. Area capacitance is given in pF/ịim^. Typical values of area capacitance are given below in Fig. 5.18 for 5 fxm process.

Capacitance Gate to channel Diffusion Polysilicon to substrate Metal 1 to substrate Metal 2 to substrate Metal 1 to metal 1 Metal 2 to polysilicon

Value in 1®^ pF/pm^ (relative value in brackets) 4(0.1) 1 (0.25) 0.4 (0.1) 0.3 (0.075) 0.2 (0.05) 0.4 (0.1) 0.3 (0.075)

Relative value = specified value/gate to channel value for that technology.

152

a

V Ls rO e s l^ n

Vakie in pF x .io ^ /p m ^ .^ k tiv e values in bradkiM y Capacitance Gate to channel Diffusion (active) Polysilicon* to substrate Metal 1 to substrate Metal 2 to substrate Metal 2 to metal 1 Metal 2 to polysilicon

4

1 - 0.4 0.3

0,2 0.4 0.3

IJZmn

'2

5 fxm (1.0) (0.25) (0.1) (0,075) (0.05) (0.1) (0.075)

.8 1.75

0.6 0.33 0.17 0.5 0.3

(1-0) (0.22) (Õ.075) (0.04) (0.02) (0.06) (0.038)

16 3.75

0.6 0.33 0.17 0.5 0.3

(1.0) (0 ^ ) (0.038) (0.02) (0.01) (0.03) (0.018)

Notes: Relative value = specified value/gate to channel value for that techn(Hogy. *Poly. 1 and Poly. 2 are similar (also silicides where used).

Fig. 5,18 Typical values of area capacitances.

5.2.5 Standard Unit of Capacitance DC^ It is convenient to employ a standard unit of capacitance that can; bẹ givea ạ value ỉQ^ropiriạts to the technology but can also be used in calculations without associating it with an absolute value. The unit is denoted by O C g and is defined as gate to channel capacitance of a MOS transistor having = z, = feature size that ịs standard. □ Cg may be calculated for any MOS process. For example for 5 |im MOS circuits Area/standard sqaure = 5 fxm X 5 fim = 25 \im?Capacitance value from the table above = 4 X 10^ pF/p,m^ Thus, standard value DCg = 25 X 4 X 10“^ pF/jim^ = 0.01 pF 5.2.6 The Delay Unit T We have developed the concept of sheet resistance R s and standard gate capacitance unit □Cg. If we consider the case of one standard (feature size square) gate area capacitance being charged through one feature size square of n-channel resistance (that is, through Rs for an nMOS pass transistor channel), as in Fig. 5.19, we have Time constant T = (l/?/(n -ch an n el) X 1 DCg) seconds

This can be evaluated for any technology and for 5 ụ.m technology, X = lo'* ohm X

0.01 pF = 0.1 nsec

In the above approach, the calculated delay is device delay, hence, weneed to consider cừcuit wiring and parasitic capacitances must be allowed for so that thefigure taken for Xis often increased by a factor of two or three so that for 5 )am circuit the worst case delay will be around X = 0.2 to 0.3 nsec.

Gate Lével Design

à

153

0 .6 3K oo

Note that T thus obtained is not much different from transit time mulas (from Chapter 2).

Tsd

calculated from the for­

VinVoS Note than V d s varies as Cg changes from 0 volts to 63% of V d d in period X, in the Fig. 5.19, so that an appropriate value for V d s is the average value = 3 volts. For 5 |L im technology, then _ 25|xm^V sec 10^ n sec cm^ = 0.13 nsec “ 650cm23V ^ lOVm^ This is very close to the theoretical time constant X calculated above. Smce the ừansition point of an inverter or gate is ữ.SVpD, which is close to 0.63 it appears to be common practice to use ttansit tune and time constant (as defined for the delay unit t) interchangeably and ‘sừay’ capacitances are usually allowed for by doublmg (or more) the theoretical values calculated. 5.2.7 Inverter Delays

5.2.7.1 nMOS Inverter Pair ữeíay Consider the basic 4:1 ratio nMOS inverter. In order to achieve the 4:1 Zp u. to Zp,d, ratio, Rp u. will be 4Rp.d. and if Rp,d. is contributed by the miniminn size transistor then, clearly, the resis­ tance value associated with Rp,u_ is Rp.u.

= 4 /?, = 40 kí2

Meanwhile, the Rpj. value is = 10 kii so that the delay associated with the inverter will depend on whether it is being turned on or off.

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VLSI Design

5t

-

4t

iT

Fig. 5.20 nMOS inverter pair delay.

However, if we consider a pair of cascaded inverters, then tíie delay over the paữ will be constant iưespective of the sense of the logic level ưansition of the input to the first. This is clearly seen from Fig. 5.20 and, assuming X = O.Snsec and making no extra allowances for wiring capacitance, we have an overall delay of T + 4 t = 5x. In general terms, the delay through a pair of similar nMOS inverter is ^

+ ^p.u. !

Thus, the inverter pair delay for inverters having 4:1 ratio is 5 t. A single 4:1 inverter exhibits undesirable asymmetric delays since the delay in turning on is, for example, X, while the coưesponding delay in turning off is 4x. Quite obviously, the asymmetry is worse when considering an inverter with an 8 :1 ratio. 5.2.7.2 Minimum Size CMOS Inveter Pair Delay When considering CMOS inverters, tìie nMOS ratio rule no longer applies, but we must allow for the natural (Rs) asymmeừy of the usually equal size pull-up p-transistors and ứie n-type pull-down ữansistors. Figure 5.21 shows the theoretical delay associated wiứi a paừ of minimum size (both n- and p-transistors) lambda-based inverters. Note ứiat ứie gate capacitance (=2DCg) is d o u b le that of the comparable nMOS inverter since the input to a CMOS mverter is connected to both transistor gates. Note also tìie allowance made for ứie difiering channel resistances. The asymmetry of resistance values can be eliminated by increasing the width of the p-device channel by a factor of two or three, but it should be noted that the gate input capaci­ tance of the p-transistor is also increased by the same factor. This, to some extent, ofifsets the speed-up due to the drop in resistance, but there is a small net gain since the wừing capaci­ tance w ill be the same.

Gate Level Design

o

5J.8 A More Formal Estimation vf CMOS Inverter Delay A CMOS inverter, in general, either charges or discharges a capacitive load Cl and rise-time tr, or fall-time tf can be estimated from the following simple analysis. Rise-Time Estimation In this analysis we assume that tìie p-device stays in saturation for the entire charging period of the load capacitor C l - The cữcuit may tíien be modelled as in Fig. 5.22. The saturation cur­ rent for the p-transistor is given by

,

» p (ra s-\r^ \f

ỉdsp -

-

This cuưent charges Cl and, since its magnitude is approximately constant, we have ỉdsnt y''out nut "" ~ Q Substituting for Idsp and rearranging, we have 2Ciyout

t =-

h { V G S - K \)

We now assume that

t = tr

when

Vout

=+

Vd d , s o

that

2V d d C l

tr =

h (V D D - K \) With

V tp\= 0 2 V d d ,

then 3C i tr =

^pVoD

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VLSI Design

^DD

out

Fig. 5.22 Rise-time model.

This result compares reasonably well wiA a more detailed analysis in which the chaiging of C l is divided, more coưectly, mto two parts: ( 1 ) saturation and (2 ) resistive region of the toansistor. Fall-Time Estimation Similar reasoning can be applied to the discharge of C l through the n-tranisistor. The cừcuit model in this case is given as Fig. 5.23. Making similar assumptions, we may write for fall-time:

Fig. 5^23 Fall-time model.

Gate Level Design

o

Ị57

, = iB l Summary of CMOS rise and fall time factors Usmg these expressions, we may deduce that; ! ỉl = Ế l

But ụ.„ = 2.5 ụ.p and hence p„ -s-2.5Pp, so that the rise-time is slower by a factor of 2.5 when using minimum size devices for both ‘n’ and ‘p’. In order to achieve symmetrical operation using minimum channel length, we would need to make Wp = 2.5 w„ and for minimum size lambda-based geometties this would result in the inverter having an input capacitance of Q

inC g (n - device) + 2.5DCg (p - device) = 3.5DCg in total.

• This simple model is quite adequate for most practical situations, but it should be rec­ ognised that it gives optimistic results. However, it does provide an insight into the factors which affect rise-times and fall-times as follows: and i/are proportional to HVoD', tr and i/are proportional to Ci; 3. ir = 2 .5 //for equal n-and p-transistor geometries. tr

2.

5.3 DRIVING LARGE CAPACITIVE LOADS The problem of driving comparatively large capacitive loads arises when signals must be propagated from the chip to off chip destinations. Generally, typical off chip capacitances may be several orders higher them on chip DCg values. For example, if the off chip load is denoted Cl then C l > lơ*nC g (typically)

Clearly capacitances of this order must be driven through low resistances, otherwise exces­ sively long delays will occur. 5.3.1 Cascaded Inverters as Drivers Inverters intended to drive large capacitive loads must therefore present low pull-up and pull­ down resistance. Obviously, for MOS circuits, low resistance values for Zp,d, and Zp,u. imply low L : w ratios; in other words, channels must be made very wide to reduce resistance value and, in consequence,

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VLSI Design

Fig. 5.24 Driving large capacitive loads.

an inverter to meet this need occupies a large area. Moreover, because of the laige L : w ratio and since length L cannot be reduced below the minimuin feature size, the gate region area L X w becomes significant and a comparatively large capacitance is presented at the iqnjt, which in turn slows down the ratio of change of voltage which can take place at the ũqmt The remedy is to use N cascaded inverters, each one of which is larger than the'preceding stage by a width factor/ as shown in Fig. 5.24 (showing nMOS inverters, for example). Clearly, as the width factor increases, so the capacitive load presented at the inverter ÌDỊHit increases, and the area occupied increases also. Equally clearly, the rate at which the widtb increases (that is, the value off ) will influence the number N of stages which must be cascaded to drive a particular value of Cl. Thus, an optimiun solution must be sought as follows (this ừeatment is attributed to Mead and Conway). With large f, N decreases but delay per stage increases. For 4:1 nMOS inverters , ^ , where A V i„ indicates logic 0 to 1 delay per stage = f x for A V i„ 1 " " ^ \ , „ „ J-transitionandvi^„ indicates or = 4/TforVf^„ logic 1 to 0 tonsition of Vj„ Therefore, total delay per nMOS paữ = 5/x. A similar ưeatment yields delay per CMOS paữ = 7t. Now let y= —

=f ^

so that the choice of / and N are interdependent. We now need to determme the value of f, which will mmimize the overall delay for a given value of y and from the definition of y ln(y) = Arin(/) That is to (/)

Gate Level Design

a

15#

Thus, for N even Total delay = ^ 5 f x = 2.5NfT (nMOS) or = — 7 fx = 3.5Nf'i (CMOS) Thus, m all cases delay

ocN / t =

fx

It can be shown that total delay is minimized if / assumes the value e (base of natural loga’ ritbms); that is, each stage should be approximate 2.7* times wider than its predecessor. This applies to CMOS as well as nMOS inverters. Thus, assuming that/ = e, we have Number of stages N = Inij) and overall delay td N even: td = 2.5eNt (nMOS) or td = 3.5eNt

(CMOS)

iVodd: tđ = [ 2 . 5 ( A f - l ) + l ] e r ( n M O S ) td = [3.5 (AT-1) + 2 ]ex (CMOS) or td

= [2.5(iV -l) + 4]eT(nMOS)

td

= [3.5(iV -l) + 5]ex(CMOS)

fo r ^ V in

5.3J Super Buffers The asymmetry of the conventional inverter is clearly undesirable, and gives rise to significant delay problems when an inverter is used to drive more significant capacitive loads. A common approach used in nMOS technology to alleviate this effect is to make use of super buffers as in Figs. 5.25 and 5.26. An inverting type is shown in Fig. 5.25; considering a positive going logic transition Vị„ at the input, it will be seen that the inverter formed by Ti and Ĩ 2 is turned on and, thus, the gate of Ti is pulled down toward 0 volt with a small delay. Thus, Ts is cut off while Tị (the gate of which is also connected to Vị„) is turned on and the output is pulled down quickly.

1(S0

a

VLSI Design

'

out

Now consider the opposite ừansition: when Vin drops to 0 volt, then the gate of Ts is allowed to rise quickly to V d d - Thus, as T4 is also turned off by Vi„, Ta is made to conduct with V d d on its gate, that is, with twice the average voltage that would apply if the gate was 4 ed io the source as in the conventional nMOS inverter. Now, since Ij)s oc Vos then doubling the efiective V g s will increase the current and thus reduce the delay in charging any capacitance on the, output, so that more symmetrical transitions are achieved. The coưesponding non-inverting nMOS super buffer circuit is given at Fig. 5.26 ạạd, to.piự matters in perspective, the structures shown when realized in 5 fxm technqiogy are capable of driving loads of 2 pF with 5 nsec rise-time. Other nMOS arrangements such as ứiose based on the native transistor, and known as native super buffers, may be used, but such processes are not readily available to tìie designer and are mentioned here only briefly.

Gate Level Design

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161

5 J J BiCMOS Driven The availability of bipolar transistors in BiCMOS technology presents the possibility of using bipolar transistor drivers as the output stage of inverter and logic gate cừcuits. We akeady know that bipolar transistors have transconductance gm and cxurent/area I/A characteristics ứiat are greatly superior to those of MOS devices. This indicates high current drive capabilities for snum areas in silicon. Bipolar ưansistors have an exponential dependence of the output cuưeat I c on the input base to emitter voltage Vbe- This means that the device can be operated with much smaller input voltage swings than MOS teansistors and still switch relatively large currents. Thus, bipolar transistors have a much better witchmg performance, primarily as a result of the smaller input voltage swings. Only a small amount of charge must be moved during switching. One point to consider is the possible effect of temperatiưe T on the required input voltage Vị^.^ Although V be is logariứimically dependent on base width W b , doping level N a , electron mobility n„ and collector current Ic it is only linearly dependent on T . This means that there is no difficult in matching V be values across a cữcuit, spread over an area on chip, as the tem­ perature differences across a chip will not be sufficient to cause more than a few millivolts of difference m V be between any two bipolar transistors. The switching performance of a transistor drivmg a capacitive load may be visiialized ini­ tially from the simple model given in Fig. 5.27. Note: The time necessary to change the output voltage by an amount that is equal to the input change is given by A/ = Ci/g„ where gm = device transconductance. ‘'D O

R

in

'^SS Fig . 5 .2 7 Driving ability of bipolar transistor.

162

D

VLSI Design

It may be shown that the time A/ necessary to change the ou^ut voltage K ^ h y a a m ia m equal to the input voltage Vi„ is given by

A/ = ,, 8 m where gm is the transconductance of the bipolar transistor. Clearly, since the bipolar ừansistor has a relatively high transconduance, the value of Át is smaiỉí A more exacting appraisal of the bipolar fransistor delay reveals that it conqnises two components: i 1. Tin - an initial time necessary to charge the base emitter junction of the bipolar ( i ^ transistor. Typically, for the BiCMOS transistor-based driver, we are considering, is in the region of 2 ns. A similar consideration of a CMOS transistor driver in the saoiẹ BiCMOS technology would reveal a figure of Ins for Tin, this being the time taken to charge the input gate capacitance. As a matter of interest, a comparable figure for a GaAs driver is around 50 - 100 ps. 2. T i - the time taken to charge the output load capacitance Cl and it w ill be noted tíiat diis

time is less for the bipolar driver by a factor of h fe, where h fe is the bipolar transistor gain. Although the bipolar transistor has a higher value of Tin, Ti is smaller because of the fastei charging rate as discussed. The combined effect of Tin and Ti is represented in Fig. 5.28 and it will be seen that theri is a critical value of load capacitance CL(crit) below which the BiCMOS driver is slower than Ỉ comparable CMOS driver.

h'hfe

Fig. 5.28 Delay estimation.

Gate Level Design

o

1«3

• Delay o f BiCMOS inverter CMI bẹ descpbed by T=Ti„ + {V/I,)ụ/hfe)Ci. where Tin - time to charge up base/emitter junction hfe = transistor current gain (common emitter) • Delay for BiCMOS inverter is reduced by a factor of hfe compared with a CMOS inverter.

A further significant parameter contributing to delay is the collector resistance Rc of a bipolar ưansistor. Clearly a high value for Rc will mean a long propagation delay through the transis­ tor when charging a capacitive load. The reason for including the buried sub-collector region in the BiCMOS process is to keep Rc as low as possible. BiCMOS fabrication processes produce reasonably good bipolar transistors—^high gm, high p, high hfe and low Rc—^without compromising or over elaborating the basic CMOS process. The availability of bipolar transistors in logic gate and driver/buffer design provides a great deal of scope and freedom for the VLSI designer, o 5^ PROPAGATION DELAYS 5

Cascaded Pass Transistors

A degree of freedom offered by MOS technology is the use of pass teansistors as series or parallel switches in logic aưays. Quite frequently, therefore, logic signals must pass through a niunber of pass transistors in series. A chain of four such transistors is shown in Fig. 5.29(a) ypD-Kp

DD

(a)

Fj

R

Vj

R

Ku,

c

(b) Fig . 5.29 (a) and (b) propagation delays in pass transistor chain.

164

Cl

VLSI Design "

in which all gates have been shown connected tò Vpb tloj^c^lX’which would be die éhe fili a signal to be propagated to the output. The circuit thiis fonned may be modelled as ỀI Fig. 5.29(b) and it is then possible to evaluate tíie delay tiirough ttie networic. ivith respect to time is given by The response at node V2 with

r
M

(v,-r2)-{r2-n)

In the limit as the number of sections in such a network becomes laige, this eỉqiressioá reduces to

Where R = resistance per unit length c = capacitance per unit length X = distance along network from input The propagation time Xp for a signal to propagate a distance X is such that XpO^X^ The analysis can be simplified if all Rs and Cs are lumped together, then ^ to ta i = n r R s C to tai ~ n c S H C g

where r gives the relative resistance per section in terms of Rs and c gives the relative capaci­ tance per section in terms of OCg. Then, it may be shown that overall delay T
Gate Levéí Design

b

li$

/ft ^inv R 1.........

h —

R ....

K, 1- --------- L , .........._J- —

h

C -, —

c

c-^—

out

1........:.......:..1

c

Long interconnect wửe Fig. 5.30 Possible effects of delays in polysilicon wires.

inverter (to which the signal emerging from the long polysilicon line is connected) means that the input voltage spends a relatively long time in the vicinity of Vim, so thát small disturbances due to noise will switch the inverter state between ‘0’ and ‘1’ as shown at the output point. Thus it is essential that long polysilicon wữes be driven by suitable buffers to guard against the effects of noise and to stop up the rise-time of propagated signal edges. 5A 3 Wiring Capacitances We considered the area capacitances associated with the layers to substrate and from gate to channel. However, there are other significant sources of capacitance, which contribute to the overall wuing capacitance. Three such sources are discussed below.

5.4.3.1 Fringing Fields

Capacitance due to fringing field effects can be a major component of the overall capacitance of interconnect wkes. For fine line metallization, the value of fringing field capacitance (C#) can be of the same order as that of the area capacitance. Thus, should be taken into account if accurate prediction of performance is needed.

Cff

/ \n-

n

1 t I 1+ 4V V

t 4d d] /

16 «

o

VLSI Design

where I = wire length t = thickness of wire d = wire to subfract separation Then, total wire capacitance

Cw= C a re a +

C ff

5.43.2 Intertayer Capacitances Quite obviously the parallel plate effects are present between one layer and anoứier. For exam­ ple, some thought on the matter will confirm the fact that, for a given area, metal to polysili­ con capacitance must be higher than metal to substrate. The reason for not taking such effects into account for simple calculations is that the effects occxư only where layers cross or when one layer underlines another, and in consequence interlayer capacitance is highly dependent on layout. However, for regular structiưes it is readily calculated and contributes significantly to the accuracy of circuit modelling and delay calculation. 5.4,3.3 Peripheral Capacitance The source and drain n-diflusion regions (n-active regions for orbit process) from junctions with the p-substrate or p-well at well-defined and uniform depths; similarly for p-diỄbsion (p-active) regions in n-substrates or n-wells. For diffusion regions, each diode tìius formed has associated with it a peripheral (side-wall) capacitance in picofarads per unit length which, in total, can be considerably greater than the area capacitance of the diffusion region to substrate; the smaller the source or drain area, the greater becomes the relative value of the peripheral capacitance. However, for n- and p-regions formed by a diffiision process, the peripheral capacitance is important and becomes particularly so as we shrink the device dimensions. In order to calculate the total difiiision capacitance we must add the contributions of area and peripheral components C to ta l ~~ C a rea

C pgriph

5.5 CHOICE OF LAYERS Frequently, in designing an aưangement to meet given specifications, there are several pos­ sible ways in which the requirements may be met, including the choice between the layers on which to route certain data and control signals. However, there are certain common-sense constraints which should be considered: •

Vdd and Vss (GND) should be distributed on metal layers wherever possible and should not depart from metal except for ‘duck unders’, preferably on the diffusion layer whoi this is absolutely essential. A consideration of Rs values will reveal the reason for this.

Gate Level Design

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• Long lengths of polysiiicon should be used only after careiiil consideration because of the relatively high R s value of the polysilicon layer. Poiysilicon is ụnsúitablẹ for routing Vdd or Vss other than for very small distances. • With these restrictions in mind, it is generally ứie case that the resistances associated with transistors are much higher than any reasonable wuing resistance, so that there is no real danger of any problem due to voltage divider effects between wmng and transistor resistances. • Capacitive effects must also be carefully considered, particularly where fast signal lines are requứed and particularly in relation to signals on wừing having relatively high values of Rị . Diffusion (or active) areas have relatively high values of capacitance to subsfrate and are harder to drive in consequence. Charge sharing may also cause problems in cer­ tain cừcuits or architectures and must be carefully considered. Over small equipotentíal regions, the signal on a wừe can be treated as being identical at all pomts. Within each region the delay associated with signal propagation is small in comparison wiứi gate o delays and with signal delays in systems connected by the wữes. Thus, the wừes in a MOS system can be modelled as simple capacitors. This concept leads to the establishment of electrical rules (guidelines) for communication paths (wires) as given m Table 5.2. The factors set out in Tables 5.2 and 5.3 help to put matters in perspectives. Table 5.2 Electrical rules M axim um length of communication wire Layer

Lambda-based (15 ^m)

^m-based (2 ^m)

Metal Stlicide Polysilicon Difiiision (active)

Chip wide 2,000X 200A. 20X*

Chip wide NA ^ 400 Jim

100

M^m-based (1.2 ^m)

■

Chip wide NA 250 Jim 60

* Taking account o f peripheral and area capacitances. NA = not applicable.

Table 5.3 Choice of layers Layer

R

c

Comments

Metal

Low

Low

Good cuưent capability without large voltage drop ... use for power distribution and global signals.

Silicide

Low

Moderate

Modest RC product. Reasonably long wires are pos­ sible. Silicide is used in place o f polysilicon is some nMOS processes.

Polysilicon

High

Moderate

RC product is moderate; high IR drop

Diflusion (active)

Moderate

High

Moderate IR drop but high c. Hence, hard to drive.

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1. The sheet resistance is a measure of resistance of fhin films ứiat have a umform thickness. It is commonly used to characterize materials made by semi­ conductor doping, metal deposition, resistive paste printing, and glass coatmg. 2. The resistance of the MOS layers depends on the thickness and die mateiM of the layer. The resistance value of any square pattern is same as W =L. 3. Standard imit of capacitance is defined as gate to channel c^iacitance of a MOS fransistor having W = L = feature size that is standard. 4. Time constant T = (« channel) X 1 DCg) seconds.

1. I n _________ logic pMOS net is m dual topology with nMOS n et. 2. Pass transistor logic uses fransistors a s __________ ^to carry logic signals from one node to another. 3. ________ logic requires clock signal. 4. The two phases in dynamic CMOS are____________ and____________ . 5. The unit of sheet resistance is ____________ . 6. The resistance of MOS layers depend on th e___________ and___________ of the layer. 7. The delay unit T = ________________ . 8. The rise tữne and fall time are dependent o n _____________ . 9. For equal n and p geometeies the rise time is equal t o _______ times that of the fall time. 10. Capacitance due t o ______________ is major component of overall capaci­ tance of the interconnects. 11. Rs is independent of the area of the square____________ . 12. Circuit design must produce________________ and__________________ . Answers 1. 2. 3. 4. 5. 6.

CMOS Switches Dynamic CMOS Evaluation and precharge O/D Thickness, material

Gate Level Design

7.

I R s X

in C g

8.

1 /V d d , C l

9 . 2 .5

10. Fringing fields 11. Square 12. Improved performance and decreased silicon area

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:hapter

CHAPTER OBJECTIVES In this chapter, you will be introduced to • • • • • •

Programmable logic devices (PLD) Progranunable logic aưays (PLA) Programmable array logic (PAL) Complex programmable logic devices (CPLD) Standard cells Field programmable logic devices (FPGA)

6.1 PROGRAMMING LOGIC DEVICES Hardware realization of logic networks is generally very time-consuming and expensive. Also, once logic functions are realized in hardware, it is difficult to change them. In some cases, we need logic networks that are easily changeable. One such case is logic networks whose output fiuictions need to be changed frequently, such as conữol logic in microprocessors, or logic networks whose outputs need to be flexible, such as additional functions in wrist watches and calculators. Another case is logic networks that need to be debugged before finalizing. Pro­ grammable logic devices (PLDs) serve this purpose. Hence, a PLD can be defined as a programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike logic gate, which has a fixed function, a PLD has an undefined fiinction at the time of manufacture. Before the PLD can be used in a circuit it must be programmed (i.e., reconfigured).

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On these PLDs, all transistor circuits are laid out on IC chips prior to designers’ use. Wiis PLDs, designers can realize logic networks on an IC chip, by only deriving concise logÌỂ expressions such as minimal sums or minimal products, and ửten m aking connections amoi^ pre-laid logic gates on the chip. So, designers can realize their own logic netwotks quickfy and inexpensively using these pre-laid chips, because they need not design logic netwoiks, transistor circuits, and layout for each design problem. Thus, designers can skip substantid time of months for hardware design. CAD programs for deriving minimal sums or minimal products are well developed, so logic functions can be realized very easily and quickly as hardware, using ứiese CAD progrmns. The ease in changing logic functibtis without changing hardware is just like programming in software, so the hardware in this case is regarded as “programmable.” Programmable logic arrays (i.e., PLAs) and FPGAs are typical programmable logic devices.

«

yiĩHirniii ► What are the limitations for ROMs to use as a PLD? Before PLDs were invented, read-only memory (ROM) chips were used to create arbiừary combinational logic functions of a number of inputs. Consider a ROM wilh m inputs (the address lines) and n outputs (the data lines). When used as a memory, the ROM contains I" words of n bits each. Now imagine that the inputs are driven not by an w-bit address, but by m independent logic signals. Theoretically, there are I ’” possible Boolean functions of these m signals, but the structure of the ROM allows just 2” of these functions to be produced at the output pins. The ROM tiierefore becomes equivalent to n separate logic circuits, each of which generates a chosen function of the m inputs. This is clearly shown in the following example of 1-bit full adder cữcuit. The full adder has 2 data inputs and one cany mput (from the previous adder). The oulput’s are sum and carry (to the next level adder). Without going much into the design of adder, the min terms for which the sum output (5'i) is 1 is given by S i = F (l^,4,7) and the min terms for which for which c, is 1 is given by c, = F(3,5,6,7). For rest of the min terms the value of sum and carry is 0. A ROM consists of an AND array and an OR aưay connected in a matrix form. The dot indicates the connection at the intersec­ tion. As shown in the following figure. For each min term whose value is one a dot is placed near the intersection. For example. Si (sum) = 1 for min term 1, hence a dot is placed near the intersection of m \ and S i Imes. Similarly, c, is one for min term 3; hence a dot is placed near the intersection of rtĩỊ and Cj lines. A dot indicates a pro­ grammable point. The advantage of using a ROM in this way is that any conceivable function of the m inputs can be made to appear at any o f the n outputs, making this die most general-purpose combinatorial logic device available. Also, PROMs (progranunable ROMs), EPROMs (ulfraviolet-erasable PROMs) and EEPROMs (electrically erasable

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r> O T3 "Ì4

:>”>5 > >——o -

- - -<>

Fig. 6.1 ROM implementation of 1-bit full adder.

PROMs) are available that can be programmed using a standard PROM program­ mer without requking specialized hardware or software. However, there are several disadvantages: 1. They are usually much slower than dedicated logic circuits. 2. They consume more power. 3. In summary ROM can be thought as hard wired truth table. Only a small frac­ tion of their capacity is used in any one application, hence they often make an inefficient use of space. This is in contrast to our VLSI goals which is mini­ mum area of the silicon area should be used. 4. Since most ROMs do not have input or output registers, they cannot be used stand-alone for sequential logic. Then came programmable logic aưays. As with ROM the aưangement of gates is fixed in PLAs. They are called fixed architecture PLAs.

62 PROGRAMMABLE LOGIC ARRAYS (PLA) A programmable logic array (abbreviated as PLA), is a special type of ROM (which stands for Read-Only Memory), although its usage is completely different from that of ROMs. MOSFETS are aưanged in a matrix on a chip. A PLA consists of an AND array and an OR array. In order to store logic expressions, connections between the MOSFET gates and

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the vertical lines in the AND aưay and also connections between the MOSFET gates the horizontal lines in the OR array are set up by semiconductor manufacturers durii^ : rication according to customer specifications. This is known as programming PLD programmable logic devices. Since for these connections only one mask is requữed to gram the transistors, PLAs are inexpensive when tibe production volume is high enougỉi to make the custom preparation cost of the connection mask negligibly small. Because of low cost and design flexibility, PLAs are extensively used in VLSI chips, such as microproces­ sor chips for general computation and microcontroller chips for home appliances, toys, and watches.

6.2.1 Architecture of PLA The block diagram of a PLA is shown below in Fig. 6.2. Product terms

OR plane

Y

V

Fig. 6.2 Block diagram of P U . In the PLA approach instead of generating all the min terms a separate logic is implemented which generates only the required product terms. This saves lot of silicon area. Also die com­ mon product terms are identified and only one product term is generated for that particular term. This is shown in the following example. Consider the following logical functions: F \= xy + x z p 2 = ỹ + xz

F ỉ = xy + x z

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"ỆịỀ terms xz is conunon for Fi and F2 . Similarly, Jiy is conunon for Fi and F 3 . Hence, we need lilgic to generate only four logic terms, xy, x z , ỹ, and ỹz. We aừeady know that NAND gate md NOR gate are universal gates hence any logic can be implemented using them. Let us see how a NOR logic is implemented using a MOS fransistor near the progranunable point. Consider tíìe following example.

We programmed two points Avith nMOS transistors. When the input values or variables a and Ố be 1 and 0 respectively. Transistor near a will conduct (remember an nMOS conducts for logic 1) while transistor near b doesn’t conduct or remains off. Hence, the positive voltage V across the horizontal line is not allowed to appear near the output. Similarly, when both tran­ sistors are off, voltage V appears near the output and the value of F is 1. This configuration is similar to a NOR gate configuration. z

X

7 +v

ị

1

ORairray

\

—{w +v

xz

\w

ỹ

ị1

+v

...... ).....

\ 1....

9

ị 1w

^

ịp ị

'

—

AND array

y . , y Fig. 6.4 PLA structure.

. ■■ < 1—

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VLSI Design

Near each junction of horizontal and vertical wừes an nMOSFET is fabricated. But the gứt of the ừansistor is connected to the vertical line only near the points maiked in die above di»t gram. Rest of the transistors remain unused.

Example The implementation of full adder using PLA is shown below:

Fig. 6.5 PLA implementation of full adder.

As the logic is implemented using NOR gates, we apply de Morgan’s law to obtain the product terms. For example, abc can be written as (ã + Ố + c) according to de Morgan’s law. Hence, we programmed ã, b, c in the AND plane (not a, b, c). CMOS PLAs use pMOS enhancement devices to pull up row and column voltages. Figure 6.6 shows the example of a PLA’s layout. 6.2.2 Advantages and Disadvantages of PLAs PLAs, like ROMs which are more general, have the following advantages over random-logic gate networks, where random-logic gate networks are those that are compactly laid out on an IC chip: 1. There is no need for the time-consuming logic design of random-logic gate networks and even more time-consuming layout. 2. Design checking is easy, and design change is also easy.

Semiconductor Integrated Circuit Design

And-Plane

177

GND

JTo Xq Xị Xị *2 *2

Pull-up devices

o

/ 77

JO

Jl

Pull-up devices

Fig. 6.6 Layout of PLA (example).

3. Layout is far simpler than that for random-logic gate networks, and thus is far less timeconsuming. 4. When new IC fabrication technology is introduced, we can use previous design informa­ tion with ease but without change, making adoption of the new technology quick and easy. 5. Only the connection mask needs to be custom-made. Considering all these, PLA is a very inexpensive approach, greatly shortening design time. PLAs have the following disadvantages compared wiứi random-logic gate networks. Randomlogic gate networks have higher speed than PLAs or ROMs. 1. Random-logic gate networks occupy smaller chip areas than PLAs or ROMs, although the logic design and the layout of random-logic gate networks are far more tedious and time-consuming. 2. Also, with large production volumes, random-logic gate networks are cheaper than PLAs or ROMs. PLAs have the following advantage and disadvantage, compared with ROMs: 1. For storing the same functions or tasks, PLAs can be smaller than ROMs; generally, the size difference sharply increases as the number of input variables mcreases. 2. The small size advantage of PLAs diminishes as the number of terms in a disjunctive form increases. Thus, PLAs cannot store complex functions, i.e., functions whose dis­ junctive forms consist of many product terms.

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3. PLA’s offer enhanced flexibility in the design of con^>lex systems. They are eflS d a|||| implementing functions with larger number of product vaiiabies m die {Hodnct to fl For simple ftinctions, however, ứiey waste chip area and effect speed. 6 .2 .3 Applications o f PLAs

Considenng the above advantages and disadvantages, PLA^ have numerous unique tions. A microprocessor chip uses many PLAs because of easy of design change and chedL ] particular, PLAs are used in its control logic, which is complex and requữes many even during its design. Also, PLAs are used for code conversions, microprogram address ( versions, decision tables, bus priority resolvers, and memory overlay. When a new product is to be manufactured in small volume or test-maiketed, PLAs is tl choice. When ứie new product is well received in the market and does not need fiiilfaer changa^ PLAs can be replaced by random-logic gate networks for low cost for high volume productioii and high speed. Also, a full custom design approach is very tune-consuming, probably taking months or years, but if PLAs are used in the conưol logic, a number of different custom-desi^ J chips with high perfonnance can be made quickly by changing only one connection mask fiv the PLAs, although Aese chips cannot have drastically different perfonnance and íiinctìons. *1 6.3 PROGRAMMABLE ARRAY LOGIC (PAL) A programmable array logic (PAL) is a special type of a PLA where the OR array is not piogrammable. In other words, in a PAL, ứie AND aưay is programmable but the OR anay is fixed; whereas in a PLA, both aưays are progranunable. The advantage of PALs is the eiimination of fuses in the OR array and special electronic cừcuits to blow tíiese iiises. Since these special X

FixedORarray

------------- 1

------ V------

1J

1

1 —

) )

-0-

■

'

XI

\ P ‘ xy

-Ọ-

)

Ô-

AND array

yz )

V V. F,

Fig. 6.7 Example PAL structure.

Ft

Semiconductor Integrated Circuit Desig

Ĩ9

electronic cữcuits and programmable OR array occupy a very large area, the area is s y léđuced m PAL. Since single-output, two-level networks (i.e., m ^ y AND gates in th ĩl md one OR gate as the network output) are needed most often m design practice, m 5ou^ut two-level networks which are mutually unconnected are placed m some PAL Let us analyse the PAL structure for the example considered in topic 6.3. The points m the OR aưay are fixed. The structure has 6 inputs, 3 outputs and 6 product terms. At first sight, ứiis might be identical to the PLA shown in Fig. 6.8 but it differs from the earlier cừcuit in that only one of its two aưays is programmable. The AND aưay is equal to fliat in PLA and can be programmed to select the minterms requứed for a given function. However, the programmable OR aưay is replaced by a fixed pattern of connections to a set of OR gates. The user now constructs the required functions by using the AND aưay to select the combinations of min tenns that are fed into each OR gate. PALS derive theữ generic part name (for example, 6L3 or 22V10) from theữ input/output characteristics 16 says the number of inputs and L says active low and 3 says tíie number of outputs, o 6^ IMPLEMENTATION APPROACHES IN VLSI DESIGN The following Fig. 6.8 shows the various implementation approaches of VLSI design.

• •'

I__________

Arra>-bdhed

I

Fig. 6.8

6AA Custom or Full Custom Design In the custom design approach, each individual transistor is designed and laid out manually. The main advantage of this method is that the circuit is highly optimized for speed, area, or power. This design style is only suitable for very high performance circuitries, however, due to amount of manual work involved. 64.2 Semicustom Design In this approach, the majority of the chip is designed using a group of predefined cells called as standard cells and rest are designed manually. The cells are predesigned, pretested and pre­ compiled. It is up to the designer to import them into the design.

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6A 3 Gate Arrays A gate array is an IC chip on which gates are placed m matrix fonn whhout connectiom among the gates, as illustrated in Fig. 6.9(a). By connecting gates, we can realize logic works, as exemplified in Fig. 6.9(b). But actually, logic gates are not realized in a gate array. Connections among gates run in naưow strips of space between columns or rows of gates. These strips of space are called routing channels. ^8

L> L> E> E> r> D> E> L> n> L> E>

O

f i

O

t]

Fig. 6.9 (a) Before making connections (b) After connections made.

Instead of gates, cells, each of which consists of imconnected components, are arranged in matrix form, and each cell can realize one of a few different types of gates by connecting these components. Then, by connecting these gates as illustrated in Fig. 6.9(b), networks can be realized. The following example illustrates tìie same. Figure 6.9(c) shows a cell of a CMOS gate array, where a pair of pMOSFETs and a paừ of nMOSFETs are placed on the left and right, respectively, without connections between Polysilicon gate for pMOS Polysilicon gate for nMOS for source/drain p tab

n substrate

f n'*’ for Vpp

f for Vss

Fig. 6.9 (c) Connected CMOS inverter.

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them. The NAND gate can be realized by connecting the components shown in Fig. 6.9(c) by two metal layer. These two metal layers are formed by forming the first metal layer shown in Fig. 6.9(d), the insulation layer (not shown), and then the second metal layer shown in Fig. 6.9(e).

Fig. 6.9 (d) First metal connection layer.

] c

] c Fig. 6.9 (e) Second metal connection layer.

Fig . 6.9 (f) The connections consist of two metal layers shown in (b) and (c).

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6.5 COMPLEX PROGRAMMABLE L06IC DEVKiS (CPIAO Complex Progranunable Logic Devices (CPLDs) are exactly what they claim to be. EssoitiaUy ứỉey are designed to appear just like a laige number of PALs m a single chip, connected to each other tìưough a cross point switch. They use the same development tools and program­ mers, and are based on the same technologies, but they can handle much more conq>lex lo^c and more of it. Hence, a complex programmable logic device (CPLD) is a pFogranunable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The building block of a CPLD is the logical block, which contains logic inq>lementing ứie intended logic operations. Features in common with PALs: • Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't requữed, and ứie CPLD can function immediately on system start-up. • For many legacy CPLD devices, routing consừains most logic blocks to have input aod output signals connected to external pins, reducmg opportunities for internal state storage and deeply layered logic. This is usually not ã factor for larger CPLDs and newer CPLD product families. Features in common witii FPGAs: • Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowmg implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several nullion. • Some provisions for logic more flexible than sum-of-product expressions, mcluding com­ plicated feedback paths between macro cells, and specialized logic for implementing var­ ious commonly-used fimctions, such as integer antíunetic.

6.5.1 CPLD Architectures The diagram in Fig. 6.10 shows the mtemal architecture of a typical CPLD. While each manu­ facturer has a different variation, m general tíiey are all similar in ứiat ứiey consist of function blocks, input/output block, and an interconnect matiix. The devices are programmed xising pro­ grammable elements ứiat, depending on tíie technology of the manufacturer, can be EPROM cells, EEPROM cells, or Flash EPROM cells.

Function or Logic Blocks A typical fimction block is shown in Fig. 6.11. The AND plane still exists as shown by the crossmg wữes. The AND plane can accept inputs from tiie I/O blocks, other ftmction blocks, or feedback from ứie same function block. The terms and tíien ORed togedier using a fixed number of OR gates, and terms are selected via a laige multiplexer. The ou^uts of the max

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Fig. 6.10 Block diagram of CPLD.

Logic anay

Global Global Clear Clocks Parallel Logic Expanders (from other inacrocells)

from I/O pin Fact Input Programmable Select Register Register Bypass to I/O ConlTO

Block

36 signals from PIA

16 Expsmder Product Terms

Fig. 6.11 Functional block of CPLD.

can then be sent straight out of the block, or through a clocked flip-flop. This particular block includes additional logic such as a selectable exclusive OR and a master reset signal, in addi­ tion to being able to program the polarity at different stages. Usually, the function blocks are designed to be similar to existing PAL architectures, such as the 22V10, so that the designer can use familiar tools or even older designs without changing them.

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I/O Blocks Figure 6.11 shows a typical I/O block of a CPLD. The I/O block is used to drive signals to the pins of the CPLD device at the appropriate voltage levels with the appropriate current. Usually, a flip-flop is included. This is done on outputs so that clocked signals can be ou^ut directly to the pins without encountering significant delay. It is done for inputs so tìiat Ihere is not much delay on a signal before reaching a flip-flop which would increase ứie device hold time requirement. Also, some small amount of logic is included in the VO block simply to add some more resources to the device.

Interconnect (wires) The CPLD interconnect is a very large programmable switch matrix that allows signals from all parts of the device go to all other parts of the device. While no switch can connect all internal function blocks to all other function blocks, there is enough flexibility to allow many combinations of connections. Programmable Elements Different manufacturers use different technologies to implement the programmable elements of a CPLD. The common technologies are Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable PROM (EEPROM) and Flash EPROM. These technologies are similar to, or next generation versions of, the technologies that were used for the simplest programmable devices, PROMs. 6.5.2 Architecture Issues When considering a CPLD for use in a design, the following issues should be taken into account: 1. The programming technology EPROM, EEPROM, or Flash EPROM? This will determine the equipment needed to program the devices and whether they came be programmed only once or many times. 2. The function block capability a. How many function blocks are there in the device? b. How many product and sum terms can be used? c. What are the minimum and maximum delays through the logic? d. What additional logic resources are there such as XNORs, ALUs, etc.? e. What kind of register controls are available (e.g., clock enable, reset, preset, polarity control)? How many are local inputs to the function block and how many are global, chip wide inputs? f. What kind of clock drivers are in the device and what is the worst case skew of the clock signal on the chip? This will help determine the maximum frequency at which the device can run.

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3. Tke I/O capabiUty a. How msữiy I/O are indep^ident, used for any function, and how many are dedicated for clock mput, master reset, etc.? b. What is the output drive capability in terms of voltage levels and cuưent? c. What kind of logic is included in an I/O block that can be used to increase the function­ ality of the design? •

► Compare FPGA and CPLD

Architecture Density Speed Interconnect Power Consumption

CPLD

FPGA

PAL-like Low to medium 12 22V10s or more Fast, predictable Crossbar High

Gate Aưay-like Medium to high up to 1 million gates Application dependent Routing Medium

The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD. The characteris­ tic of non-volatility makes the CPLD the device of choice in modem digital designs to perform ‘boot loader’ functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. The main distinction between FPGA and CPLD device architectures is that FPGAs are internally based on look-up tables (LUTs) while CPLDs form the logic functions with sea-of-gates (e.g., sum of products).

6.6 STANDARD CELLS Standard cells are pre-defined logic elements used in the circuit. The design methodology that uses standard cells is known as cell based design methodology. Hence, Standard cells are the basic building blocks of cell-based IC design methodology. A standard-cell library is one of the foundations upon which the VLSI design approach is built. A standard cell is designed either to store information or perform a specific logic function (such as inverting, a logic AND, or a logic OR). The type of standard cell created to store data is referred to as a sequen­ tial cell. Flip-flops (FF) and latches are examples of sequential cells, which are indispensable elements of any ASIC library. The type of standard cell used to perform logic operations on the signals presented on its inputs is called combinational cell.

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Standard cells are built on transistors. They are OIK abstraction level higher tíian t r a a ^ tors. As shown in Fig. 6.12, a hardware block can be repsMcmted in four different abstrac­ tion levels during the chip implementation process. The k>west level is the teansistor oc device level. At this level, the entire block is described diceetly by the veiy basic buildii^ elements of toansistors, diodes, capacitors, and resistors. One level up is the cell level, in which designs are composed of standard cells. One more step up is the module level. At this level, designs are represented by modules such as adder, multiplier, ALU, and shifter. The highest level is the chip level. At the chip level, designs are partitioned mto sub­ systems, such as DSP, microconừoller, MPEG decoder, UART, USB, DMA, ADC, DAC, and PLL. The higher the abstraction level, the less implementation detail it contains. Lev­ els of standard cells are created for easy chip implementation, especially for large digital designs. Chip level

m i : - é í< í

i

Fig. 6.12 Level of abstraction.

During the chip construction process, a designer’s HDL code is transformed to a netlist using synthesis tools. The resultant netlist is composed of a certain number of standard cells, each one having its specific logic function. Overall, the intended system functions, ũũtially described by HDL code, are realized by the standard cells in ttiis netlist. These standard cells are placed within the chip’s floorplan by special place and route tool. The interconnections among these standard cells are also routed and wired by this tool. Figure 6.13 shows more details of the OR gate layout. The cell’s physical size is defined by cell height and cell width. The cell boundary is an attribute used by a place and route tool to place the cells during the placement stage. At the top and the bottom of tìie cell, there are usually wide strips of metal for the power supply and ground connections (DVDD and DVSS ports, as shown). The transistors inside the cell are fonned by the geometries on die base and metal layers as represented by the different shadings in the figure. The exact shapes and dimensions of those geometeies are drawn in the layout view. Typically, only tbe metal 1 layer

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Power DVDD bus

Port

Cell boundary Ground

Fig. 6.13 Block diagram of a standard cell.

is used inside the cell layout since higher level metals are reserved for signal routing. It is important to complete each standard cell’s layout with the least amount of silicon area pos­ sible. The reason is that the number of standard cells in a design could be on the order of mil­ lions, and a small amount of overuse of area at the cell level could add up to a large penalty in area at the chip level. In some cases, the same logic cell could have different layout versions: for example, same NAND gates small layout for low-performance but compact designs and large layout for high performance. Physically, the standard cells within an ASIC library have a fixed size m one dũnension (usually the height) so that they can be placed and aligned along the rows of the chip. Figure 6.14 shows two rows of standard cells within a certain portion of a chip layout. Each of those rows is filled with various standard cells that make up the actual chip. In some special cases, certain standard cells are designed twice (or even more) as high as regular cells. But those heights must be multiples of the regular cells so that they can be placed appro­ priately in the rows by the place and route tool. As seen in Fig. 6.14, when the cells are placed next to each other in a row, the DVDD and DVSS geometries about to form one long metal strip. Also, between two adjacent rows, the cells are flipped vertically so that DVDD andDFiS'5' metals are shared among the two rows. As a result, there is no wasted space existed between the rows. A large chip has a huge number of rows with power and ground busses ranning through each row. In this configuration, the height of the row (which is also the height of regular cells) is often refeưed to as row pitch and the smaller the pitch, the higher the gate

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One standard cell

Row

DVDD bus —** 4 . . ỳ

1.0

m ,r j9

Fig. 6.14 Two rows of standard cells in a chip layout.

density. As process technology continuously shrinks, so does the size of the standard cells. As a result, more and more logic gates can be packed into the same silicon area. The other name of cell-based design methodology is cell-based ASIC or CBIC in simple. «

>•

What are the advantages of cell-based design methodology? 1. Designers save time as they need not design the standard cells to be included in the design as they just import them from the ASIC or Design libraiy directly into the design. 2. As the standard cells are predesigned, pretested and precharecterized and kept in the STANDARDIZED library the risk of the design is reduced. 3. Each standard cell can be optimized individually and the changes can be reflected throughout the chip at a time. 4. During the design of cell library each and every transistor in every standard cell can be chosen to maximise the speed or minimize the area. The amount of risk is reduced to the designers m the cell-based design methodology.

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► What are the things the designer defines in the CBIC? The designer defines only two thmgs of the CBIC, they are 1. The placement of standard cells. 2. The mterconnects (wires) between the standard cells. ^ What is the sequence of operations in a standard cell based design? 1. A design is captured using the standard cells in a library via schematic or HDL. 2. The layout is then normally automatically and routed by the CAD software. 3. As the complete layout is being done optimization of the height of the routing channels may be completed by good placement.

6.6.1 ASIC Library or standard Cell Library An ASIC library or standard cell library is a group of standard cells glued together as a package. Typically, an ASIC library contains a sufficient number of combinational cells to perform any logic operation required by commonly used design styles with decent efficiency. It should also have many t3^es of sequential cells to meet any storage requirements. A typical modem ASIC library, could have more than several hundred diiferent standard cells. Those cells are categorized into groups by their functionality, such as INV, BUF, NAND, NOR, AND, OR, XOR, Boolean functions, flip-flop, and scan flip-flop. Within each functional group, there are a certain number of cells with different drivability. For example, in the inverter group of INV, there are usually a Ix drive cell INVl; a 3X drive cell INV3; and INV5, INV7, and INV9 cells. Different drivability cells within one group provide flexibility to the synthesis tool so that the optimal result can be achieved. An ASIC library is often tied to a particular process technology. Sometimes, several ASIC libraries can coexist within the same process technology, each targeting a specific purpose such as high speed, low power, or high density. Because standard cells are the basic building blocks of ASIC design methodology, appropri­ ate information must be provided to the CAD tools when they are used to create a silicon chip: the cell’s physical appearance, its logic functionality, timing behaviour, and electrical characteristics. For this reason, the cells in the ASIC library are characterized, modelled, and packed in certain data formats. A complete ASIC library should have following information (which is characterized as a view) available for each cell for the automatic design tools to use during various design phases: logic view, timing view, physical view, power view, and elec­ trical view. Together, these views provide a complete picture of each cell in the library. Vari­ ous automatic CAD tools used in IC design implementation utilize them to make their design decisions. The quality of an ASIC library has a great impact on the quality of the designs that use this library.

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6.7 FIELD-PROGRAMMABLE GATE ARRAY (FP6A) A field-programmable gate array (FPGA) is a semiconcfocW device that can be configured by the customer or designer after manufacturing—Whence the name “field-programmable*’. FPGAs are progranuned using a logic circuit diagram or a sòiưce code in a hardware desoiption language (HDL) to specify how the chip will work. FPGA can be used to mq>!emeiit ai^ logical ftinction that an application-specific integrated cừcuit (ASIC) could perform. Unlike an Application Specific Integrated Cừcuit (ASIC) which can perform a single specific function for the lifetime of the chip and it can be reprogrammed to perform a difieient function in a matter of microseconds. Before it is programmed an FPGA knows notiiing about how to com­ municate witii the devices suưounding it.

Fig. 6.15 XilinxFPGA.

6.7.1 FPGA Architecture Each FPGA vendor has its own FPGA architecture, but in general each type of an FPGA con­ sists of following resources: 1. Rectangular aưay of configurable logic blocks (CLBs) capable of implementing a variety of logic functions. 2. Progranunable interconnection resources or wữing tracks in simple wừes to route the signals between the CLBs. 3. Switches to connect the horizontal and vertical wữing tracks. 4. Configurable I/O blocks for signal conditionmg at the chip input and output pins. The available four types of FPGA architectures are: Symmetrical Array FPGA In this type, the structure is similar to a gate array with routing channels where each logic cell in a gate aưay is replaced with a logic block. Xiiinx follows ứiis type of architecture. It

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consists of a many square cluster of logic blocks suưoimded by inpuưoutput (I/O) blocks as shown in tíie Fig. 6.16. Each one of the CLB is able to handle a function with four Boolean variables. The interconnection resources or wking ừacks mentioned above would run along the entừe cluster, connectmg tíie logic blocks. Part of the programmable nature of the design allows users to turn on/tum off fransistor based switches to connect or disconnect specific logic cells. This essentially allows the user to control which of the cells is used in creating output from ứie cluster in particular applications. Since the configuration of the switches is stored in Static-RAM (which is volatile), a battery backup must be used. These chips contamed any­ where from 1000 to 1800 logic gates to be managed by the lookup table.

Fig. 6.16 Symmetrical array FGPA,

Sea of Gates This design is very similar to Xilinx’s original design, with the one major difference being the type of interconnections between components. In the Xilinx chips connections were made between the different logic gates, whereas the sea-of-gates technology uses overlays of the entire logic block. This allows for a much greater speed and usage of up to 40,000 logic gates, which is many, more than the maximum of 1800 used in Xilinx’s early chips. Row-Based Arrays Row-based architecture consists of alternating rows of logic blocks and programmable inter­ connect tracks. Input output blocks are located in the periphery of the rows. One row may be connected to adjacent rows via vertical interconnect. Logic modules can be implemented in various combinations. Combinatorial modules contain only combinational elements which

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' ‘ '

l - j - ^ r l-1 H I M .

ia iể ÌB Ìr iin ỉ í i i IP Denotes a connectioii lo be made or to be discfmnected

S S S S S S frS

liiiiiiih iv * IM ầm m Ềầm m ềầm m iẫm m

Denotes a logic blodc

ềmmiĩmmỉimmì umm PMt # Ù P « ỊỊM ỈIM ms

Connection line

ill

i l l

l i t

I I II I I i

Fig. 6.17 Sea of gates type FPGA.

•Denotes a connection to be made or to be disconnected 1.

■Connection Ime

i;

I 1:

' Logic block

Fig. 6.18 Row-based arrays.

Sequential modules contain both combinational elements along with flip-flops. These sequen­ tial modules can implement complex combinatorial-sequential functions. Routing toacks are divided into smaller segments connected by anti-fuse elements between them. Hierarchical PLDs The final category of chip is the “Hierarchical Programmable Logic Device,” which is used widely by the relatively late-coming company named Altera. Altera’s design is very difierent from previous designs. Here less than twenty logic blocks are used, which is sưikũigly less than the hundreds used by Xilinx and thousands used by Actel. Despite the relatively small number of logic blocks, this design uses a comparable number of logic gates (up to 20,000). It

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achieves this task by creating an aưay of logic gates within the blocks. No external memory units are requừed to store infonnation, unlike the usage of SRAM for anti-fuse technology. This allows tíie chips to be truly reprogranuned; however, the speed of reprogramming is nowhere near as fast as with SRAM technology.

Macrocell

Fig. 6.19 Hierarchical PLDs.

6.7.2 Configurable Logic Blocks (CLBs) Logic block of an FPGA can be configured in such a way that it can provide functionality as simple as that of teansistor or as complex as that of a microprocessor. It can used to imple­ ment different combinations of combinational and sequential logic functions. Logic blocks of an FPGA can be implemented by any of the following: 1. 2. 3. 4. 5.

Transistor pairs Combinational gates like basic NAND gates or XOR gates n-input Lookup tables Multiplexers Wide fan-in And-OR structure.

In the configurable logic block, look up table is used to implement any number of different functionality. The input lines go into the input and enable the lookup table. The output of the lookup table gives the result of the logic function that it implements. Lookup table is imple­ mented using SRAM cells and multiplexers. A lookup table with K inputs coưesponds to a

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2K X l-bit SRAM, and the user can realize any ^-mput togie fatw.rinn by jm>graiiiinmg logic function’s truth table dkectly into the memoty. of different possible functioiK for k input LUT is 2K. Advantage of such architecture ỈS that It suj^OTts ũnpiementatíoB of 80 many logic functions, however, the disadvantage is unusually large number of memoiy cells requữed to implement such a logic block in case number of inputs is laige. Figure 6.20 shows the block diagram of typical CLB.

Fig. 6.20 Lookup table - block diagram.

Consider the above Fig. 6.20, XC4000 CLB from XILINX. It contains two foiư-ũiput lookup tables fed by CLB inputs, and a third lookup table fed by the other two. This aưangement allows the CLB to implement a wide range of logic functions of up to nine inputs, two separate four input functions, or other possibilities. Each CLB also contains two flip-flops. Each CLB contains circuitry that allows it to efficiently perform arithmetic (that is, a circuit that implements a fast carry operation for adder-like circuits). Hence, we can think of lookup table as a small black box to implement its intended function taking many inputs giving a single output. Also, users can configure the lookup tables as read/write RAM cells.

Fig. 6.21 Logical block from Actel.

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^ Explain the concept of lookup table (LUT) with an example. As already discussed, a lookup table consists of SRAM cells to store the values and multiplexers to select the value. The size of the LUT is defined by its number of inputs. Each memory cell (SRAM) can store one value either 0 or 1. The stored value is given as output of the storage cell. Let us consider the following architecture of two input LUT.

Fig. 6.22 Circuit for two input LUT.

Typically, an Actel logic block consists of multiple number of multiplexers and logic gates. The LUT has 2 inputs ai and a2 and one output variable f. It is capable of imple­ menting any logic of two variables. Since it is two variable logic, there are four pos­ sible output values hence we need four storage RAM cells. Each cell corresponds to the output value in each row of the truth table. The input variables ai and a2 are used as select inputs of three multiplexers. Depending on the values of ai and a2 one of the contents of the four SRAM cells is given as output of the LUT. Suppose we need to implement a logic function/ = 0 1 0 2 + a^az. The truth table for the above equation is «1 0 0 1 1

Ơ2 0 1 0 1

F 1 0 0 1

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The values in the last column are stored in the 4 RAM eells of the LUT. The anangement of the multiplexers coưectly realizes the function f. When the value Q Ĩa\= 0 2 = ữ, LUT is driven by the top storage value 1. For a complex digital system (circuit) to be realized in an FPGA, each of its logic function in the circuit must be small enough to fit within the CLB. Remember the entire digital system is combination of various logic functions. Size of logic block plays an important role in deciding density of logic blocks and area uti­ lization in an FPGA. It also affects the performance of the FPGA. 1. A large size logic block implements more logic and hence requừes less number of logic blocks to implement functionality on the FPGA. On the other hand, a laige logic block will consume more space on the FPGA. So optimal size of logic block is one ứiat opti­ mally uses lesser number of logic blocks for functionality implementation while con­ suming as little space as possible. 2. Active logic area is generally less than total logic area due to presence of programmable connections. Total logic area is sum of active logic area and area consumed by program­ mable connections. 3. Routing area in an FPGA is typically more than the active area. It is 70 to 90 per cent of total area in an FPGA. 4. In case of lookup table based FPGA, a 4-input lookup table gives best results in terms of logic synthesised and area consumed.

6.7.3 FPGA Routing Techniques Routing architecture comprises of programmable switches and wừes. Routing provides connec­ tion between I/O blocks and logic blocks, and between one CLB and another CLB. The type of routing architecture decides area consumed by routing and density of logic blocks. Routing technique used in an FPGA largely decides the amount of area used by wừe segments and programmable switches as compared to area consumed by logic blocks. Connection between different CLBs is done through switch mattix. This is similar to the switching box in the telecommunications which is shown in the Fig. 6.23. A wire segment can be described as two end points of an interconnect with no program­ mable switch between them. A sequence of one or more wire segments in an FPGA can be termed as a track. There are four types of wire segments available: 1. General purpose segments, the ones that pass through switches in the switch block. 2. Direct interconnect: ones which connect logic block pins to four suưounding connecting blocks. 3. Long line: high fan out uniform delay connections. 4. Clock lines: clock signal provider which runs all over the chip.

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ILLLUJl

ỊỊỊỊỊỊỊI Cl

!

ìliỉỉiii

K4

Configurable logic block

F4 X

G3 C3 F3

XQ F2

C2 G2

Switch matrix

Switch matrix

rmrm

TTTTTTTT

Fig. 6.23 Typical connection of a configurable logic block to single line sections.

6.74 Switching Methodologies There are two types of programmable switching methodologies. 1. SRAM based switches 2. Antifuse technology

SRAMbased switches Consider the small section of an FPGA as shown in Fig. 6.34. The example of SRAM-controlled switches in Fig. 6.24 illustrates two applications of SRAM cells, one to control tìie gate nodes of pass-transistor switches and the other, the select lines of multiplexers that drive logic block inputs. The figure shows the connection of one logic block (represented by the AND gate in the upper left comer) to another through two pass-ừansistor switches and then a multiplexer, all controlled by SRAM cells. Whether an FPGA uses pass transistors, multiplexers, or both depends on the particular product. Depend­ ing on the value stored in the SRAM cell the wire segment can be connected or disconnected. If logic 0 is stored or programmed there is no further connection of wire segment else the wữe segment remains connected to the other side of the pass transistor. Recall pass transis­ tor is nothing but an NMOS transistor. Depending on the gate voltage the MOSFET conducts and transmits the signal to the other side. Hence, programming interconnects in FPGA can be

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|sram|

Logic block }

\^ S R A M |

IsramI

-

^

-

:

Fig. 6.24 SRAM controlled program switches.

understood as keeping appropriate Is and Os in SRAM cells so that the requữed connections are formed between the various CLBs on the FPGA.

Anti-fuse technology In an anti-fiise two conductors (in the below figure polysilicon and diflftision wires) are sepa­ rated by a dielectric material (ONO - oxide nitride oxide) which normally exhibits high imped­ ance. Hence, an anti-fuse is normally high resistance (>100 MÍ2). On application of appropriate programming voltages across the dielectric, it breaks down and cuưent flows and a permanent low resistance (200-500 £2) connection is made between the conductors. This can be under­

Anti-fuse polysilicon

ONO dielectric

anti-fuse diffusion 1__________ 2

X

Fig. 6.25 Anti-fuse technology.

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stood as a permanent connection between two wừe segments. This is contrast to SRAM switching technology which can be re-programmed any tune. The process is iưeversible. •

^ Compare SRAM and Anti-fuse Programming. There are two competing methods of programming FPGAs. The first, SRAM pro­ gramming, involves small Static RAM bits for each programming element. Writing ứie bit with a zero turns off a switch, while writing with a one turns on a switch. The otìier metíiod involves anti-fuses which consist of microscopic structures which, unlike a regular fiise, normally make no connection. A certam amount of current diưing programming of the device causes the two sides of the anti-fuse to connect. The advantages of SRAM based FPGAs is that they use a standard fabrication process that chip fabrication plants are familiar with and are always optimizing for better per­ formance. Since the SRAMs are reprogrammable, the FPGAs can be reprogrammed any number of times, even while they are in the system, just like writing to a nor­ mal SRAM. The disadvantages are that they are volatile, which means a power glitch could potentially change it. Also, SRAM based devices have large routing delays. The advantages of anti-fuse based FPGAs are that they are non-volatile and the delays due to routing are very small, so they tend to be faster. The disadvantages are that they requữe a complex fabrication process, they requữe an external programmer to program them, and once they are programmed, they cannot be changed. ^ What are the aspects to be considered in selecting a particular switching technology? 1. Values or R and c of the switch. 2. Reprogram ability: important if the user wants to easily incorporate design changes or change the function of the logic. 3. Volatility: what happens when the power is lost? How easily is the function­ ality restored? 4. Area of the switch: more switches make routing easier and fewer switches. 6.7.5 Configurable I/O Blocks A configurable I/O block, shown in Fig. 6.26 is used to bring signals onto the chip and send them back off again. It consists of an input buffer and an output buffer with three state and open collector output controls. Typically, there are pull up resistors on the outputs and some­ times pull down resistors. The polarity of the output can usually be programmed for active high or active low output and often the slew rate of the output can be programmed for fast or slow rise and fall times. In addition, there is often a flip-flop on outputs so that clocked signals can be output dừectly to the pins without encountering significant delay. It is done

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Local Bus

Open Slew

Bus

Fig. 6.26 FPGA configurable I/O block.

for inputs so that there is not much delay on a signal before reaching a flip-flop which would increase the device hold time requirement. 6.7.6 Features of FPGAs If we go for mask-programmable gate aưays, we need to wait several weeks and pay twenty thousand to hundreds of thousands of dollars to the semiconductor manufacturers. But witìi FPGAs, we can program FPGAs in minutes by ourselves and need to pay less. But a FPGA can pack only about one-tenth the number of logic gates in a mask-programmable gate anay because devices for user programmability, such as SRAMs, non-volatile memory, and anti­ fuses, take up large areas. Mask programmable gate aưays are faster by two orders of magnitude and far cheaper for large production volume. Thus, for debugging or verifying logic design that needs to be done quickly, FPGAs are used, and then mask-programmable gate arrays are used for large volume production after completing debugging or verification. As seen already, FPGAs are classified into two types, depending on the types of devices used for programmability: rewritable FPGAs and non-rewritable FPGAs. Then, they are accordingly used for completely different piuposes. Rewritable FPGAs, such as Xilinx’s based on SRAMs and Altera’s based on non-volatile memory, can be repeatedly rewritten in minutes. Non-rewritable FPGAs cannot be changed once programmed, but still have the advantages of realizing inexpensive logic chips with faster speed. The area size of different devices for programmability also gives different advantages and disadvantages. A non-volatile memoiy

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cell is roughly four to five tinifts larger ứian anti-fiise; a memory cell of SRAM is two times laiger than a non-volatile memoiy cell. Antí-íiises are much smaller. So, because of smaller parasitic capacitance, FPGAs based on anti-fuses tend to be faster than those based on non-volatile memory or SRAMs. 6.7.7 Applications 1. Applications of FPGAs include digital signal processing, software-defined radio, aero­ space and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, biomformatics, computer hardware emulation and a growing range of other areas. 2. FPGAs originally began as competitors to CPLDS. As theừ size, capabilities, and speed increased, ửiey began to take over larger and larger functions to the state where some are now marketed as full systems on chips (SoC). Particularly with the inteoduction of dedicated multipiiers into FPGA architectures in the late 1990s, applications which had traditionally been ứie sole reserve of DSPs, began to incor|)orate FPGAs mstead. 3. FPGAs especially find applications in any area or algorithm that can make use of the massive parallelism offered by theừ architecture. One such area is code breaking of ciyptographic algorithms. 4. FPGAs are increasingly used in conventional high performance computing applications where computational kernels such as FFT or convolution are performed on the FPGA instead of a microprocessor. 5. The inherent parallelism of the logic resources on an FPGA allows for considerable compute throughput even at a low MHz clock rates. The flexibility of the FPGA allows for even higher performance by frading off precision and range in the nximber format for an increased number of parallel arilỉunetic units. This has driven a new type of processing called reconfigurable computing, where time intensive tasks are offloaded from software to FPGAs. 6. The adoption of FPGAs m high performance computing is cuưently limited by the com­ plexity of FPGA design compared to conventional software and the extremely long turn­ around times of cuưent design tools, where 4-8 hours wait is necessary after even minor changes to the soiưce code. 7. Traditionally, FPGAs have been reseiyed for specific vertical applications where the vol­ ume of production is small. For these low-volume applications, the premium that compa­ nies pay in hardware costs per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC for a low-volume application. Today, new cost and performance dynamics have broadened the range of viable applications. 64t DESIGN ISSUES Top-Down Design Top-down design is the design method whereby high-level ftmctions are defined first, and the lower-level implementation details are filled in later. A schematic can be viewed as a

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Fig. 6.27 Top-down design.

hierarchical tree as shown in Fig. 6.27. The top level block represents tìie entire chip. Each lower level block represents major functions of the chip. Intermediate level blocks may con­ tain smaller functionality blocks combined with gate-level logic. The bottom level contains only gates and macrofimctions which are vendor-supplied high level functions. Fortunately, schematic capture software and hardware description languages used for chip design easily allows use of the top-down design methodology. Also important is the fact that simulation is much simplified using this design methodology. Simulation is an extremely important consideration in chip design since a chip c^mot be bluewired after production. For this reason, simulation must be done extensively before ứie chip is sent for fabrication. A top-down design approach allows each module to be simulated mdependently from the rest of the design. This is important for complex designs where an entữe design can take weeks to simulate and days to debug.

1. PLD is an electronic component used to build reconfigurable digital cữcuits. Unlike logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a cừcuit it must be programmed (i.e., reconfigured). 2. A programmable logic array (abbreviated as PLA), is a special type of ROM (which stands for Read-Only Memory). A PLA consists of an AND array and an OR aưay which are programmable. 3. A progranunable aưay logic (PAL) is a special type of a PLA where ứie OR aưay is not programmable. 4. In the custom design approach, each individual transistor is designed and laid out manually.

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5. In semicustom design approach the majority of the chip is designed using a group of predefined cells called as standard cells and rest are designed manually. 6. A gate aưay is aa IC chip on which gates are placed in matrix form with­ out connections among the gates. By connecting gates, we can realize logic networks. 7. Standard cells are predefined logic elements used in the cữcuit. 8. An ASIC library or standard cell library is a group of standard cells glued . together as a package. 9. FPGAs are programmed using a logic cừcuit diagram or a source code Ũ1 a hardware description language (HDL) to specify how the chip will work.

1. 2. 3. 4. 5. 6. 7. 8. 9.

Predesigned logic cells are known as Standard cell areas in CBIC are Standard cells can be placed________ ■ on the silicon chip. Power buses are also known a s _____________ . Connecting__________ ^to form a ____________ ^results in faster and denser layout using standard cells. The small squares on the edge of the cell are raised for____________ . Device sizes in a gate aưay are________ ^fixed. The advantage of changing transistor size in standard cell is_________ . ______________ are programmable in FPGAs.

Answers 1. 2. 3. 4. 5. 6. 7. 8. 9.

Standard cells Flexible blocks Anywhere Rails Datapath cells, datapath Connecting to pins Fixed Optimized speed and performance Interconnections

Subsystem Design

CHAPTER OBJECTIVES In this chapter, you will be introduced to • • • • • •

Datapaths in digital processor architectures The adder The multiplier The shifter Memory elements Architectural issues

7.1 DATAPATHS IN DIGITAL PROCESSOR ARCHITECTURES A digital processor consists of the datapath, memory, control, and inpuưoutput blocks. The datapath is ữie core of the processor and this is where all computations are performed. The other blocks in the processor are support units that either store the results produced by the datap­ ath or help to determine what will happen in the next cycle. A typical datapath consists of an interconnection of basic combinational functions, such as arithmetic operators (additions, multiplication, comparison, and shift) or logic (AND, OR, and XOR). The design of the arith­ metic operators is the topic of this chapter. The intended application sets constraints on the datapath design. In some cases, such as in personal computers, processing speed is everything. In most other applications, there is a m ayim iim energy available for computation while maintaining the desired throughput. Datapaths often are arranged in a bit-sliced organization, as shown in Fig. 7.1. Instead of operating on single-bit digital signals, the data in a processor are arranged in a word-based

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Fig. 7.1 Bit sliced datapath organization. fashion. Typical microprocessor datapath are 32 or 64 bits, while the dedicated signals pro­ cessing datapath, such as tíiose in DSL modems, magnetic disk drives, or compact-disc play­ ers are of arbitrary with, typically 5 to 24 bits. For instance, a 32-bit processor operates on data words that are 32 bites wide. This is reflected in the organization of tiie datq)atli. Sinủé the same operation frequently has to be performed on each bit of the data word, the datapatii consist of 32 bits slices, each operating on a single bit—^hence the term bit sliced. Bit slices are either identical or resemble a similar structure for all bits. The datapatíi designer can concenữate on the design of a single slice that is repeated 32 times. 7.2 THE ADDER Addition is the most commonly used arithmetic operation. It is often a speed-limiting element as well. Therefore, careful optimization of the adder is of utmost ũnportance. This optimiza­ tion can proceed either at the logic or cừcuit level. Typical logic-level optimization fay to rear range the Boolean equations so that a faster or smaller cừcuit is obtained. An example of such a logic optimization is the cany lookahead adder discussed later in tíie chapter. Cừcuit opti­ mization, on the other hand, manipulate fransistor sizes and cữcuit topology to optimize the speed. Before considering boứi optimization processes, we provide a short summary of basic definitions of an adder cừcuit. The Binary Adder: Definitions The Table 7.1 shows the trutìi table of a binary full adder. A and B are inputs, c, is the cany inputs, s is the sum output, and Co is tìie cany output. The Boolean expressions for s and Co are given in equation 7.1. S = A ® B ® Q

= A B Q + A B Q + A B Q + A B Q

(7.1) C o = A B + B C i+ A Q

Subsystem Design

a

207

Table 7.1 Truth Table of full adder A

B

Cl

s

Ci

Carry status

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1 1 1

0 1 1

1 0 1

0 0

1 1 1

delete delete propagate propagate propagate propagate generate generate

1

It often useful from an implementation perspective to define s and Co as functions of some intermediate signal G (generate), D (delete), And p (propagate). G = I (D = I) ensures that a cany bit will be generated (deleted) at Co mdependent of Ci, while p = 1 guarantees tibat an incoming cany will propagate to Co. Expressions for these signals can be derived from inspection of the truth table G = AB D = AB P =A® B

(7.2)

We can rewrite 5 and Co as functions of p and G (or D): C,(G,P) = G + PQ S ( G ,P ) = P ® C i

Notice that G and p are only functions of A and B and are not dependent upon C/. In a similar way, we can also derive expressions for s (G, P) and Co (G, P). 7.2.1 Four Bit Ripple Carry Adder An N-bit adder can be constructed by cascading N full adder (FA) circuits in series, connect­ ing Co,k-i to c,jt for A: = 1 to iV-1, and the first carry in Ci o to 0 (Fig. 7.2). This aưangeraent is known as ripple carry adder since the carry bit ripples from one stage to another. The delay tìirough the circuit depends upon the number of stages that must be traversed and is a func­ tion of the applied input signals. For some inputs no rippling occurs at all, while for others, the carry has to ripple all the way from the least significant bit (LSB) to the most significant bit (MSB). The propagation delay of such structure is defined as the worst case delay over all possible input patterns.

208

o

VLSI Design

"KO

u ■t?A-

Qo

______ ( = c , . )

-'0

^2 Fig. 7.2 Four bit ripple carry adder.

In the case of ripple cany adder the worst case delay happens when a cany generated at the least significant bit position propagates all the way to the most significant position. This cany is finally consumed in the last stage to produce the sum. The delay is then proportional to the number of bits in the input words N and is approximated by I ladder —

^^carry

ti

(7.4)

where tcan y and tsum equal the propagation delays from C/ to C o and s respectively. Two important conclusions can be drawn from the above equation. • The propagation delay of the ripple carry adder is linearly proportional to iV. This prop­ erty becomes very important when designing adders for wide datapaths. «

>■ Derive the values of A gi and (JT= 0 to A^-1) so that the worst case delay is obtained for the npple carry adder. The worst case condition requữes that a carry be generated at ứie LSB position. Since the input carry of the first full adder C/, 0 is always 0, this both Aữ and 5o must equal 1. All other stages must be in the propagation mode. Hence, either Ai or Bi must be high. Finally, we would like to physically measure the delay of the transition on the MSB sum bit. Assuming an initial value of 0 for Sn-I we must arrange a 0->l ữansition. This is achieved by settmg both An-\ and Bn-\ to 0 (or 1), which yields a high sum bit given the incoming carry of 1. For example, the following values of A, and B trigger the worst case delay for an 8-bit addition.

yi = 00000001; 5 = 01111111

To set up the worst case delay all the inputs can be kept constant wiứi Ao imdergoing a 0->l transistion. The leftmost bit represents the MSB m this binary repre­ sentation. Observe that tìiis is only one of the many worst case patterns. This case exercises the 0—>1 delay of the final sum.

Subsystem Design

•

o

209

Whoi d esigning the fiill adder ceU for the fast ripple cany adder, it is far important to optimize tcany than tsum since the latta' one has minor influence on the total value of fodder.

Before starting an m dq>th discussion on cừcuit design of fixll adder cells, the followmg additional logic property of die full adder is worth mentiomng. Inverting all inputs to a full adder results in inverted values for all outputs. This property is known as inverting property. It is expressed in the paừ of equations S(A,B,C ) = SiA,B,C i) Co(A + B + C ) = C o ( A ,B ,Q )

(7.5)

B

C ,—

Fig. 7.3 Inverting property of the full adder. The circles in the schematic represents inverters.

and will be exừemely useful when optimizing the speed of the ripple carry adder. It states tìiat the cừcuits shown in Fig. 7.3 are identical.

T22 Static Adder Circuit: Circuit Design Considerations One way to implement the full-adder cữcuit is to take the logic equations of equation 7.1 and translate them directly mto complementary CMOS cừcuitry. Some logic manipulations can help to reduce the transistor coxmt. For instance, it is advantageous to share some logic between the Sum-and carry-generation subcircuits, as long as this does not slow down the carry generation, which is the most critical part, as stated previously. The following is an example of such a reorganized equation set: C o= A B + B Q + A C i S = A B C i + C o { A + B -\-Ci)

(7.6)

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VLSI Design

The equivalence with the original equations is The corre^XHiding addei design, using complementary static'CMOS, is shown in Fig. l A and requứes 28 bansistora. fa addition to consuming a large area, this cừcuit is slow: • Tall pMOS ừansistor stacks are present in both cuiy-and sum-geneiation circuits. • The intrinsic load capacitance of the Co signal is Ivge and consists of two diffiisicm and six gate capacitances, plus the wiring capacitance. • The signal propagates through two inverting stages m the caixy-genCTatÌOT circuit. As mentioned earlier, minimizing the cany-path delay is the prime goal of tìie designer ọf high-speed adder cừcuits. Given the small load (fan-out) at the output of the cany chaiii, having two logic stages is too high a number, and leads to extra delay. • The sum generation requkes one extra logic stage, but that is not ứiat inqxHtant, since a âctor appears only once m the propagation delay of the ripple-cany adder of equation 7.4. Although slow, the cữcuit includes some smart design tricks. Notice that the first gate of the carry-generation circuit is designed with the c, signal on the smaller pMOS stack, lower­ ing its logical effort to 2. Also, the nMOS and pMOS ưansistors connected to C,- are placed as close as possible to the output of the gate. This is a direct application of a cừcuit-optiinization technique—transistors on the critical path should be placed as close as possible to úie output of the gate. For instance, in stage k of the adder, signals A/c and Bk are available and

DO ''DD

C,-c| B

A-

T3------ p A -< ]

■n \^ A

B-

c.

''D P

J a

hQ

t: —A

A —

-A

t r -

L_r

B —

B—

I

— A

— B

H Fig. 7.4 Complementary static CMOS implementation of full adder.

SubsystemDesign a Even cell Ả,

c,0

By

211

Odd cell As

'O .Ì

Fig. 7.5 Inverter elimination in carry path. FA stands for a full adder without the inverter in the carry path.

stable long before Ci,k (= Co, A-i) arrives after rippling through the previous stages. In this way, the capacitances of the internal nodes m the transistor chain are precharged or discharged in advance. On aưival of Qfc only the capacitance of node X has to be (dis)charged. Putting the C/Jfc fransistors closer to V dd and GND would require not only the (dis)charging of the capaci­ tance of node X, but also of the internal capacitances. The speed of this circuit can now be improved gradually by using some of the adder prop­ erties discussed in the previous section. First, the number of inverting stages in the carry path can be reduced by exploiting the inverting property-investing all the inputs of a full-adder cell also mverts all the outputs. This rule allows us to eliminate an inverter in a cany chain, as demonstrated in Fig. 7.5. 1 1 .Ì Transmission-Gate-Based Adder

A full adder can be designed to use multiplexers and XORs. While this is impractical in a complementary CMOS implementation, it becomes attractive when the multiplexers and XORs are implemented as transmission gates. A ftill-adder implementation based on this approach is shown m Fig. 7.6 and uses 24 transistors. It is based on the propagate-generate model. Intro­ duced in equation 7.3, the propagate signal, which is the XOR of inputs A and B, is used to select the true or complementary value of the input carry as the new sum output. Based on the propagate signal, the output carry is either set to the input cany, or either one of inputs A or B. One of interesting features of such an adder is that it has similar delay for both sum and carry outputs.

Ĩ2 A Allanchester Carry-Chain Adder The caưy-propagation circuitry in Fig. 7.6 can be simplified by adding generate and delete signals, as shown in Fig. 7.7(a). The propagate path is unchanged, and it passes Cj to the Co

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VLSI Design

Sum Generation

B .

c

Carry Generation

Setup Fig. 7.6 Transmission-gate-based full adder with sum and carry delays of same value.

output if the propagate signal { Ạ i ® B , ) is true. If the propa^te condition is not satisfied, the output is either pulled low by the D ị signal or pulled by G j . The dynamic implementation [Fig. 7.7(b)] makes even further simplification possible. Since the transitions in a dynamic cữcuit are monotonic, the transmission gates can be replaced by nMOS-only pass ựansistors. Precharging the output eliminates the need for the kill signal (for the case in which the cany chain propagates the complementary values of the cany signals).

^DD

c, G.

T a-H P:

Fig, 7.7 Manchester carry gates (a) static using propagate, generate and kill (b) dynamic implementation using only propagate and generate signals.

Subsystem Design

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213

Fig. 7.8 Manchester carry adder in dynamic logic. (Four bit section)

^DD ^,-.1

Gị+1

c,

+1

GND Fig. 7.9 Stick diagram of two bits of a Manchester carry chain.

A Manchester cany-chain adder uses a cascade of pass tt^nsistors to implement tìie carry chain. An example, based on ứie dynamic cừcuit version introduced Ũ1 Fig. 7.7, is shown in Fig. 7.8. Dur­ ing the precharge phase (C> = 0) all mtermediate nodes of the pass-transistor carry chain are prechdiiged to Vdd - During evaluation ứie A k node is discharged when there is an incoming cany and the propagate signal Pk is high, or when tiie generate signal for stage k{Gkị is high. Figure 7.9 shows an example layout of the Manchester Cany chain in stick-diagram for­ mat. The datapath layout consists of three rows of cells organized in bit-sliced style: The top row of cells computes the propagate and generate signals, the middle row propagates the carry from left to right, and the bottom row generates the final sums.

214

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VLSI Design

The worst case delay of the carry chain of ứie adder in Fig. 7.8 is modelled by die linear­ ized RC network. The propagation delay of such a network equals tp = 0 .6 9 ^ Q i=i

p U=1 ;

when Ci = c and Rj = R. Increasing the transistor width reduces this time constant, but it also loads the gates in the previous stage. Therefore, the ừansistor size is limited by the input loading capacitaoce. Unfortunately, the distributed iỉC-nature of the carry chain result in a propagation delay that is quadratic in the number of bits N. To avoid this, it is necessary to insert signal-buffering inverts. The optimum number of stages per buffer depends on the equivalent resistance of the inverter and the resistance and capacitance of the pass transistors. In our technology, and in most other practical cases, this number is between 3 and 4. Adding the inverter makes the overall propagation delay a linear function of N, as is the case with ripple-carry adders. The ripple cany adder is only practical for the implementation of additions with a relatively small word length. Most desktop computers use word lengứis of 32 bits, while servers reqmre 64; very fast computers, such as mainframes, supercomputers, or multimedia processor (e.g., the Sony Play Station2) require word lengths of up to 128 bits. The linear dependence of the adder speed on the number of bits makes the usage of ripple adders rather impractical. Logic optimi­ zations are therefore necessary, resulting in adders with tp < 0(N). We briefly discuss a number of those in the sections that follow. We concentrate on the circuit design implications, since most of the presented structures are well known from the traditional logic design literature. 7.2.5 Carry Bypass Adder or Carry Sidp Adder Consider the four-bit adder block of Fig. 7.10(a). Suppose that the values of Ale and Bk (k = 0...3) are such that all propagate signals Pk (k = 0...3) are high. An mcoming carry Qo = 1 propagates under those conditions through the complete adder chain and causes an outgoing carry Co i = 1. In other words, ^f(PoPjP2 P 3 j 1) then = else either DELETE or GENERATE occuưed.

(7.8)

This information can be used to speed up the operation of the adder, as shown in Fig. 7.10(b) when BP = PqP xP iP ì = 1 the incoming carry is forwarded immediately to the next block through the bypass transistor Ả/i-hence the name Carry-bypass adder or carry-skip adder. If this is not the case, the carry is obtained by way of the normal route. Carry Bypass in Manchester Carry-Chain Adder Figure 7.11 shows the possible carry propagation paths when the full adder circuit is implemented in Manchester-caưy style. This picture demonstrates how the bypass speeds

Subsystem Design

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(a) Carry propagation

(b) Adding a bypass Fig. 7.1 D Carry-bypass structure— basic concept.

(BP)

q „-

(BP) Fig. 7.11 Manchester carry chain implementation of bypass adder.

up the addition: The carry propagates either through the bypass path, or a carry is gener­ ated somewhere in the chain. In both cases, the delay is smaller than the normal ripple configuration. The area overhead incuưed by adding the bypass path is small and typically ranges between 10 and 20%. However, adding the bypass path breaks the regular bit-slice structure. Let us now compute the delay of an TV-bit adder. At first, we assume that the total adder is divided in {N/M) equal-length bypass stages, each of which contains Mbits. An approximating

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VLSI Design

Bit 0-3

p

Bit4-7 S^up

Cany/ *■

%»»

B ừ8-il Selíụ

It

Cany propag^ion

Cany propagation

Sum

Sum

_BỊ

s

'i

Sum A/bits

Fig. 7.12 (N= 16) carry-bypass adder composition. The worst case path is shown in gỊữíexpression for the total propagation time can be derived from Fig. 7.12 and is given in eqixation 7.9, namely. fp — U ettq>

+M

tc a n y

+

(7.9)

with the composmg parameters defined as follows: • (setup' the fixed overhead tune to create the generate and propagate signal • icarry'- The propagation delay through a single bit. The worst case cany-propagatioD del^ through a single of Mbits is approxũnately Af times larger. • fiyjmss- the propagation delay through the bypass multiplexer of a single stage. • fsum- the time to generate the sum of the final stage. The critical path is shaded in gray on the block diagram of Fig. 7.14. From equation 7.9, it follows that tp is still Imear in the number of bits N since in the worst case, the carry is gener­ ated at the first bit position, ripple through tìie first block, skips around (N/M-2) bypass stages, and is consumed at the last bit position without generating an output carry. The optimai num­ ber of bits per skip block is determined by technological parameters such as ứie e ? ^ delay of the bypass selectmg multiplexer, the buflfering requữements m the cany chain, and the ratio of the delay through the ripple and the bypass paths. Although still linear, tbe slope of tíie delay function increases in a more gradual fashion than for the ripple-cany adder, as pictured in Fig. 7.13. This difference is substantial fot laiger adders. Notice that the ripple adder is actually faster for small values ofN, for which the over­ head of the extra bypass multiplexer makes the bypass structures not interesting. The cross­ over point depends upon technology considerations and is normally situated between four and eight bits.

Subsystem Design

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217

Fig. 7.13 Propagation delay of ripple carry versus carry by pass adder.

7J.6 The Linear Carry-Select Adder In ripple-carry adder, every íiỉll-adder cell has to wait for the incoming cany before an outgoing caưy can be generated. One way to get around this linear dependency is to anticipate both possible values of the cany mput and evaluate the result for both possibilities in advance. Once ứie real value of the incoming carry is known, the coưect result is easily selected with a simple multiplexer stage. An implementation of this idea, appropriately called the carry-select adder, is demonstrated m Fig. 7.14. Consider the block of adders, which is adding bits k i o k + h. Instead of waiting on the arrival of the output carry of bit ^-1, both the 0 and 1 possibilities are analyzed. From a cữcuit point of view, this means that two cany paths are implemented. When Co,k-\ finally settles, either the result of the 0 and 1 path is selected by the multiplexer, which cm be performed with minimal delay. As is evident from Fig. 11.16, tìie hardware overhead of the cany-select adder is restricted to an additional cany path and a multiplexer, and equals about 30% with respect to a ripple cany structure. A fill! cany-select adder is now constructed by chaining a number of equal-length adder stages, as in tiie canry-bypass approach (see Fig. 7.15). The critical path is shaded in gray from inspection of the ckcuit, we can derive a first order model of the worst-case propagation delay of the module, written as (ĩn M

(7.10)

where tsetup, tsum and tmux are fixed delay and N and M represent the total number of bits and the number of bits per stage, respectively tcarry is the of the carry through a suigle full-adder cell.

218

'o ,

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VLSI Design

k-\

o,k*i

Fig, 7.14 Four bit carry-select module— topology.

Bit 4-7 Setup

Bit 0-3

B it 8-11

Bit 12-15

O-Carry

3E

3£ Q.o

]-Carry

Nfail%lexer

-0,3

Sum Generation

Z 3 E Z Sum Generation

^0-3

-»4-7

3E

^8-11

Fig. 7.15 Sixteen-bit, linear carry-select adder. The critical path is shaded in grey.

Subsystem Design

o

219

The carry delay through a single block is proportional to the length of that stage or equals M tca rry

The propagation delay of the adder is again, Imearly proportional to N (equation 7.10). The reason for this linear behaviour is tìiat the block-select signal that selects between the 0 and 1 solution still has to ripple dirough all stages in the worst case. 7^.7 The Cany-Lookahead Adder fhe monolithic lookahead adder When designing even faster adders, it is essential to get around the rippling effect of the carry that is still present in one form or another in both the carry-bypass and carry-elect adders. The carry-lookahead principle offers a possible way to do so. As stated before, the following rela­ tion holds for each bit position m an iV-bit adder: C o,k = f i Ạ k , B k , C o ,k - i) = G k + P k C o ,k -i

♦

7 11)

( .

The dependence between Coi and Cok-I can be eliminated by expanding Co,k-i' C o .k = G k + P á . G k - 1

+ P k -iC o .k -2 )

(7.12)

In a fiilly expanded form, C o .k = G k + P á .G k - 1 + P k - i i - - - - + P i i G o

+ -PoQo)))

(7.13)

with Qo typically equal to 0. This expanded relationship can be used to implement an TV-bit adder. For every bit, the carry and sum outputs are independent of the previous bits. The ripple effect has thus been effectively eliminated, and the addition time should be independent of the number of bits. A block diagram of the overall composition of a cany-lookahead adder is shown in Fig. 7.16. Such a high-level model contains some hidden dependencies. When we study the detailed schematics of the adder, it becomes obvious that the constant addition time in wishful think­ ing and that the real delay is at least increasing linearly with the number of bits. This is illustrated in Fig. 7.17, where a possible cữcuit implementation of equation 7.13 is shown for N= 4 note that the circuit exploits the self duality and the recursivity of the carry-lookahead equation to build a mirror structure. The large fan-in of the circuit makes it prohibitively slow for larger values of N. Implementing it with simpler gates requires multiple logic lev­ els. In both cases, the propagation delay increases. Furthermore, the fan-out on the some of the signal tends to grow excessively, slowing down the adder even more. For instance, the signals Go and Po appear in the expression for every one of the subsequent bits. Hence, the capacitance on these lines is substantial. Finally, the area of the implementation grows pro­ gressively with N. Therefore, the lookahead structure suggested by equation 7.12 is only usefiil for small values of N(<4).

220

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VLSI Design

Fig. 7.16 Conceptual diagram of a carry-look ahead adder.

'D D

■G, •Ơ, ■G o

^3

Fig. 7.17 Schematic diagram of mirror implementation of four-bit look ahead adder.

Subsystem Design

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221

73 THE MULTIPLIER Consider two unsigned binary ninnbers X and Y tíiat are M and N bits wide, respectively. To introduce the multiplication operation, it is useful to express X and Y m the binary representation X = Y ^X à' /•=0

Y = ỵ ^ Y j2 i ỹ=0

(7.14)

with ATẻ Yj e (0,1), then the multiplication operation is defined as follows: M + N -l

Z = X x.Y =

Zkl'^ *=0

X jr ,2' vm K i -“

J

M - \( N -l

i=0 \ j=0

(7.15)

The simplest way to perform a multiplication is to use a single two-input adder. For inputs that are M and N bits wide, the multiplication takes M cycles, using an A^-bit adder. This shift-and-add algorithm for multiplication adds together Mpartial products. Each par­ tial product is generated by multiplying the multiplicand with a bit of the multiplier-which essentially, is an AND operation-and by shifting the result on the basis of the multiplier bit’s position. A faster way to implement multiplication is to resort to an approach similar to manually computing a multiplication. All the partial products are generated at the same time and organized in an aưay. A multiơperand addition is applied to compute the final product. The approach is illustrated in Fig. 7.18. This set of operation can be mapped directly into hardware. The resulting structure is called an array multiplier and combines the follow­ ing three functions: partial-product generation, partial product accumulation, and final addition. 7.3.1 Partial-Product Generation Partial products result from the logical AND of multiplicand X with a multiplier bit Y (see Fig. 7.19). Each row m the partial-product array is either a copy of the multiplicand or a row of zeros. Careful optunization of the partial-product generation can lead to some substantial delay and area reductions. Note that in most cases the partial-product array has many zero rows

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VLSI Design 1 0

1 0

1 0 1 0

1 0

1 0 to 0

1 0

4

1

1 0

Multiplier

1 0

1 0

0 0 0 0 0

1 0

Multiplicand

Partial products

1 0

1 1 1 0

0

1 1 1 0

Result

Fig. 7.18 Binary multiplication— an example.

Xn

Xo

Ỏ

PPI

o pp.

o PPs

Ỏ

Ô

Ỏ

Ồ

PP^

p p.

pp.

pp,

PPc.

Fig. 7.19 Partial product generation logic.

that have no impact on the result and thus represent a waste of effort when added. In tíie case of multiplier consisting of all ones, all the partial products exist, while in the case of all zeros, there is none. This observation allows us to reduce the number of generated partial products by half. Assume, for example, an eight-bit multiplier of the form 01111110, which produces six nonzero partial-product rows. One can substantially reduce the number of nonzero rows by recoding this number (2^+2^+2^+2‘*+2^+2^) into a different format. The reader can verify that the form 10000010 with 1 a shorthand notation for -1 represents the same number. Using tiiis format, we have to add only two partial products, but the final adder has to be able to perform subtraction as well. This type of teansformation is called Booth’s recoding [booth 51] and it reduces the number of partial products to, at most, one half. It ensures that for every two consecutive bits, at m o st one bit will be 1 or -1. Reducing the number of partial products is equivalent to reducing the number of additions, which leads to a speedup as well as an area

Subsystem Design

a

223

reduction. Fonnally, this transformation is equivalent to formatting the multiplier word into a base-4 scheme, instead of the usual binary format: Y = ỵ Yj 4^' with (Yj e (-2, -1 ,0 ,1 , 2)) ý=0

(7.16)

Note that 1010... 10 represents the worst case multiplier input because it generates the most partial products (one half). While the multiplication with {0,1} is equivalent to an AND oper­ ation multiplying with {-2,-1,0,1,2} requừes a combmation of inversion and shift logic. The encoding can be performed on the fly and requữes some simple logic gates. Having a variable-size partial-product aưay is not practical for multiplier design, and a modified booth’s recoding is most often used instead. The multiplier is partitioned into threebit group that overlap by one bit. Each group of three is recoded, as shown in Table 7.2, and forms one partial product. The resulting number of partial products equals half of the multi­ plier width. The input bits to the recoding process are the two current bits, combined with the upper bit from the next group, moving from msb to Isb. In simple terms, the modified booth’s recoding essentially examines the multiplier for strings of ones from msb to Isb and replaces them with a leading 1 , and a - 1 at the end of the string. For example, o il is understood as the beginning of a string of ones and is therefore replaced by a leading 1 or (or 1 0 0 ) while, 1 1 0 is seen as the end of a string and is replaced by a-1 at the least significant position (or OlO). Modified Booth’s Recoding Consider ứie eight-bit binary number 01111110 shown earlier. This can be divided into four overlappmg groups of three bits, going from msb to lsb\ 00 (1), 11 (1), 11(1), 10 (0). Recording by using Table 7.2 yields: 1 0 ( 2 x), 0 0 ( 0 x), 0 0 ( 0 x), To ( - 2 x) or, in combmed format, 1000000Ĩ0. This is equivalent to the result, we obtained before.

Table 7.2 Modified booth’s recording Partial product selection table Multiplier bits 00 0 001 010

o il 100 101 1 10 111

Recorded bits 0

+ Multiplicand + Multiplicand +2 X Multiplicand -2 X Multiplicand -Multiplicand -Multiplicand 0

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VLSI Design

7 3 .2 Partial-Product Accumulation

After the partial products are generated, tíiey must be summed. This accumulation is essen­ tially a multioperand addition. A sừaigfatforward way to accumulate partial products is by using a number of adders that will from an aưay-hence, the name, arrcfy multiplier. A more sophisticated procedure performs the addition in a ứee format. 7 .3 .3 The Array M ultiplier

The composition of aưay multiplier is shown in Fig. 7.20. There is a one-to-one topologi­ cal coưespondence between this hardware structure and the manual multiplication shown in Fig. 7.18. The generation of N partial products requữes N X Af two bit AND gates (in the style of Fig. 7.19) Most of the area of the multiplier is devoted to the addmg of the N partial prod­ ucts, which requires N-\ M-hits adders. Shifting of the partial products for theữ proper align­ ment is performed by simple routing and does not require any logic. The overall structure can easily be compacted into a rectangle, resulting in a very efficient layout. Due to the array organization, determining the propagation delay of this cữcuit is not sfraightforward. Consider the implementation of Fig. 7.20. The partial sum adders are imple­ mented as ripple-carry structures. Performance optimization requừes that tíie critical tuning path be identified first. This turns out to be nontrivial. In fact, a large number of paữis of almost identical length can be identified. Two of those are highlighted in Fig. 7.21. A closer look at

FA

HA

FA

FA

FA

HA

T z

TZ4

~ fz -

FA

HA

Fig. 7.2Q A4 X 4 bit array multiplier for unsigned numbers-composition. HAstands for a half adder, or an adder cell with only two inputs. The hardware for the generation and addition of one partial products shaded in gray.

Subsystem Design

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Critical Paứi 1 Critical Path 2

Fig. 7.21 Ripple carry 4x4 multiplier. Two most possible critical paths are highlighted. those critical paths yields an approximately expression for the propagation delay (derived here for critical path 2). We write this as tmult — Ị M ” !)■*■ ( - ^

2 ) tcan y +

^ tsu m + tand

(7.17)

where tcan y is the propagation delay between input and output caưy, tsum is the delay between the input carry and S l u n bit of tiie full adder. And tand is the delay of the AND gate. SÌQce all critical paths have the same length, speeding up just one of them-for instance, by replacing one adder by a faster one such as a carry-select adder-does not make much sense from a design standpoint. All critical paths have to be attacked at the same tune. From equa­ tion 7.17, it can be deduced that the minimization of tmuit requires the minimization of both tcany and tsum- In this case, it could be beneficial for tc a n y to equal tsum. This conttasts with the requữements for adder cells discussed before, where a minimal tcarry was of prime impor­ tance. An example of a fiill adder cữcuit with comparable tsum and tcan y delay was shown previously.

7.ÌA Girry-Save Multiplier Due to the large number of almost identical critical paths, increasing the performance of the structure of Fig. 7.21 through transistor sizing yields marginal benefits. A more efficient real­ ization can be obtained by noticing that the multiplication result does not change when the output caưy bits are passed diagonally downwards instead of only to the right, as shown in Fig. 7.22. We include an extta adder called a vector-merging adder to generate the final result. The resultmg multiplier is called a carry-save multiplier, because the carry bits are not

226

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VLSI Design

Fig. 7.22 A 4 X 4 carry save multiplier. The critical path is high lightened in gr^. immediately added, but rather are “saved” for the next adder stage. In the final stage, car­ ries and sums are merged in a fast cany-propagate (e.g., carry-lookahead) adder stage. While this structure has a slightly increased area cost (one extra adder), it has the advantage that its worst case critical path is shorter and uniquely defined, as highlighted in Fig. 7.22 and is expressed as ^mult

(and (-^ ^tcany + Emerge still ãssumuig thãt tofij

tcarry

(7.18)

When mappmg the carry-save multiplier of Fig. 7.22 onto silicon, one has to take into account some other topological considerations. To ease the integration of the multiplier into the rest of the chip, it is advisable to make the outline of the module approximately rectan­ gular. A floor plan for the cany save multiplier that achieves this goal is shown m Fig. 7.23. Observe the regularity of the topology. This makes the generation of the structure amenable to automation. 7.3.5 The Tree Multiplier The partial-sum adders can also be reaưanged in a teee-Iike fashion, reducing botíi tìie criti­ cal path and the nximber of adder cells needed. Consider the simple example of four partial products each of which is four bits wide, as shown in Fig. 7.24(a). The number of fiill adders needed for this operation can be reduced by observation that only column 3 in the array has to add four bits. All other columns are somewhat less complex. This is illustrated in Fig. 7.24(a), where the original matrix of partial products is recognized into a tree shape to visually illus­ trate its varying depth. The challenge is to realize the complete matrix with a minimum dq)ứi and a minimum number of adder elements. The first type of operator that can be used to cover

Subsystem Design

o

227

HA Multiplier Cell

FAMulripIierCell

Vector Merging Cell

X and Y signals are broadcasted through the complete aưay.

(—

Fig. 7.23 Rectangular floor plan of carry save multiplier. Different cells are differentiated by shades of gray. X and Y signals are AND’ed before being added. The left most column of cells is redundant and can be eliminated.

Partial products 6

5

First stage

4 3

2

1

0

•

@

&

@

5 432 1 0 Bit position ® 9 @ @

6

@

@ 0 0 9 •

•

•

e

e

0 9 9 (a)

(b)

Second stage 6

5 4 w 0

FA

Final adder 3

2

1 0

m

0 ® «

@

&

©

ẽ (c)

6 5 ©

4

3

o

2

1 0

0 o

HA (d)

Fig. 7.24 Transforming a partial product tree (a) into a Wallace tree (b,c,d) using iterative covering process. The example shown is for a four bit operand.

228

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VLSI Design

the aưay is a filll adder, which takes three inputs and produces two outputs: the sum, located in the same column and the cany, located in the next one. For this reason, ứie FA is called a 3-2 compressor. It is denoted by a cừcle covering three bits. The other operator is the halfadder which takes two input bits in a coliunn and produces two ou^uts. The HA is d e n o te d b y a circle covering two bits. To arrive at the minimal implementation, we iteratively cover the tree witii FAs and HAs staring from its densest part. In a first step, we inừoduce HAs in column 4 and 3 (Fig. 7.24(b)). The reduced tree is shown in Fig. 7.24(c). A second roxmd of reductions creates a ừee of dqrth 2 (Fig. 7.24(d)). Only three FAs and three HAs are used for the reduction process, compared with six FAs and six HAs in the cany-save multiplier of Fig. 7.22. The final stage consists of a simple two-input adder, for which any type of adder can be used (as discussed n the next section. “Fmal Addition”). The presented structure is called the Wallace tree multiplier, and its implementation is shown in Fig. 7.25. The tree multiplier realizes substantial hardware savings for iaiger multipliers. The propagation delay is reduced as well. In fact, it can be shown that the propagation delay ứưough the tree is equal to o (log3/2(iV)- While substantially faster than ứie cany-save structure for large multiplier word lengths, tìie Wallace multiplier has the disadvantage of being very ữregular, which complicates the task of coming up with an efficient layout. This ữregularity is visible even in the four bit implementation of Fig. 7.25.

7.3.6 Final Addition The final step for completing the multiplication is to combine the result in ứie final adder. Performance of this “vector-merging” operation is of key importance. The choice of the adder

^2^2

Z7

25

Zj

Z4

^371 ^ 1 ^ 2

^ 3 ^ 0 ^\y\

Z3

Fig . 7.2 5 Wallace tree for four bit multiplier.

^2^0

W t

^ 0

Subsystem Design

o

229

style depends on the sừucture of the accumulation aưay. A cany-lookahead adder is the preferable option of all input bits to the adder arrive at the same time as it yields the small­ est possible delay.. This is the case if a pipeline stage is placed right before the final addition. Pipelming is a technique frequently used in high performance multipliers. In non-pipelined multipliers, the arrival time profile of the mputs to the final adder is quite uneven due to the varying logic depths of the multiplier tree. Under these cừcumstances, otìier adder topologies such as cany select, often yield performance numbers similar to lookahead at a substantially reduced hardware cost.

lA THE SHIFTER The shift operation is another essential arithmetic operation that requừes adequate hard ware support. It is used extensively in floating-point units, scalers, and multiplication by constant number. The latter can be implemented as a combination of add and shift operations. Shiftmg a data word left or right over a constant amount is a trivial hardware operation and is imple­ mented by the appropriate signal wking. A programmable shifter, on the other hand, is more' complex and requires active cữcuitry. In essence, such a shifter is nothing less than an intri­ cate multiplexer circuit. A simple one-bit left-right shifter is shown in Fig. 7.26. Depending on the control signals, the input word is either shifted left or right, or else it remains unchanged. Multibit shifters can be built by cascading a number of these units. This approach rapidly becomes complex, unwieldy, and ultimately too slow for larger shift values. Therefore, a more structured approach is advisable. Next, we discuss two commonly used shift structures, the barrel shifter and the logarithmic shifter.

Right

nop

Left

TI >

B.

j - r A,i-i

I—I

n

I — C.

>

5,., Bit-Slice i

Fig. 7.26 One-bit (left-right) programmable shifter. The data passes undisturbed under the nop condition.

230

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VLSI Design

7^.1 Barrel Shifter

■ậ The structure of ã baưel shifter is shown in Fig. 7.27. It omsists of an airay of toansistors, in which the number of rows equals the word lengtíi of the data, and ứie number of column equals the maximum shift width. In this case, both are set equal to four. The ctmtrol wires are routed diagonally through the aưay. A major advantage of this shifter is that die signal has to pass through at most one transmission gate. In other words, the propagation delay is tìie©retically constant and independent of the shift value or shifter size. This is not frue in reality, however, because the capacitance at the input of the buffer rises linearly with the maximum shift width. An important property of tiiis ckcuit is that the layout size is not dominated by the active taansistors as in the case of all other aríứunetic cừcuits, but by the niimber of wkes running tfarougji tíie cell. More specifically, the size of the cell is bounded by tìie pitch of the metal wửes! Another important consideration when selecting a shifter is the format in which the shift value must be presented. From the schematic diagram of Fig. 7.27, we see that the barrel shifter needs a control wữe for every shift bit. For example, a foiư-bit shifter needs four con­ trol signals. To shift over three bits, the signals ShsiSho take on the value 1000. Only one of the signals is high. In a processor, the requừed shift value normally comes in an encoded binary format, which is substantially more compact. For instance, the encoded control word

: Data Wừe 5>

: Control Wữe

Bn

Fig. 7.27 Barrel shifter with a programmable shift width from zero to three bits to the right. The structure supports automatic repetition of the sign bit As also called sign bit extension.

Subsystem Design

a

231

needs only two control signals and is r^resented as 11 for a shift over three bits. To translate the latter representation into the fonner (with only one bit high), an exừa module called a decoder is requừed.

1A2 Logarithmic Shifter While the barrel shifter implements ứie whole shifter as a single aưay of pass transistors the logarithmic shifter uses a staged approach. The total shift value is decomposed into shifts over powers of two. A shifter with a maximum shift width of M consists of a log2M stages, where die iứi stage either shifts over 2' or passes the data unchanged. An example of a shifter with a maximum shift value of seven bits is shown in Fig. 7.28. For instance, to shift over five bits, the first stage is set to shift mode, the second to pass mode, and the last stage again to shift. Notice that the control word for this shifter is abeady encoded and no separate decoder is requừed. The speed of the logarithmic shifter depends on the shift width in a logarithmic way, since to M-bit shifter requừes log2M stages. Furthermore, the series connection of pass tonsistors slows the shifter down for larger shift values.

Sh| Sh,

Sh4 Sh4

Sh, Sh,

IS

Irft

jf t

JTX-

Jhk

---------- 1

jft.

A,

ppc>

jljT t

B,

j

Tt

t

a

f in

_n Fig. 7.28 Logarithmic shifter with maximum shift width of seven bits to the right, (only four least significant bits are shown)

232

a

VLSI Design

In general, we conclude that a barrel shifter is appropriate for smaller shifters. Far Ifflger shift values, the logarithmic shifter becomes more eifecthre, in terms of bodi area and speed. Furthermore, the logarithmic shifter is easily parametrized, allow ing for automatic genetaf tion. The most important concept of this section is that the exploitation of regularity in an arithmetic operator can lead to dense and high-speed cứcuit implementations. 7.5 MEMORY ELEMENTS 7.5.1 SRAM An SRAM (Static Random Access Memory) is designed to fill two needs; to provide a dừect interface with the CPU at speeds not attainable by DRAMs and to replace DRAMs in systems that require very low power consumption. In the first role, the SRAM serves as cache mem­ ory, interfacing between DRAMs and the CPU. Figure 7.29 shows a typical PC microproces­ sor memory configuration. The second driving force for SRAM technology is low power applications. In this case, SRAMs are used in most portable equipment because the DRAM refresh ciưrent is several orders of magnitude more than the low-power SRAM standby ciurent. For low-power SRAMs, access time is comparable to a standard DRAM. How the Device Works The SRAM cell consists of a bi-stable flip-flop connected to the internal cừcuitry by two access ứansistors. When the cell is not addressed, the two access transistors are closed and the data is kept to a stable state, latched within the flip-flop (Fig. 7.30). The flip-flop needs the power supply to keep the information. The data in an SRAM cell is volatile (i.e., the data is lost when the power is removed). However, the data does not “leak away” like in a DRAM, so the SRAM does not require a refresh cycle. ReadAVrite Figure 7.31 shows the read/write operations of an SRAM. To select a cell, the two access transistors must be “on” so the elementary cell (the flip-flop) can be connected to the internal

SRAM

Microprocessor

External Cache (L2) 64 KB to 1 MB

Internal Cache (LI) 8 KB to 32 KB Fig . 7.2 9 Memories in a microprocessor.

DRAM Main Memoiy 4 MB to 512 MB

Subsystem Design

Word Line

------ ị Í----------

. 1

- O Í

1

----------- ( t------

^ 1

1

1

u
B y r ~ To Sense Amplifier Fig. 7.30 SRAM cell.

Word Line

Word Line

r l> ^ 1_

U<^

|

r~ i

Column Decode v

Column Decode

Sense Amplifier (Voltage Comparator)

♦ Write CircuitT)Ỉ

D Out

Din

READ OPERATION Fig . 7.3 1 Read/Write operations.

WRITE OPERATION

o

233

234

o

VLSI Design

SRAM circuitry. These two access ữansistors of a cell are connected to ứie word line (a called row or X address). The selected row will be set at v c c . The two flip-flop sides are 1 connected to a pair of lines, B and B. The bit lines are also called colunuỉs or Y addresses. During ã read operation these two bit lines are connected to the sense amplifier that recog­ nizes if a logic data “1” or “0” is stored in the selected elementary cell. This sense amplifier then transfers the logic state to the output buffer, which is connected to the output pad. There are as many sense amplifiers as there are output pads. During a write operation, data comes from the input pad. It then moves to the write cữcuitry. Since the write cữcuitry drivers are stronger than the cell flip-flop transistors, the data will be forced onto the cell. When the read/write operation is completed, the word line (row) is set to ov, the cell (flip-flop) either keeps its original data for a read cycle or stores the new data, which was loaded during the write cycle. Data Retention To work properly and to ensure that the data m the elementary cell will not be altered, the SRAM must be supplied by a Vcc (power supply) that will not fluctuate beyond plus or minus five or ten per cent of the VccIf the elementary cell is not disturbed, a lower voltage (2 volts) is acceptable to ensure that the cell will coưectly keep the data. In that case, the SRAM is set to a retention mode where the power supply is lowered, and the part is no longer accessible. Figure 7.32 shows an exam­ ple of how the Vcc power supply must be lowered to ensure good data retention. Data Retention Mode ^cc

3.0 V

V

______f k H Z _____

•3.0 V

Fig, 7.32 SRAM data retention waveform.

MEMORY CELL Different types of SRAM cells are based on the type of load used in the elementary inverter of the flip-flop cell. There are cuưently three types of SRAM memory cells: • The 4T cell (four nMOS ừansistors plus two poly load resistors) • The 6 T cell (six transistors^—four nMOS ừansistors plus two pMOS transistors) • The TFT cell (four nMOS transistors plus two loads called TFTs) 4 Transistor (4T) Cell The most conunon SRAM cell consists of four nMOS transistors plus two poly-load resis­ tors (Fig. 7.33). This design is called the 4T cell SRAM. Two nMOS transistors are passtransistors. These transistors have their gates tied to the word line and connect the cell to the columns. The two other nMOS transistors are the pull-downs of the flip-flop inverters. The loads of the inverters consist of a very high polysilicon resistor.

Subsystem Design

o

235

To Sense Amps Fig. 7.33 SRAM4T (Four-transistor) cell.

This design is the most popular because of its size compared to a 6 T cell. The cell needs room only for the four nMOS ừansistors. The poly loads are stacked above these ừansistors. Although tìie 4T SRAM cell may be smaller than the 6 T cell, it is still about four times as large as the cell of a comparable generation DRAM cell. The complexity of the 4T cell is to make a resistor load high enough (in the range of gigaohms) to mmimize the cuưent. However, this resistor must not be too high to guarantee good fimctionality. Despite its size advantage, the 4T cells have several limitations. These include the fact tìiat each cell has current flowing in one resistor (i.e., the SRAM has a high standby current), the cell is sensitive to noise and soft eưor because the resistance is so high, and the cell is not as fast as the 6 T cell. Transistor (6 T) Cell A different cell design that eliminates the above limitations is the use of a CMOS flip-flop. In this case, the load is replaced by a pMOS transistor. This SRAM cell is composed of six transistors, one nMOS ttansistor and one pMOS transistor for each inverter, plus two nMOS transistors connected to the row line. This configuration is called a 6 T Cell. Figure 7.34 shows this structure. This cell offers better electrical performances (speed, noise immunity, standby ciưrent) than a 4T structure. The mam disadvantage of this cell is its large size. Until recently, the 6 T cell architecture was reserved for niche markets such as military or space that needed high immunity com­ ponents. However, with commercial applications needing faster SRAMs, the 6 T cell may be implemented into more widespread applications in the future. Much process development has been done to reduce the size of ứie 6 T cell. 6

236

o

VLSI Design

N/ To Sense Amps Fig. 7.34 SRAM 6T (Six-transistor) cell.

TFT (Thin Film Transistor) CeU Manufacturers have tried to reduce the cwrent flowing in the resistor load of a 4T cell. As a result, designers developed a structure to change, during operating, the electrical characteristics of the resistor load by controlling the channel of a transistor. This resistor is configured as a pMOS ừansistor and is called a thin film ừansistor (TFT). It is formed by dq>ositing several layers of polysilicon above the silicon surface. The source/channel/drain is fonned in ứie poly­ silicon load. The gate of this TFT is polysilicon and is tied to the gate of the opposite mverter as m the 6 T cell architecture. The oxide between this control gate and the TFT polysiiicon channel must be thin enough to ensure the effectiveness of the fransistor. The performance of the TFT pMOS (Fig. 7.35) transistor is not as good as a standard pMOS silicon transistor used in a 6 T cell. It should be more realistically compared to the linear polysilicon resistor characteristics. Reading Data From Memory Figure 7.36 shows the timing diagram for the sunplified read operation. It is used to illusfrate the following example. To read data from a memory cell, the cell must be selected using its row and column coor­ dinates, the state of the cell must be determined, and the information must be sent to the data output. In terms of timing, the following steps must occur: 1. Before the clock transition (low to high) that initiates the read operation (1), the row and column addresses must be applied to the address input pins (ADDR) (2), the chip must be selected (3), and the Write Enable must be high (4). Note that each of these signals must be present and valid a specified amount of time (the set up time) before the clock switches from low to high, and must remain valid for a specified amount of time (Ihe

Subsystem Design

o

237

Word Line Ọ

I/

3h

Poly-Si PMOS

\

Ọ

BL

BL

Fig. 7.35 SRAM TFT cell.

hold time) after the clock switches (7). When the chip select (CS) is low, the chip is selected. When it is high (inactive), the chip cannot accept any input signals. The Write Enable is used to choose between reading and writing. When it is low, a write operation occurs; when it is high, a read operation occurs. 2. On the rising edge of the clock (CLK) (1), the address is registered and the read cycle begins. 3. If the Output Enable is being used to conữol the appearance of data at the output, OE must go low (5). OE is an asynchronous signal; it can be activated at any time. When OE is high, the DQs are fri-stated; data from the memory will not appear on the outputs. 4. Data appears at the output pins of the SRAM (6 ). The time at which the data appears depends on the access time of the device, die delay associated with the Output Enable and the type of SRAM you are using. The access time of the SRAM is the amount of time requừed to read a bit of data from the memory when all of the timing requirements have been met. Note: DQo is the data associated with Address 0 (AO). DQi is the data associated with Address 1 (Al). Writing Data to Memory Figure 7.37 shows a simplified timing diagram for the write operation used in the following example. To vmte data to a memory cell, the cell must be selected using its row and column coordinates, the data to be stored must be applied at the data input pins, and the information

238

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VLSI Design

must be stored in the selected memory cell. In terms of timing, the following steps must occur: 1. Before the clock transition (low to high) that initiates the write operation (1), the row and column addresses must be applied to the address input pins (ADDR) (2), the chip must be selected (3), the Write Enable must be low (4) and the data to be writ­ ten must be applied to the data input pins (5). If the SRAM has Byte Write Enables, they must be low as well. Note that each of these signals must be present and valid a specified amount of time (the set up time) before the clock switches from low to high, and must remain valid for a specified amount of time (the hold time) after the clock switches. When the chip select (CS) is low, the chip is selected. When it is high (inactive), the chip cannot accept any input signals. The Write Enable is used to choose between reading and writing. When it is low, a write operation occurs; when it is high, a read operation occurs. When the Byte Write Enables are high, no data may be written to the memory. When they are low, data may be written to the associated data inputs. 2. On the rising edge of the clock (CLK) (1), the address and input data are latched and the write operation begins. The data is stored in the selected memory cell.

Subsystem Design

o

239

CLK

ADDR

Chip Select

cs

Write Enable WE )ataJnput DI

Fig. 7.37 Writing into memory. 7.5.2 DRAM DRAM (Dynamic Random Access Memory) is the main memory used for all desktop and larger computers. Each elementary DRAM cell is made up of a single MOS ữansistor and a storage capacitor (Fig. 7.38). Each storage cell contains one bit of information. This charge, however, leaks off the capacitor due to the sub-threshold cuưent of the cell transistor. There­ fore, the charge must be refreshed several times each second. Bit ,ine Word Line

c

Transistor Capacitor

^

Plate

Fig. 7.38 DRAM cell.

240

o

VLSI Design

How the Device Works The memory cell is written to by placing a “1” or “0” chaige into the capacitor celL This Ú done during a write cycle by opening the cell transistor (gate to power supply or V cc) and presenting either Fee or 0 V (ground) at the capacitor. The word line (gate of the ừansỉstor) it then held at ground to isolate the capacitor charge. This capacitor will be accessed for eilhw a new write, a read, or a refresh. Figure 7.39 shows a simplified DRAM diagram. The gates of tìie memory cells are tied to the rows. The read (or write) of a DRAM is done in two main steps as iUusưated in Fig. 7.40. The row (X) and column (Y) addresses are presented on the same pads and multiplexed. The first step consists of validating the row addresses and the second step consists of validating die colunm addresses. First Step: Row Addresses Row addresses are present on address pads and are internally validated by the RAS (Row Address Access) clock. A bar on top of the signal name means this signal is active when it is at a low level. The X addresses select one row through the row decode, while all the oứier non-selected rows remain at 0 V. Each cell of the selected row is tied to a sense amplifier. A sense amplifier is a circuit that is able to recognize if a charge has been loaded into the capaci­ tor of the memory cell, and to translate this charge or lack of charge into a 1 or 0. There are as many sense amplifiers as there are cells on a row. Each sense amplifier is connected to

Address pads C A S> -

X

\

Ằ RAS Data

Sense Data Amplifiei

ị

Data Dnui

Output Buffer

D.in

Input Buffer

Sense Data Amplifiei

ị

ị

Data.---------Sense Data Ajnplifiei Data.---------Sense Data Amplifiei

ị

ị ị ị

ị

Fig . 7.3 9 Simplified DRAM diagram.

ị ị ị ị

Subsystem Design

\

RAS

Address

X

Row

X

Column

X

\

CAS Step I

Row Access

Step II

Column Access

Fig. 7.40 DRAM access timing.

a column (Y address). In this first step, all the cells of the entire row are read by the sense amplifier. This stq) is long and critical because the row has a high time constant due to the fact that it is formed by the gates of the memory cells. Also, the sense amplifier has to read a very weak charge (approximately 30 femtoFarads or 30fF). Second Step: Column Addresses Following the first step, column addresses are present on the address pads and are internally validated by the Column Address Access (CAS) clock. Each selected memory cell has its data validated in a sense amplifier. Colxrnm access is fast. This step consists of transferring data present in the sense amplifier to the Dout pin through the column decode and the output buf­ fer. On memory data sheets, the access time from RAS is termed tRAC and the access time from CAS is listed as tCAC. On a typical standard DRAM of 60ns access time, tRAC = 60ns andtCAC = 15ns. Refresh To maintain data integrity, it is necessary to refresh each DRAM memory cell. Each row of cells is refreshed every cycle. For example, if the product specification states, “Refresh cycle = 512 cycles per 8 ms,” then there are 512 rows and each individual row must be refreshed every eight milliseconds. As explained above, during the row access step, all the cells from the same row are read by the sense amplifier. The sense amplifier has two roles. Since it holds information within the cell, it is able to transmit this data to the output buffer if it is selected by the column address. The sense amplifier is also able to re-transmit (write) the information into the memory cell. In this case, it “refreshes” ứie memory cell. When one row is selected, all the cells of that row are read by the sense amplifiers and all these cells are refreshed one at

242

o

VLSI Design

a time. Burst or distributed refresh methods can be used. Burst refresh is done by perfoimim' a series of refresh cycles until all rows have been accessed. For ứie example given above, tỉdbi is done every 8 ms. During the refresh, other commands are not allowed. Using the distrib^ uted method and the above example, a refresh is done every 12.6 ^s ( 8 ms divided by 512). Figure 7.41 shows these two modes.

a refresh cycle Fig. 7.41 Burst and distributed refresh.

For standard DRAMs there are three ways to perform refresh cycles. They are RAS-only refresh, CAS-before-RAS refresh, and hidden refresh. To perform a RAS-only refresh, a row address is put on the address lines and then RAS goes low. To perform a CAS-before-RAS refresh, CAS first goes low and then a refresh cycle is performed each time RAS goes low. To perform a hidden refresh the user does a read or write cycle and then brings RAS high and then low. MEMORY CELL A great deal of design effort has been made to shrink the cell area, particularly, the size of the DRAM capacitor. As memory density increases, the cell size must decrease. Designers have managed to shrink overall cell size. However, due to factors such as noise sensitivity and speed, it has been a challenge to reduce the capacitance. The capacitance must stay in the range of 30fF. The charge (Q) stored in a capacitor is equal to capacitance times voltage (Q = c X V)Over the years, DRAM operating voltage has decreased (i.e., 12 V tó 5 V to 3.3 V). As voltage decreases, the stored charge will also decrease. Design improvements allow for the decrease in the cell charge as long as the capacitance remains in the range of 30 fF. Two main develop­ ments are used to reduce capacitor area without reducing its value. These are the use of new capacitor shapes to fit into a minimum chip surface area and increasing the dielectric constant. Memory Cell Shape The 1 Mbit DRAM generation was the first to abandon the classical planar capacitor and replace it with a trench or a stacked capacitor. As shown, the major 64 Mbit DRAMs available on the market are today made of stacked capacitors. Cross-sections of 64 Mbit DRAMs used by HITACHI is shown in Fig. 7.42.

Subsystem Design

a

243

Fig. 7.42 Hitachi 64 Mbit DRAM cross-section.

PERFORMANCE Compared with other memory ICs, DRAMs suffer from a speed problem. The on-chip cir­ cuitry required to read the data from each cell is inherently slow. As such, DRAM speeds have not kept pace with the increased clock speed of CPUs. *

► What are the advantages of SRAM over DRAM? There are many reasons to use an SRAM or a DRAM in a system design. Design tradeoffs include density, speed, volatility, cost, and features. All of ứiese factors should be considered before you select a RAM for your system design. 1. Speed. The primary advantage of an SRAM over a DRAM is its speed. The fast­ est DRAMs on the market still requừe five to ten processor clock cycles to access the first bit of data. Fast, synchronous SRAMs can operate at processor speeds of 250 MHz and beyond, wiứi access and cycle times eqxial to the clock cycle used by the microprocessor. Wiứi a well designed cache usmg ultta-fast SRAMs, condi­ tions in which the processor has to wait for a DRAM access become rare. 2. Density. Because of the way DRAM and SRAM memory cells are designed, readily available DRAMs have significantly higher densities than the largest SRAMs. Thus, when 64 Mb DRAMs are rolling off the production lines, the largest SRAMs are expected to be only 16 Mb. 3. Volatility. While SRAM memory cells require more space on the silicon chip, they have other advantages that translate directly into improved performance. Unlike DRAMs, SRAM cells do not need to be refreshed. This means they are available for reading and writing data 1 0 0 % of the time.

244

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VLSI Design

4. Cost. If cost is the primary factor in a memory design, then DRAMs win hands down. If, on the otfier hand, performance is a criticai fa c to r , then a welldesigned SRAM is an effective cost performance solution.

1. A digital processor consists of the datapath, memory, conữol, and input/output blocks. 2. The datapath is the core of the processor and this is where all computations are performed. 3. Circuit optimization, on the other hand, manipulates transistor sizes and cừcuit topology to optimize the speed. 4. In the ripple cany adder the cany bit ripples from one stage to another. The delay through the cừcuit depends upon the number of stages that must be tra­ versed and is a function of the applied input signals. 5. The propagation delay of the ripple carry adder is Imearly Ịíroportional to N. This property becomes very important when designing adders for wide data paths. 6 . Transmission-gate-based adder is based on the propagate-generate model 7. A Manchester carry-chain adder uses a cascade of pass ưansỉstors to imple­ ment the carry chain. 8 . The SRAM serves as cache memory, interfacing between DRAMs and the CPU.

1. A _____________ uses a cascade of pass ừansistors to unplement the cany chain. 2. The delay in the addition operation can be reduced by using_______property. 3. In cany bypass adder the cany propagates either through_______________ . 4. In ___________ adder every full adder cell has to wait for the incoming carry before an outgoing carry can be generated. 5. In cany save multiplier the cany bit is passed_________ . 6 . In : ’_____ multiplier propagation delay is reduced for larger multiplications: 7. _______ is used in cache memory.

Subsystem Design

8 . __________ ^cell consists of bi-stable flip-flop. 9. DRAM is made of ____________ ^transistor. 10. DRAM has to b e _________ to retain the logic value.

Answers Ỉ. 2. 3. 4. 5. 6. 7. 8. 9. 10.

Manchester cany chain Inverting Bypass patfi. Ripple cany adder Diagonally Wallace tree multiplier SRAM SRAM Single nMOS Refreshed.

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CHAPTER

CHAPTER OBJECTIVES In this chapter, you will be introduced to • • • • • • • • • • •

Simulation Logic synthesis Inside tiie synthesizer Constramts in synthesis Technology libraries VHDL and logic synthesis Functional gate-level verification Inverter delays Placmg and routing Post layout timing simulation Static timing

8.1 SIMULATION Simulation is one of the most important methods for chip functional verification. Simulation is also a very powerful technique in verifying a chip’s timing characteristics. During chip development, simulations are earned out at different stages, such as at the component level (standard cell design, analog cell design and memory design), system level, RTL level, gate

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level, and post-layout gate level. Accordingly, simulators are usually divided into die follow­ ing categories or simulation modes: 1. 2. 3. 4. 5. 6.

Behavioural simulation Functional simulation Static timing analysis Gate-level simulation Switch-level simulation Transistor-level or circuit-level simulation.

This list is ordered from high-level to low-level simulation (high-level being more abstract and low-level being more detailed). Proceeding from high-level to low-level sũnulation, the simulations become more accurate, but they also become progressively more complex an( take longer to run. 1. Behavioural simulation models the subcomponents of a system as black boxes with inputs and outputs. Often c , VHDL, or Verilog are used to model. 2. Functional simulation ignores timing. It includes unit delay duiing simiilation, which sets delays of the components to a fixed value (for example, 1 ns). Once a behavioiưal or functional simulation predicts that a system can work coưectly, the next stq) is to check the timing performance. 3. Gate-level simulation is also used to check the timing performance of an ASIC. In a gate-level simulator, a logic gate (NAND, NOR, and so on) is treated as a black box modelled by a function whose variables are the input signals. This function may also model the delay through the logic cell. Gate-level simulation is mostly used in post synthesis or post-layout netlists. It is especially useful for verifying asynchronous timing paths since they cannot be handled efficiently by static timing analysis. 4. Switch level simulation In this type of simulation transistors are modelled as switches with ON and OFF conditions. Switch level simulation merges gate-level logic simulation techniques by modelling fransistors as switches. It provides more accurate timing that gate-level simulation. Example is RSIM in which gates are modelled as either pull up or pull down structures and calculates resistance between power rails. This resistance when multiplied with output capacitance gives rise time and fall time from which propagation delays can be calculated. 5. Transistor level or circuit level simulation It is the most detailed and accurate simulation. It is very complex and time-consuming simulation process. Circuit simulators are concerned about electrical behaviour of vari­ ous parts of the circuit to be implemented in silicon. SPICE is used for this type of sim­ ulations. The basis for SPICE program is to solve the equations relating ckcuit voltages, cuưents and resistances. The simulation times depends on the number of non-linear

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devices in the cứcuit. cữcuit simulators cannot be assiuned to accurately predict the perfoimance of the design. The three major sources of eưor are • ỉnacciưacies in MOS modelling parameters • The use of an in appropriate M OS model • Inaccuracies in parasitic capacitances and resistances. Vừtually all cừcuit level sũnulators used for ASIC design are commercial versions of SPICE. Simulators may be used to verify the results of any of the design stages. In addition to the circuit description, a simulator needs a set of simulation data or stimuli. The simulation pro­ gram applies this data to the input description at the specified times and generates responses of the cừcuit. The results of a simulation program may be illustrated by waveforms, timing diagrams, or time-value tabular listings. These results are interpreted by the designer, who detennines whether to repeat the design stage if simulation results are not satisfactory. Regardless of tìie level of design to which a simulation program is applied, digital system simulators have generally been classified into oblivious and event-driven simulators. In oblivi­ ous stimulation, each cừcuit component is evaluated at fixed time points, while in event-driven simulation, a component is evaluated only when one of its inputs changes. 8.1.1 Oblivious Simulation As an illustration of the oblivious simulation method, consider the gate network of Fig. 8.1(a). This is an exclusive-OR circuit that uses AND, OR, and NOT primitive gates and is to be simulated with the data provided in Fig. 8.1(b).

(b)

Fig. 8.1 An exclusive -OR function in terms of AND, OR and NOT (a) logical diagram (b) test data.

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GATE 1

FUNCTION Input Input NOT NOT AND AND OR

INPUT 1 INPUT2

VALUE 0 0

4

Fig. 8.2 Tabular representation of exclusiv&-OR circuit for oblivious simulation.

The first phase of an oblivious simulation program converts the input cũcuit description to a machine-readable tabular form. A simple example of such a table is shown in Fig. 8.2. ITiis table contains information regarding the cữcuit components and theừ intercoimectíons, as well as the initial values for all nodes of the cữcuit. After the initialization of the cữcuit, the simulation phase of an oblivions simulation metbod reads input values at fixed time intervals, applying them to the internal tabular representatíon of the cữcuit. At time ti, input values of a and b are read from an input file. Hiese values replace the old values of a and b in the value column of the table of Fig. 8.2. Using these new values, the output values of all cừcuit components will be reevaluated, and changes will be made to the value column of the effected components. A change in any value column indi­ cates that the cữcuit has not stabilized, and more revaluation of the table may be necessaiy. Sequential computation of ail output values contmues until ã single pass through the table necessitates no new changes. At this time, all node values for time ti will be rqx>rted, the time indicator will be incremented to ti+i, and new data values will be read from ứie data file. 8.1.2 Event-Driven Simulation Event-driven simulation, while more complex than oblivious simulation, is a more efiBcient method of digital system simulation. In event-driven simulation, when an input is changed, only those nodes that are effected are reevaluated. A data structure suitable for implementing event-driven simulation of our sũnple gate-level example of Fig. 8 .1 is shown in Fig. 8.3. The first phase of an event-driven simulation program converts the circuit description to a linked-list data structure like that in Fig. 8.3. In the second phase of the simulation, a change on an input triggers only those nodes of the linked list for which an input changes. For exam­ ple, at time h (/ = 2) m Fig. 1.8(b), transition of a form ‘0’ logic level to ‘1’ causes node 1 of the linked list to change its output from ‘0’ to ‘r . Since this node feeds nodes 3 and 6 , these nodes will also be evaluated, which causes theữ outputs to change to ‘0 ’ and ‘1 ’ respectively. These changes then propagate to nodes 5 and 7 until the output value is evaluated. No iiulfaer computations will be done until ts, when input b changes. As shown, event-driven simulation does not evaluate cữcuit nodes until there is a change on an input. When an event occurs on an input, only nodes that are affected are evaluated.

VHDL Modelling of Digital Systems

Inp

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AND

NOT

OR

Inp

NOT

(a)

Ini In2 Fnc out

Ini: Input 1 Id2; Input 2 Fnc: Function out: output value

(b) Fig. 8.3 (a) Linked list representation of exclusive-OR circuit for event driven simulation (b) Skeleton. and all other node values will be unchanged. Since activities occur only on relatively small portions of digital cừcuits, evaluation of all nodes at all times, as is done in oblivious simula­ tion, is unnecessary. Because of parallelism in hardware structures, event-driven simulation is a more suitable simulation method for digital systems. The speed of this method justifies its more complex data structure and algorithm. 8.2 LOGIC SYNTHESIS Synthesis is an automatic method of converting a higher level of abstraction to a lower level of abstraction. The current synthesis tools available today convert Register Transfer Level (RTL) descriptions to gate-level netlists. These gate level netlists consist of interconnected gate-level macro cells. Models for the gate level cells are contained in technology libraries for each type of technology supported. Designers use graphic or text design enừy to create an HDL behavioural model, which does not contain any references to logic cells. State diagrams, graphical datapath descriptions, truth tables, RAM/ROM templates, and gate-level schematics may be used together with an s

>■ What are the inputs to the logic synthesis? The inputs to the synthesis process are an RTL (Register Transfer Level) VHDL description, cữcuit consừamts and attributes for the design, and a technology library.

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The synthesis process produces an optimized gate level netlist from all of these inputs.

HDL description. Once a behavioural HDL model is complete, two items are requừed to pro­ ceed: a logic synthesizer (software and documentation) and a cell library (the logic cells— NAND gates and such) that is called the target library. Most synthesis software companies produce only software. Most ASIC vendors produce only cell libraries. The behavioural model is simulated to check that the design meets the specifications and then the logic synthesizer is used to generate a netlist, a structural model, which contains only references to logic cells. There is no standard format for the netlists that logic synthesis produces, but EDIF is widely used. Some logic-synthesis tools can also create structural HDL (Verilog, VHDL, or both). Following logic synthesis the design is simulated again, and the results are compared with the earlier behavioural simulation. Layout for any type of ASIC may be generated from the struc­ tural model produced by logic synthesis. 8.3 INSIDE A LOGIC SYNTHESIZER A logic synthesizer performs translation, logic minimization and logic optimization, and map­ ping to gates functions. Each of them is described below. 8.3.1 Translation The RTL description is translated to an unoptimized boolean description usually consisting of primitive gates such as AND and OR gates, flip-flops, and latches. This is a function­ ally coưect but completely unoptimized description. All IF, CASE, and LOOP statements,

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conditional signal assignments, and selected signal assignment statements are converted to ứieừ Boolean equivalent in this intermediate form. Flip-flops and latches can either be instan­ tiated or inferred; both cases produce the same flip-flop or latch entry in the intermediate description. 83 J Logic Minimization and Logic Optimization Logic minimization involves the reduced number of literals which ultimately saves the sili­ con area. The output characteristic equations of the cừcuit’s logic minimization are known as synthesized network. Minimization can be understood by Karnaugh maps. The Logic optimization process takes an unoptimized Boolean description and converts it to an optimized Boolean description. Optimization uses a senes of factoring, substitution, and elimination steps to simplify the equations that represent the synthesized network. This is where the real work of synthesis gets done. The optimization process uses a number of algorithms and rules to convert the unoptimized Boolean description to an optimized one. One technique is to convert the unoptimized Boolean description to a very low-level description (a PLA format), optunize that description (using PLA optimization techniques). 83.2.1 Flattening

The process of converting the unoptimized Boolean description to a PLA format is known as flattening, because it creates a flat signal representation of only two levels: an AND level and an OR level. The idea is to get the unoptimized Boolean description into a format in which optimization algorithms can be used to optimize the logic. A PLA structure is a very easy description in which to perform Boolean optimization, because it has a simple structure and the algorithms are well known. An example of a Boolean description is shown here: Original equations: a = b and c; b = X or (y and z); c = q or w; This description shows an output a, has three equations describing its function. These equa­ tions use two intermediate variables b and c to hold temporary values which are then used to calculate the final value for a. These equations describe a particular structure of the design that contains two intermediate nodes or signals, b and c. The flattening process removes these intermediate nodes to produce a completely flat design, with no intermediate nodes. For exam­ ple, after removing intermediate variables: a = (x and q) or (q and y and z) or (w and x) or (w and y and z); This second description is the Boolean equivalent of the first, but it has no intermediate nodes. This design contains only two levels of logic gates: an AND plane and an OR plane. This

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should result in ã very fast design because there are very few logic levels fimn ứie to output. In fact, the design is usually very fast. There are, however, a number of ptobleiiis witfkr this type of design. First, this type of design can actually be slower than one ứiat has more logic levels. TliỀ reason is that this type of design can have a ừemendous fanout loading on die iiqnit signab because inputs fan out to every term. Second, this type of design can be very laige, becaaie there is no sharing between terms. Every term has to calculate its own ftmctionality. Also, There are a number of circuits that are difficult to flatten, because the number of terms created is extremely large. An equation that only contams AND functions produces one tenn. A fimction that contains a large XOR function can produce hundreds or even tíiousands of tenns. A 2-input XOR has the terms A and (not B) or B and (not A). An N-inpiit XOR has 2**(N-1) terms. For instance, a 16-input XOR has 32,768 terms and a 32- bit XOR has over 2 billion terms. Clearly, designs with these types of functions cannot be flattened. Flattening gets rid of all of the implied structure of design whether it is good or not. Flatten­ ing works best with small pieces of random control logic that the designer wants to minimize. Used in conjunction with structuring, a minimal logic description can be generated. Usually, the designer wants a design that is nearly as fast as the flattened design, but is much smaller in area. To reduce the fanout of the input pins, terms are shared. Some synthesis vendors call this process structuring or factoring. 83.2.2 Factoring

Factoring is the process of adding intermediate terms to add structure to a description. It is the opposite of the flattening process. Factoring is usually desirable because, as was men­ tioned in the last section, flattened designs are usually very big and may be slower than a factored design because of the amount of fanouts generated. Following is a design before factoring: X = a and b or a and d; y = z or b or d;

After factoring the conưnon term, (b or d), is factored out to a separate intermediate node. The results are shown here: X = a and q;

y = z or q; q = b or d; Factoring usually produces a better design but can be very design dependent. Adding sứucture adds levels of logic between the inputs and outputs. Adding levels of logic adds more delay. The net result is a smaller design, but a slower design. Typically, the designer wants a design that is nearly as fast as the flattened design if it was driven by large drivers, but as small as the completely factored design. The ideal case is one in which the critical path was flattened for speed and the rest of the design was factored for small area and low fanout.

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After the design has been optimized at the Boolean level, it can be mapped to the gate functions in a technology libraiy. In summary, logic optimization attempts to simplify tíie equations in the hope that this will also minimize area and maximize speed. 833 Mapping to Gates or Tedinology-Decomposition The mapping process takes the logically optimized Boolean description created by the opti­ mization stq) and uses the logical and timing information from a technology library to build a netlist. This netlist is targeted to the user’s needs for area and speed. There are a number of possible netlists that are functionally the same but vary widely in speed and area. Some netlists are very fast but take a lot of library cells to implement, and others take a small num­ ber of library cells to implement but are very slow. To illusfrate this point, let’s look at a couple of netlists that implement the same functional­ ity. Following is the VHDL description: LIBRARY IEEE; USE IEEE.stdJogic_1164.ALL: USE IEEE.stdJogic_unsigned.ALL; ENTITY adder IS PORT{ a,b : IN std_logic_vector(7 DOWNTO 0); PORT( c ; OUT stdJogic_vector(7 DOWNTO 0): PORT(): END adder; ARCHITECTURE test OF adder IS BEGIN c <= a + b; END test;

Both of the examples implement an 8 -bit adder, but the first implementation is a small but slower design, and the second is a bigger but fast design. The small but slower design is an 8 -bit npple carry adder shown in Fig. 8.5. The bigger but faster design is an 8 -bit look ahead adder shown in Fig. 8 .6 . Both of these netlists implement the same function, an 8 -bit adder. The ripple carry adder takes less cells to implement but is a slower design because it has more logic levels. The loo­ kahead adder takes more cells to implement but is a faster design because more of the Bool­ ean operations are calculated in parallel. The additional logic to calculate the functionality in parallel adds extra logic to the design making the design bigger. In most synthesis tools, the designer has control over which type of adder is selected through the use of constraints. If the designer wants to constrain the design to a very small area and doesn’t need the fastest possible speed, then the ripple carry adder probably works. If the designer wants the design to be as fast as possible and doesn’t care as much about how big the design gets, then the lookahead adder is the one to select. The mapping process takes as

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Fig. 8.5 Smaller but slower 8-bil ripple carry adder.

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input tíie optimized Boolean description, the technology library, and the user constraints, and generates an optimized netlist built entirely from cells m the technology library. During the mapping process, cells are inserted that implement ứie Boolean function from the optimized Boolean description. These cells are then locally optimized to meet speed and area require­ ments. As a final step, the synthesis tool has to make sure that the output does not violate any of the rules of the technology being used to implement the design, such as the maximum num­ ber of fanouts a particular cell can have.

8^ CONSTRAINTS Constraints are used to control the output of the optimization and mapping process. They pro­ vide goals that the optimization and mapping processes try to meet and control tíie structural implementation of the design. They represent part of the physical environment that the design has to interface with. The constraints available in synthesis tools today include area, timing, power, and testability constoaints. A block diagram of a design with some possible consttaints is shown in Fig. 8.7. Again, the design is shown using the cloud notation. The combinational logic between registers is represented as clouds, with wires going in and out representing the mterconnection to the registers. There are a number of consữaints shown on the diagram including required time constramts, late arrival consframts, and clock cycle consteaints. Required time consttaints specify the latest time that a signal can occur. Clock constraints are used to specify the operatmg frequency of the clock. From the clock consữaint, required time consteamts of each signal feedmg a clocked register can be calculated. Each of these constraints is further described m the next sections.

Delay Constraint Register

Register ^^ax_delay 5

Data in

Data out

/ Combinational ) I Logic ^

J

CLK

CLK

Area= 100 Clock

clock 0

10 10

V Clock Consfraint

Area Constraint

Fig. 8.7 Constraints in synthesis process.

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8.4.1 Timing Constraints Typical uses for timing constraints are to specify maximum delays for particular paUis in a design. For instance, a typical timing consfraint is the requừed time for an oulput port. The timing constoaint guides the optimization and mapping to produce a netlist ứiat meets the tim­ ing constraint. Meeting timing is usually one of the most difficult tasks when designing an ASIC or FPGA using synthesis tools. There may be no design that meets tìie timing con­ straints specified. A typical delay constoaint format is shown here: seLattribute -port data_out -name requiredjime -value 25

This constt-aint specifies that the maximum delay for signal data_out should be less than or equal to 25 library units. A library unit can be whatever the library designer used when describ­ ing the technology from a synthesis point of view. Typically, it is nanoseconds, but can be picoseconds or some other time measxxrement depending on the technology. 8.4.2 Clock Constraints One method to consữain a design is to add a requked time constraint to every flip-flop input with the value of a clock cycle. The resulting design would be optimized to meet the one clock cycle timing constraint. An easier method, however, is to add a clock constraint to the design. A clock consừaint effectively adds an input required time constoaint to every flip-flop data input. An example clock constraint is shown here: seLattribute -port elk -name clock_cycle -value 25

This example sets a clock cycle constraint on port elk with a value of 25 library units. Some synthesis tools do a static timing analysis to calculate the delay for each of the nodes in the design. The static timing analyzer uses a timing model for each element connected in the netlist. The timing analyzer calculates the worst and best case timing for each node by adding the contribution of each cell that it traverses. The circuit is checked to see if all delay constraints have been met. If so, the optimization and mapping process is done; otherwise, alternate optimization strategies may be applied—such as adding more parallel­ ism or more buffered outputs to the slow paths—and the timing analysis is executed again. More detail about the typical timing analysis is discussed later in the section “Technology Libraries.” 8.4.3 Attributes Attributes are used to specify the design envữonment. For instance, attributes specify the load­ ing that output devices have to drive, the drive capability of devices drivmg the design, and tim­ ing of input signals. All of this information is taken into accoxmt by the static timing analyzer

VHDI M odpllinnofO in italSvitpm s

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Data2

Clock Fig. 8.8 Attributes in synthesis process.

to calculate the timmg through the cừcuit paths. A cloud diagram showing attributes is shown in Fig. 8 .8 .

SAA Load Each output can specify a drive capability that determines how many loads can be driven within a particular time. Each input can have a load value specified that determines how much it will slow a particular driver. Signals that are aưiving later than the clock can have an attribute that specifies this fact. The load attribute specifies how much capacitive load exists on a particular output signal. This load value is specified in the units of the technol­ ogy library in terms of pico-farads, or standard loads, and so on. For instance, the timing analyzer calculates a long delay for a weak driver and a large capacitive load, and a short delay for a strong driver and a small load. An example of a load specification format is shown here; seLattribute -port xbus -name inputjoad -value 5

This attribute specifies that signal xbus will load the driver of this signal with 5 library units of load. 8.4.5 Drive The Drive attribute specifies the resistance of the driver, which controls how much cuưent it can source. This attnbute also is specified in the units of the technology library. The larger a driver is the faster a particular path will be, but a larger driver takes more area, so the designer

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needs to ưade off speed and area for the best possible implementation. An example of a drive specification format is shown here: seLattribute -port ybus -name outpuLdrive -value Z.7 This attribute specifies that signal yb u s has 2.7 library units o f drive Cỉụability.

8.4.6 Arrival Time Some synthesis tools use a static timing analyzer during the synthesis process to check that the logic being created matches the timing constraints the user has specified. Setting the arrival time on a particular node specifies to the static timing analyzer when a particular signal will occur at a node. This is especially important for late arriving signals. Late arriving signals drive inputs to the cuưent block at a later time, but the results of the cuưent block still must meet its own timing constraints on its outputs. Therefore, the path to the output of the late amving input must be faster than any other inputs, or the timing constraints of the ciurent block cannot be met. 8.5 TECHNOLOGY LIBRARIES Technology libraries hold all of the information necessary for a synthesis tool to create a netlist for a design based on the desired logical behaviour, and constraints on the design. Technology libraries contain all of the information that allows the synthesis process to make the coưect choices to build a design. Technology libraries contain not only the logical func­ tion of an ASIC cell, but the area of the cell, the input to output timing of the cell, any constraints on fanout of the cell, and the timing checks that are required for the cell. Other information stored in the technology library may be the graphical symbol of the cell for use in schematics. Following is an example technology library description of a 2-input AND gate written in Synopsys .lib format: library (xyz) { cell (and2) { area ; 5; pin (a1,a2){ direction: input; capacitance: 1; } pin (o1) { direction; output; function: “a1 * a2”; timing 0 {

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intrinsic_rise: 0.37; intnnsic.fall: 0.56; rise.resistance: 0.1234; falLresistance: 0.4567; relatedjiin : “a1 a2"; } 1 } }

This technology library describes a library named xyz witii one library cell contamed in it The cell is named and2 and has two input pins al and a2 and one output pin ol. The cell reqmres 5 units of area, and ứie input pins have 1 unit of loading capacitance to the driver driv­ ing them. The intrinsic rise and fall delays listed wiứi pin ol specify the delay to the output with no loading. The timing analyzer uses ứie intrinsic delays plus the rise and fall resistance with the output loading to calculate tìie delay through a particular gate. Notice that ứie function of pin ol is listed as tìie AND of pins al and a2. Also, notice that pm ol is related to pins al and a2 in tìiat the timing delay ứirough the device is calculated from pins al and a2 to pin ol. Most synứiesis tools have fairly complicated delay models to calculate timing through an ASIC cell. These models include not only mttinsic rise and fall time, but output loading, input slope delay, and estimated wừe delay. A diagram illustrating this is shown in Fig. 8 .8 . The total delay from gate A1 to gate Cl is: intrinsic_delay + loading_delay + wire_delay + slope_delay

The intrinsic delay is the delay of the gate without any loading. The loading delay is the delay due to tìie input capacitance of ứie gate being driven. The wữe delay is an estimated delay used to model the delay through a typical wire used to connect cells together. It can be a statistical model of the wữe delays usually based on the size of the chip die. Given a particu­ lar die size, tìie wire loading effect can be calculated and added to the overall delay. The final component in the delay equation is the extra delay needed to handle the case of slowly rising input signals due to heavy loading or light drive. Delay Effects Used in Delay Model In the preceding technology library, the inữinsic delays are given in the cell description. The loading delay is calculated based on ứie load applied to ứie output pin ol and the resistance values in the cell description. The value calculated for the wire delay depends on the die size selected by the user. Selecting a wire model scales the delay values. Finally, the input slope delay is calculated by the size of the driver, in this example, Al, and the capacitance of the gate being driven. The capacitance of the gate being driven is in the technology library description. Tech­ nology libraries can also contain data about how to scale delay information with respect to process parameters and operating conditions. Operating conditions are the device operating temperature and power supply voltage applied to the device.

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Delay

Wire Delay

Fig. 8.9 Delay effects in synthesis process.

8.6 VHDL AND LOGIC SYNTHESIS The goal of the VHDL synthesis step is to create a design that implements ứie lequữed fimctionality and matches ứie designer’s constoaints in speed, area, or power. The VHDL synthesis tools convert ứie VHDL description into a netlist in the target FPGA or ASIC technology. For ứie VHDL synứiesis tool to perform ữiis step properly, the VHDL code must be written in a pailicular style.

^ Explain the stepwise execution of logic synthesis and various reports generated To synthesize a VHDL description, the designer reads the verified VHDL descrip­ tion mto the VHDL synthesis tool in the same way that the designer read the design into the VHDL simulator. The VHDL synthesis tool reports syntax eưors and synthesis eưors. Synthesis eưors usually result from the designer using constructs that are not synthesizable. Syntax eưors result from improper VHDL syntax being read by the VHDL synứiesis tool. Presumably, most all of these eưors will aừeady have been taken care of because tìie VHDL code has already been verified with the VHDL simulator. The VHDL synthesis tool also rq>orts warnings of constructs that have ứie pos­ sibility of generating mismatches between the RTL simulation results and the ou^ut netlist simulation results. The designer reads the VHDL design into the VHDL syntíiesis tool. If there are no syntax eưors, the designer can synthesize the design and map the design to the target technology.

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the designer had to make changes to tìie VHDL description, then the VHDL description needs to be simulated again and the output validated for coưectness. Fkst, the designer needs to make sure that the synthesizer is producing an output in the target technology (FPGA or standard cells) that looks reasonable. The designer looks at the synthesizer output to determine whether or not the synthesizer produced a good result. The synthesizer produces an output netlist in the target technology and a number of report files. By looking at the netlist, the designer can determine whether or not the design looks reasonable. For most reasonable size designs, however, it can be very difficult to determine how well the synthesizer implemented the function. The designer looks at tìie report files to determine the quality of the sjTithesis output. The most conunon output files are the timing report and the area report. Most synthesis tools produce a number of other reports such as hierarchy reports, instance reports, net reports, power reports, and others. The most useful reports initially are the timing and area reports, because these are usually the most critical factors. If

8.6.1 Area Report

Cell; adder

Library; wort

View: test

' Total accumulated area: Number of L C S : Number of CARRYs:

B 7

•

24 107 91 0

Number of ports: Number of nets: Number of instances; Number of references to this view : Cell

Library

References

GND OUTBUP INBUF CARRY 0R2 AND2 LCELL X0R2

flexio flexio flexio flexio flexio flexio flexio flexio

1 X 8 X

16 1 14 21

X

X X X

8 X

16 X

Total 1 1 1 1 1 1 1

Í

1 8 16 7 14 21 9 16

Area GND OUTBUP INBUF CAREYS 0R2 AND2 LCS K0R2

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1. The area report tells the designer the size of die implemented design. 2. The units of measure are detennined by the units used when die syndiesis libraiy was implemented. 3. The area report shows the designer how much of ttie resources of tiie chip the design has consumed. 4. The designer can tell if the design is too big for a particuiar chip and ứie designer needs to target a larger chip, if the design should go into a smaller chip, or ư*the current chip will work fine. The designer can also get a relative size of tìie design to use in iater stages of the design process.

8.6.2 Timing Report The timing report shows the timing of critical paths or specified paứis of the design. The designer examines the timing of the critical paths closely because these paths ulti­ mately determine how fast the design can ran. If the longest path is a timing critical part of the design and is not meeting the speed requirements of the designer, then tíie designer may have to modify the VHDL code or tty new timing constraints to make the path meet timing. The following is a sample timmg report: Critical path #1, (unconstrained path) NAME GATE ARRIVAL LOAD a(0)/0.00up 0.00 up

0.00

AND22.40

up

0.00

0R2 2.40

up

0.00

modgen 0 11 10 10 0 10 c5/Y

0R2 2.40 CARRY 2.90

up up

0.00

modgen 0 11 10 10 1 10 c1/Y

AND22.90

up

0.00

modgen 0 11 10 10 1 10 c3/Y

0R2 2.90

up

0.00

modgen 0 11 10 10 1 10 c4/Y

up

0.00

modgen 0 11 10 10 1 10 c5/Y modgen 0 11 10 10 2 10 c2/Y modgen_OJ1_IO_IO_2_IO_c4A'

0R2 2.90 CARRY 3.40

up

0.00

AND23.40

up

0.00

0R2 3.40

up

0.00

modgen 0 11 10 10 2 10 c5/Y

CARRY 3.90

up

0.00

modgen 0 11 10 10 3 10 c l/Y modgen_0_l 1JO _IO_3JO_c3/Y 1

AND23.90

up

0.00

0R2 3.90

up

0.00

modgen 0 11 10 10 3 10 c4/Y modgen_OJ1_IO_IO_3_IO_c5/Y

0R2 3.90

up

CARRY 4.40

up

modgen 0 11 10 10 4 10 c1/Y

AND24.40

up

0.00 0.00 0.00

modgen 0 11 10 10 4 10 c3/Y

0R2 4.40

up

0.00

ixSO/OUT m od gen_ 0 _l1 J0J0 _ 0J0 _c1/Y modgen 0 11 10 10 0 10 c3/Y m odgen_0_l1_l0J0_0_l0_c4/Y

INBUF 2.40

0.00

VHDL Modelling of Digital Systems m odgen_OJ1JOJO_4_IO_c4/Y

0R2 4.40

up

0.00

m o d o e n _ O J1JO JO _ 4 JO _ c5 /Y

CARRY 4.9Đ

up

0.00

AND24.90

up

0.00

m odgen_OJ1JO_IO_5JO_c3/Y

0R2 4.90

up

0.00

m ođgen_OJ1JO_IO_5JO_c4A'

0R2 4.90

up

0.00

modgen_OJ1JOJO_5_IO_c5/Y

CARRY 5.40

up

0.00

m odgen_OJ1JO_IO_6JO_c1/Y

AND25.40

up

0.00

m odgen_OJ1JOJO_6_IO_c3/Y

0R2 5.40

up

0.00

m odgen_OJ1JO_IO_6JO_c4/Y

0R2 5.40

up

0.00

modgen_OJ1JOJO_6_IO_c5/Y

CARRY 5.90

up

0.00

m o dgen _O J1JO JO_ 7JO _su m O /Y X

0R2 5.90

up

0.00

m odgen_OJ1JOJO_7_IO_sum 1/Y X

0R25.90

up

0.00

m odgen_OJ1JD_IO_7JO_sum 2/Y

L C E L L 10.00

up

0.00

ÌX39/0UT

OUTBUF13.80

up

0.00

up

0.00

m o d g e n _ O J1JO JO _ 5 JO _ c 1/Y

c(7)/13.80

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data arrival time 13.80

In this report, the worst-case path is listed shown with estimated time values for each node traversed in the design. The timmg analyzer calculates the tune for a path from an input pin to a flip-flop or output, or from a flip-flop output to a flip-flop input, or output pin. The designer has tíie ability to ask for the timing for particular paths of interest, or of the paths that have the longest timmg value, and how many to display. As mentioned previously, the worst-case paths ultimately determine the speed of the design. For instance, in this case, the worst-case path is 13.8 nanoseconds; therefore, the fastest this design would be able to run is about 72 MHz. The last type of output data that the designer can examine is the netlist for the design in the target technology. This output is a gate or macro-level output in a format compatible with the place and route tools that are used to implement the design m the target chip. When the netlist meets the designer’s tuning, area, power, and other constraints, the next step is to pass the netlist to the gate level simulator. This simulator checks the functionality of the synthesized design. 8.7 FUNCTIONAL 6ATE-LEVEL VERIFICATION Some designers might want to do a quick check on the output of the synthesis tool to make sure tiiat the synthesis tool produced a design that is functionally coưect. If proper design rules are followed for the input VHDL description, the synthesis tool should never generate an ou^ut that is fiznctionally different from the RTL VHDL input, unless the tool has a bug. However, if some of the warnings or eưors are ignored or some part of the design is written using a strange VHDL style, the synthesizer can produce an output netlist that does not exactly match the RTL mput in terms of functionality. Most designers like to run a quick check on the results of the synthesis tool to make sure the synthesis tool produced a functionally coưect output. To do this, the designer runs a functional gate-level verification. The designer reads

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the output VHDL netlist from tìie synthesis tool plus a library of the synứiesis jHimitives into the VHDL simulator and runs the simulation usmg ứie RTL verification vectors. If the design matches, then the synthesis tool did not produce logic mismatches; if it does not match, the designer needs to debug the VHDL RTL description to see what is wrong. The most common method for performing this step is to run a VITAL simulation of the netlist from the synthesis tool. For a completely functional sũnulation, no timing is back-annotated. If the synthesis tool supports estimated timing and SDF file generation, the synthesis tool could write the VHDL netlist and an SDF timing file for the design. The designer could use these two files to run a VITAL simulation with estimated timing. After the design has been functionally verified, it is passed to the place and route tools to implement the design. 8.8 PLACE AND ROUTE Place and route tools are used to take the design netlist and implement tíie design in the tar­ get technology device. The place and route tools place each primitive from ứie netlist into an appropriate location on the target device and then route signals between the primitives to connect the devices according to the netlist. Place and route tools are typically very architec­ ture and device dependent. These tools are tuned to take advantage of each architectural and routing advantage the device contains. FPGA vendors provide these tools because the differ­ ences in architectures are large enough that writing a common tool for all architectures would be very difficult. Place and route tools for ASIC devices can be obtained from the ASIC ven­ dor or EDA (Electronic Design Automation) vendors. ASIC architectures do not have as wide a variation between architectures as FPGA architectures and, therefore, place and route tools exist that can handle lots of different ASIC architectures. Inputs to the place and route tools are the netlist in EDIF or another netlist format, and possibly timing constraints. The format of the netlist input file varies from manufacturer to manufacturer. Some tools use EDIF; others use proprietary formats such as XNF. Another input to some place and route tools is the timing constraints, which give the place and route tools an indication about which signals have critical timing associated with them and to route these nets in the most timing efficient manner. These nets are typically identified during the static timing analysis process during synthesis. These consữaints tell the place and route tool to place the primitives in close proximity to one another and to use the fastest routing. The closer the cells are, the shorter the routed signals will be and the shorter the time delay. Some place and route tools allow the designer to specify the placement of large parts of the design. This process is also known as floor planning. Floor planning allows the user to pick locations on the chip for large blocks of the design so that routing wires are as short as possible. The designer lays out blocks on the chip as general areas. The floor planner feeds this informatioQ to the place and route tools so that these blocks are placed properly. After the cells are placed, the router makes the appropriate connections. After all the cells are placed and routed, the output of the place and route tools consists of data files that can be used to implement the chip. In the case of FPGAs, these files describe all of the connections needed to make the FPGA macrocells implement the functionality requữed.

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Fig. 8.10 Dataflow diagram of the place and route tools.

Antifuse FPGAs use this infoiroation to biUTi the appropriate fuses, while reprogrammable devices download this information to the device to turn on the appropriate transistor connec­ tions. The other output from the place and route software is a file used to generate the timing file. This file describes the actual timing of the programmed FPGA device or the final ASIC device. This timing file, as much as possible, describes the timing exttacted from the device when it is plugged into the system for testing. The most common format of this file for most simulators is SDF (Standard Delay Format). Sometimes, proprietary formats are generated and later translated to SDF. SDF is used to back-annotate the post route timing information from place and route tools into the post layout timing simulation. 8.9 POST LAYOUT TIMING SIMULATION After the place and route process has completed, the designer will want to verify the results of the place and route process. There are a niunber of methods to accomplish this task but the most common is to use post route gate-level simulation. This simulation combines the netlist used for place and route with the timing file from the place and route process into a simula­ tion that checks both functionality and timing of the design. The designer can run the simula­ tion and generate accurate output waveforms that show whether or not the device is operating properly and if the timing is being met. If the design has been properly structured, the same test vectors used for the RTL simulation can be used for the post route gate-level simulation. In this way, the designer is saved the process of generating a new set of vectors to check the

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gate-level design and verifying the new vector ou^ut values. Post route gate-level sŨQulatiaiV' if done properly, also uses the same simulator as the RTL simuiation. For VHDL sitnulatiom^ this requires a VITAL-compliant (standard way of describing designs with designs diat aUovr SDF timing back-aimotation) VHDL simulator. VHDL simulators ứiat are not VITAL-compliaat do not accelerate the execution of the gate-level primitives and cannot accept SDF to badE annotate the timing. 8.10 STATIC TIMING For designs of 10,000 gates to 100,000 gates, post route timing simulation can be a good method of verifying design functionality and timing. However, as designs get larger, or if the designer does not have test vectors, the designer can use static timing analysis to make sure the design meets the timing requirements. A static timing analyzer ưaces each path in the design and keeps track of the timing from a clock edge or an input. A timing report is then generated in a number of formats. For instance, the designer can ask for all paths and get an enormous listing of every path in the design. A more intelligent method, however, is to ask for the most timing critical paths in the design and make sure the timing constraints have been met. Typical static timing analyzers have a number of report types that can be generated so that the designer can make sure the critical paths of the design can be found and verified to be within the required specifications. If paths are not within the specifica­ tions, the static timing analyzer shows the entire path so that the designer can try to fix the problem. 8.11 MAJOR NETLIST FORMATS FOR DESIGN REPRESENTATION Logically, the design of a VLSI chip can be completely represented by its netlist. The major formats used for netlisting are: • • • • •

Verilog VHDL EDIF DEF SPICE

Any of these formats can be used to precisely describe the cells instantiated in the design and the interconnections among those cells. Among those, Verilog is the most popular one. Duringproject execution, especially for a large SoC project, many tools from different EDA vendors will be used to achieve individual design objectives at specific design stages. Between stages and tools, a Verilog netlist is commonly used for transfemng the design information. In the past, it has been exừemely difficult to transport a design from one EDA tool to another tool from a different EDA vendor since each company has its own approach to netlisting design. Nowadays, companies seem to standardize theữ approaches around Verilog.

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1.12 VHDL SYNTHESiS-PROCRAMMINfi APPROACH Most logic synthesizers insist we follow a set of rules when we use a logic system to ensure iỉiat what we synthesize matches the behavioural description. Here is a typical set of rules for use with the IEEE VHDL nine-value system: • You can use logic values coưesponding to states ‘r , ‘H’, ‘0’,and ‘Ư in any manner. • Some synthesis tools do not accept the uninitialized logic state ‘U’. • You can use logic states ‘Z’, ‘X’, ‘W’,and in signal and variable assignments in any manner. ‘Z’ is synthesized to three-state logic. • The states ‘X’, ‘W’, and are treated as unknown or don’t care values. The values ‘Z’, ‘X’, ‘W’, and may be used in conditional clauses such as the comparison in an if or case statement. However, some synthesis tools will ignore them and only match suưounding ‘1’ and ‘0’ bits. Consequently, a synthesized design may behave differently from the simulation if a stimulus uses ‘Z’, ‘X’, ‘W’ or The IEEE synthesis packages provide the STD_MATCH fiinction for comparisons. 8.12.1 Initialization and Reset You can use a VHDL process with a sensitivity list to synthesize clocked logic with a reset, as in the following code: process (signalj, signal_2) " begin if {signal_2’EVENT and signal_2 = ‘0’) then - Insert initialization and reset statements, elsif (sig n alJ’EVENT and s ig n a lj = 1 ’) then - Insert clocking statements, end i f ; end process;

Using a specific pattern the synthesizer can infer that you are implying a positive-edge clock (signal l) and a negative-edge reset (signal_2). In order to be able to recognize sequen­ tial logic in this way, most synthesizers restrict you to using a maximiun of two edges in a sensitivity list. 8.12.2 Combinational Logic Synthesis in VHDL In VHDL a ievel-sensitìve process is a process statement that has a sensitivity list with sig­ nals that are not tested for event attributes (‘EVENT or ‘STABLE, for example) within the process. To synthesize combinational logic we use a VHDL level-sensitive process or a con­ current assignment statement. Some synthesizers do not allow reference to a signal inside a

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level-sensitive process unless that signal is in ^ missing from the sensitivity list:

ãeasiârity list In this exanq>le, ágoal b H;;

entity And_Bad is port (a, b; in BIT; c; out BIT); end And_Bad; architecture Synthesis_Bad of And.Bad is begin process (a) -- this should be process (a, b) begin c <=a and b; end process; end Synthesis_Bad;

This situation is similar but not exactly the same as omitting a variable from an event confrol in a Verilog always statement. Some logic synthesizers accept the VHDL version of Aild Bad but not the Verilog version or vice versa. To ensure that the VHDL simulation will match tìie behaviour of the synthesized logic, the logic synthesizer usually checks the sensitivity list of a level-sensitive process and issues a warning if signals seem to be missing. 8.123 Multiplexers ỉn VHDL Multiplexers can be synthesized using a case statement (avoiding the VHDL reserved word ‘select’ ), as the following example illustrates: entity Mux4 is port (i: BIT_VECT0R(3 downto 0): sel; BIT_VECT0R(1 downto 0); s; out BIT); end Mux4; architecture SynthesisJ of Mux4 is begin process (sel, i) begin case sel is when “00” => s <= i(0): when “01” => s <= i(1): when “10” => s <= i(2); when “11” => s <= i(3): end case; end process; end SynthesisJ;

The following code, using a concuưent signal assignment is equivalent: architecture Synthesis_2 of Mux4 is begin with sel select s <=i(0) when “00”, i(l) when “01”, i(2) when “10”, i(3) when “11”; end Synthesis_2;

In VHDL the case statement must be exhaustive in either form, so there is no question of any priority in the choices as there may be in Verilog.

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For larger MUXes we can use an anay, as in the following example: library IEEE; use ieee.std_logic_1164. all : nitity Mux8 is port [InBus: In STD_L0GIC_VECT0R(7 downto 0): Sel: in INTEGER range 0 to 7; DutBit: out STD.LOGIC): end Mux8; architecture SynthesisJ of Mux8 is begin process (InBus, Sel) begin OutBit <= InBus(Sel); end process; end SynthesisJ:

Most synthesis tools can infer that, in this case, Sel requữes three bits. If not, you have to declare the signal as a STD_LOGIC_VECTOR, Sel: in STD_L0GIC_VECT0R{2 downto 0): and use a conversion routine from the STDJNUMERIC package like this: OutBit <= lnBus(TO_INTEGER { UNSIGNED (Sel)) ) :

At some point you have to convert from an INTEGER to BIT logic anyway, since you cannot connect an E^TEGER to the input of a chip! The VHDL case if and select statements produce similar results. Assigning don’t care bits (‘X’) in these statements will make it easier for the synthesizer to optimize the logic. 8.124 Decoders in VHDL The following code implies a decoder: library IEEE; use IEEE.STD_L06ICJ164. a l l ; use lEEE.NUMERIC.STD. a l l ; entity Decoder is port (enable; in BIT; Din: STD_LOGIC_VECTOR (2 downto 0); Dout: out STD_LOGIC_VECTOR (7 downto 0)): end Decoder; architecture Synthesis_1 of Decoder is with enable sele ct Dout <= STD_LOGIC_VECTOR (UNSIGNED’ (shiftjeft (“00000001”, TOJNTEGER (UNSIGNED(Din))

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) ) ) W hen r ,

“11111111” when ‘O’, “00000000” when others: end SynthesisJ:

There are reasons for this seemingly complex code: • Line 1 declares the IEEE library. The synthesizer does not parse the VHDL code inside the library packages, but the synthesis company should be able to guarantee that .the logic will behave exactly the same way as a simulation that uses the IEEE iibraries and does parse the code. • Lme 2 declares the STD_LOGIC_1164 package, for STD LOGIC types, and Uie NUMERIC_STD package for conversion and shift functions. The shift operators (sll and so on-the infix operators) were introduced in VHDL-93, they are not defined for STD LOGIC types in the 1164 standard. The shift Junctions defined m NUMERIC_ STD are not operators and are called shift left and so on. Some syntìiesis tools support NUMERIC_STD,but not VHDL-93. • Line 10 performs a type conversion to STD_LOGIC_VECTOR from UNSIGNED. • Line 11 is a type qualification to tell the software that tiie argument to ứie type conver­ sion function is type UNSIGNED. • Line 12 is the shift function, shift_left,from the NUMERIC STD package. • Line 13 converts the STD_LOGIC_VECTOR, Djn, to UNSIGNED before converting to INTEGER. We cannot convert directly from STD LOGIC VECTOR to INTEGER. • The others clause in line 18 is requừed by the logic syndiesizer even ứiough type BIT may only be ‘0 ’ or ‘r . If we model a decoder using a process, we can use a case statement inside the prcicess. A MUX model may be used as a decoder if the input bits are set at ‘1’ (active-high decoder) or at ‘0 ’ (active-low decoder), as in the following example: library IEEE; use lEEE.NUMERIC.STD. a l l : use IEEE.STD_L0GIC_1164. a l l : entity ConcurrenLDecoder is port ( enable: in BIT; Din : in STD_LOGIC_VECTOR (2 downto 0); Dout; out STD_LOGIC_VECTOR (7 downto 0)); end ConcurrenLDecoder; architecture SynthesisJ of ConcurrenLDecoder is begin process (Din, enable) variable T : STD_L0GiC_VECT0R(7 downto 0): begin

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n (enable =‘1’) then T := “00000000”; T( TOJNTEGER (UNSIGNED(Din))) := 1 ’: Dout<=T; else Dout <={ others =>T): ■Rdif; end process: end SynthesisJ;

Notice that T must be a variable for proper timing of the update to the output. The else clause in the if statement is necessaiy to avoid infemng latches. 8.12.5 Adders in VHDL To add two «-bit numbers and keep the overflow bit, we need to assign to a signal with more hits as follows: library IEEE; use IEEE.NUMERIC_STD. a l l : use IEEE.STD_L0GIC_1164. a l l : entily A dderJ is port (A, B: in UNSIGNED(3 downto 0); C; out UNSIGNED(4 downto 0)); endAdderJ: architecture SynthesisJ of AdderJ is begin c <=(‘0’ & A) + (‘0’ & B): end SynthesisJ:

Notice that both A and B have to be SIGNED or UNSIGNED as we cannot add STD_ LOGIC VECTOR types directly using the IEEE packages. You will get an eưor if a result is a different length from the target of an assignment, as in the following example (in which the arguments are not resized): adder l : begin c <= A + B; Error: Width mis-match: right expression is 4 bits wide, c is 5 bits wide The following code may generate three adders stacked three deep: z <= a + b + c + d; Depending on how the expression is parsed, the first adder may perform X = a + b, a second adder y = X + c, and a third adder z = y + d. The following code should generate faster logic with three adders stacked only two deep: z <= (a + b) + (c + d);

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8.12.6 Sequential Logic in VHDL Sensitivity to an edge implies sequential logic in VHDL. A synthesis tool can locate edges is VHDL by finding a process statement that has either: • no sensitivity list with a wait \mtil statement • a sensitivity list and test for 'EVENT plus a specific level. Any signal assigned in an edge-sensitive process statement should also be reset—but be careful to distinguish between asynchronous and synchronous resets. The following exanq>le illustrates these points: library IEEE; use IEEE.STD_L0GIC_1164. a l l : entity DFF_With_Reset is port (D. Clk, Reset; in STD.LOGIC; Q ; out STD.LOGIC); end DFF_With_Reset; architecture Synthesis_1 of DFF_With_Reset is begin process (Clk, Reset) begin if (Reset = ‘0’) then Q <= ‘O’; - asynchronous reset e lsif rising_edge(Clk) then Q <= D; end i f ; end process; end Synthesis_l; architecture Synthesis_2 of DFF_With_Reset is begin process begin w ait until rising_edge(Clk); -- This reset is gated with the clock and is synchronous: if (Reset = ‘0’) then Q <= ‘O’; e lse Q <= D; end i f ; end process; end Synthesis_2;

Sequential logic results when we have to “remember” something between successive exe­ cutions of a process statement. This occurs when a process statement contains one or more of the following situations: • • • •

A signal is read but is not m thesensitivity list of a process statement. A signal or variable is read before it isupdated. A signal is not always updated. There are multiple wait statements.

Not all of the models that we could write using the above constructs will be syntfiesizable. Any models that do use one or more of these constructs and that are synthesizable will result in sequential logic.

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M 2.7 Shift Registeis and doddng in VHDL ^Bie following code implies a serial-in/parallel-out (SIPO) shift register: library IEEE; Hse IEEE.STD_L0GIC_1164. a ll: use IEEE.NUMERIC_STD. a ll: entity SIPOJ is port ( Clk:riiSTD_LOGIC: S I: In STD_LOGIC; -- serial in po: buffer STD_L0GIC_VECT0R(3 downto 0)); - parallel out endSIPOJ; architecture SynthesisJ of SIPOJ is begin process (Clk) begin if (Clk =1’ ) then PO <=SI & P0(3 downto 1); end i f ; end process; end SynthesisJ;

The syntiiesized design consists of four flip-flops. Notice that (line 6 in the VHDL input) sig­ nal PO is of mode buffer because we cannot read a signal of mode out ủỉside a process. This is acceptable for synthesis but not usually a good idea for sũnulation models. We can modify the code to eUminate the buffer port and at the same time we shall include a reset signal, as follows: library IEEE; use IEEE.STD_L0GICJ164. a l l : use lEEE.NUMERIC.STD. a i l : entity SIPO.R is port ( elk; in STD_LOGIC ; re s : in STD.LOGIC ; SI: in STD.LOGIC : PO : out STD_L0GIC_VECT0R(3 downto 0)); end; architecture Synthesis_1 of SIPO_R is signal P O J : STD_L0GIC_VECT0R(3 downto 0): begin process (POJ) begin PO <= POJ: end process; process (elk, res) begin If (res =‘0’) then POJ <= ( others =>‘0’): elsr! (rising_edge(clk)) then POJ <= SI & P0J(3 downto 1): end i f ; end process; end SynthesisJ:

Notice the following; • Line 10 uses a temporary signal, PO_t, to avoid using a port of mode buffer for the out­ put signal PO. We could have used a variable instead of a signal and the variable would

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consume less overhead during simulation. However, we must complete an assignment fQi a variable inside the clocked process (not m a separate process as we can for the signaQ. Assignment between ã variable and a signal inside a single jnx>cess creates its own set of problems. • Line 11 is sensitive to the clock, elk, and the reset, res. It is not sensitive to PO_t or SI and this is what indicates the sequential logic. • Line 13 uses the rising edge function from the STD_LOGIC_1164 package. • The software synthesizes four positive-edge-4riggered D flip-flops for design entity SIPO_R(Synthesis_l) as it did for design entity SIPO_l(Syiilliesis_l).The diffoence is that the synthesized flip-flops in SIPO_R have active-low resets. However, ứie simulatiffli behaviour of these two design entities will be difiFerent. In SIPO_R, the function risiiig_ edge only evaluates to TRUE for a ừansition from ‘0’ or ‘L’ to ‘1’ or ‘H’. In SEP0_1 we only tested for Clk = ‘1’.Since nearly all synthesis tools now accept iismg_edge and falling_edge, it is probably wiser to use these fimctions consistently. 8.12.8 Adders and Arithmetic Functions If you wish to perform BIT VECTOR or STD LOGIC VECTOR arithmetic you have three choices: • Use a vendor-supplied package (there are no standard vendor packages—even if a com­ pany puts its own package in the IEEE library). • Convert to SIGNED (or UNSIGNED) and use the IEEE standard synthesis packages (IEEE std 1076.3-1997). • Use overloaded functions in packages or iiinctions that you define yourself. Here is an example of addition using a ripple-carry architecture: library IEEE; use IEEE.STD_L0GICJ164. a l l ; use IEEE.NUMERIC_STD. a l l : entity Adder4 is port ( in1, in2 : in BIT_VECT0R(3 downto 0): mySum ; out BIT_VECT0R(3 downto 0) ) : end Adder4; architecture 6ehave_A of Adder4 is function DIY(L,R. BIT_VECT0R(3 downto 0)) return BIT_VECTOR is variable sum;BIT_VECT0R(3 downto 0); variable It,rt,St,cry: BIT; begin cry :=‘O’: for i in L’REVERSE_RANGE loop It ;= L(i); rt := R(i); St := It xor rt; sum(i):= St x o r cry; cry:= (It an d It) o r (st an d cry);

end loop;

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feturn sum; end: begin mySum <= DIY (in1, in2): -- do it yourself (DIY) add end BehavạJ\;

This model results in random logic. An alternative is to use UNSIGNED or UNSIGNED from the IEEE NUMERIC_STD or NUMERIC_BIT packages as in the foUowing example: lỉb ra iy IEEE; use IEEE.STD_L0GIC_1164. a ll: use IEEE.NUMERIC_STD. a ll: entity Adder4 is port ( in1, in 2 ; in UNSIGNED^ downto 0); mySum; out UNSIGNED(3 downto 0 ) ) ; end Adder4; architecture Behave.B of Adder4 is begin mySum <= ini + in2; -- This uses an overloaded V . end Behave.B;

In tíũs case, the synthesized logic will depend on the logic synthesizer.

8.12.9 Adder/Subtracter and Don't Cares The following code models a 16-bit sequential adder and subừacter. The input signal, xin, is added to output signal, result, when signal addsub is high; otherwise result is subữãcted from xin. The internal signal addout temporarily stores the result until the next rising edge of the dock: library IEEE; use IEEE.STD_L0GICJ164. a l l ; use lEEE.NUMERIC.STD. a l l : entity Adder_Subtracter is port ( x in : in UNSI6NED(15 downto 0): elk, addsub, cir; in STD_LOGIC; result: out UNSIGNED(15 downto 0)): end Adder_Subtracter; architecture Behave_A of Adder_Subtracter is signal addout, resultj: UNSIGNED(15 downto 0): begin result <= resultJ: with addsub select addout <= (xin + resultj) when ‘1’, (xin - resultj) when ‘O’,

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VLSI Design

( Others => when others; process (cir, elk) begin if (clr = ‘0’) then re su ltj <= ( others => ‘0’): elsif rising_edge(clk) then re su ltj <= addout; end i f : end process : end Behave_A;

Notice the following: • Line 11 is a concurrent assignment to avoid usmg a port of mode bufier. • Lines 12-15 define an exhaustive list of choices for the selected signal assignment state­ ment. The default choice sets the result to (don’t care) to allow Ae synthesừer to optunize the logic. • Line 18 includes a reference to signal addout that could be eliminated by movmg the selected signal assignment statement inside the clocked process as follows: architecture Behave_B of Adder_Subtracter is signal resultj: UNSI6NED(15 downto 0); begin result <= re su ltj;

process (cir, elk) begin if (clr = ‘0’) then re su ltj <= ( others => ‘0’): elsif rising_edge(clk) then case addsub is when ‘1’ => re su ltj <= (xin + resultj): when ‘0’ => re su ltj <= (xin - resultj): when others => resultj <= ( others => end case ; end i f ; end process ; end Behave_B;

This code is simpler than architecture Behave_A, but ứie synthesized logic should be iden­ tical for both architectures. Since the logic that results is an adder/subfracter followed by a register (bank of flip-flops) the Behave A model more clearly reflects the hardware. 8.13 A LOfilOSYNTHESIS EXAMPLE How does logic synthesis generate smaller and faster circuits? Figure 8.11 shows the compara­ tor/MUX example. The Verilog code and theschematic in Fig.8.11describe the same func­ tion. The comparison, in Table 8.1 of the two designapproachesshows that thesynthesized version is smaller and faster than the hand design, even though the synthesized design uses more cells.

VH DL Modelling o f Digital Systems

ỵ r ' -

bp

X7

a[llb[l]

t

a[0 ]. b[0 ]-

r>

sel 5 ^outp[l]

0 >outp[ 0 ]

O '

o

2 79

II comp_mux.v module comp_mux(a, b, outp); input [2:0] a, b; output [2:0] outp; function [2:0] compare; input [2:0] ina, inb; begin If (ina <= inb) compare = ina; e lse compare = inb; end endfunction assign outp = compare(a, b); endmodulie

Fig. 8.11 Schematic and HDL design entry.

Table 8.1 Comparison of the comparator/MUX designs using a 1.0 mm standard-cell library

Hand design Synthesized

Area/mils^

Delay/ns

No. of standard cells

No. of transistors

4.3 2.9

12

116

68.68

15

66

46.43

Note: • These delays are imder nominal operating conditions with no wữmg capacitance. This is the only stage at which a comparison could be made because the hand design was not completed. • Both figures are initial layout estimates using default power-bus and signal routmg widths. With the Verilog behavioural model of Fig. 8.11 as the input, logic-synthesis software gen­ erates logic that performs ứie same function as the Verilog in Fig. 8.13. The software then opti­ mizes the logic to produce a structural model, which references logic cells from the cell library and details their connections as shown in Fig. 8.12. Before running a logic sjmthesizer, it is necessary to set up paths and startup files (synopsys dc.setup, etc). Note: The reader is expected to understand the process only in this chapter. The commands and other files are dependent on the application and beyond the scope o f this book. These files set the target library and dừectory locations. Normally, it is easier to run logic syn­ thesis in text mode usmg a script. A script is a text file that dừects a software tool to execute

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‘timescale 1 ns / 1 0 ps

module comp_mux_u (a, b, outp); input [2:0] a; input [2:0] b; output [2:0] outp; supplyl VDD; supplyO VSS; a íH alH ạlO ] inoido u2 (.l(b[1]), .ZN(u2_ZN)): nd02d0 u3 (.A1(a[1]), .A2(u2_ZN), ,ZN(u3_ZN)); inOldO u4 (j(a[1]), .ZN(u4_ZN)): nd02d0 u5 (.A1(u4_ZN). .A2(b[1]), ,ZN(u5_ZN)): inOldO u6 (.l(a[0]), .ZN(u6_ZN)): nd02d0 u7 (.A1(u6_ZN), .A2(u3_ZN), ,ZN(u7_ZN)); nd02d0 u8 (,A1 (b[01), ,A2(u3_ZN), .ZN(u8_ZN)): nd03d0 u9 (.A1(u5_ZN), .A2(u7_ZN). ,A3(u8_ZN), ,ZN(u9_ZN)): inOldO u10 (.l(a[2]), ,ZN(u10_ZN)): nd02d0 u11 (.A1(u10_ZN), ,A2(u9_ZN), .ZN(u11_ZN)); nd02d0 u12 (,A1(b[2]), ,A2(u9_ZN), ,ZN(u12_ZN)): NAND3 (nd03d0) nd02d0 u13 (.A1(u10_ZN), .A2(b[2]), .ZN(u13_ZN)): nd03d0 u14 (.A1(u11_ZN), .A2(u12_ZN), .A3(u13_ZN), ,ZN{u14_ZN)): logic cell names nd02d0 u15 (.A1(a[2]), ,A2(u14_ZN), ,ZN(u15_ZN)); inOldO u16 (.l(u14_ZN), ,ZN(u16_ZN)); IW iin O ld O ) NAND2 (ndOldO] nd02d0 u17 (,A1(b[2]), .A2(u16_ZN), ,ZN(u17_ZN)): NAND3 (nd03d0) nd02d0 u18 (.A1(u15_ZN), .A2(u17_ZN), .ZN(outp[2])): nd02d0 u19 (.A1(a[1]). ,A2(u14_ZN), .ZN(u19lzN)): nd02d0 u20 (.A1(b[1]). .A2(u16_ZN), .ZN(u20_ZN)): nd02d0 u21 (.A1(u19_ZN), .A2(u20_ZN), .ZN(outp[1])); nd02d0 u22 (.A1(a[0]), .A2(u14_ZN), .ZN(u22_ZN)); nd02d0 u23 (.A1(b[0]), ,A2(u16_ZN), .ZN(u23_ZN)): nd02d0 u24 (,A1(u22_ZN), ,A2(u23_ZN), .ZN(outp[0])); outp[l]outp[2] Oirtp[0] endmodule Fig. 8.12 The comparator/MUX after logic synthesis, but before logic optimization. This figure shows the structural netlist, comp_mux_u.v,and its derived schematic.

a series of synthesis commands (we call tìiis a synthesis run). Figure 8.11 shows a sữuctuial netlist, comp mux u.v, and the derived schematic after logic synthesis, but before any logic optimization. A derived schematic is created by software from a structural netlist (as opposed to a schematic drawn by hand), shows the structural netlist, comp_mux_o.v, and the derived sche­ matic after logic optimization is performed (with the default settings). Figures 8.12 and 8.13 show the results of the two separate steps: logic synthesis and logic optimization. The whole process, which includes synthesis and optimization (and other steps as well), is refeaed to as logic synthesis.We also refer to the software that performs all of these steps (even if the soft­ ware consists of more than one program) as a logic synthesizer.

VHDL Modelling of Digital Systems

b[i]^ 'timescale 1ns / lOps module comp_mux_o (a, b; outp): input [2:0] a; input [2:0] b; output [2:0] outp; supplyl VDD; suppiyO VSS; inOldO B1J1 (,l(a[2]), .ZN(B1_i1_ZN)); inoido B1J2 (.l(b[1]), .ZN(B1J2_ZN)): oa01d1 B1J3 (.A1(a[0]), .A2(B1J4_ZN). .B1{B1_i2_ZN). .B2(a[1]), .ZN(B1_i3_Z; fn05d1 B1J4 {.A1(a[1]), ,B1(b[1]), .ZN(B1J4_ZN)): fn02d1 B1J5 (.A(B1J3_ZN), .B(B1_i1_ZN). .C(b[2]), .ZN(B1J5_ZN)); . mx21d1 B1J6 (,l0(a[0]), ,l1(b[0]),.S(B1J5_ZN), ,Z(outp[0])): mx21d1 B1J7 (.IO(a[lj), .I1(b[1]),.S(B1_i5_ZN), .Z(outp[1])): mx21d1 B1J8 (.IO(aI2]), .I1(b[2]),.S(B1_i5_ZN), ,Z(outp[2])); endmodule

281

o

INV

NORl-l

(inOIdO)

(fnO S dl)

&

INV (inO ldO )

’O

OA122 (oaOldl)

critical path

MAJ3 (fli02dl)

b[0]a[0] ---- 1

0 MUX

outp[0]

b[2]a[2] I Jk 1 0

b[l]a[l] 1> » 1 0

outp[2]

ou tp [ 1]

Fig, 8.13 The comparator/MUX after logic synthesis and logic optimization with the default settings. This figure shows the structural netlist, comp_mux_o,v, and its derived schematic.

Logic synthesis parses (in a process sometimes called analysis) and translates (sometimes called elaboration) the input ETOL to a data structure. This data structure is then converted to a network of generic logic cells. For example, the network in Fig. 8.12 uses NAND gates (each with three or fewer inputs in this case) and inverters. This network of generic logic cells is technology-independent since cell libraries in any technology normally con­ tain NAND gates and inverters. The next step, logic optimization, attempts to improve this technology-independent network under the controls of the designer. The output of the optimization step is an optimized, but still technology-independent, network. Finally, in the logic-mapping step, the synthesizer maps the optimized logic to a specified technologydependent target cell library. Figure 8.14 shows the results of using a standard-cell library as the target. Text reports such as the one shown in Table 8.2 may be the only output that the designer sees from the logic-synthesis tool. Often, synthesized ASIC netlists and the derived schemat­ ics containing thousands of logic cells are far too large to follow. To make things even more difficult, the net names and instance names in synthesized netlists are automatically generated. This makes it hard to see which lines of code in the HDL generated which logic cells in the synthesized netlist or derived schematic. In the comparator/MUX example the derived schematics are simple enough that, with hind­ sight, it is clear that the XOR logic cell used in the hand design is logically inefficient. Using

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Table 8.2 Reports fromthe logic synthesizer for ttie Verilog vmion of ttie comparator/MUX Command

Synthesizer output 1

> synthesize

Num Gate Count Tot Gate Mdth ToUd Cell Name Insts Per Cell Count Per Cell Width inOldO 5 .8 3.8 7.2 36.0 nd02d0 16 1.0 16.0 9.6 153.6 ndOSdO 2 1.3 2.5 12.0 24.0 Totals: 23 22.2 213.6

> optimize

Num Gate Count Tot Gate Width Total Cell Name Insts Per Cell Count Per Cell Width fii0 2 dl 1 1.8 1.8 16.8 16.8 &05dl 1 1.3 1.3 12.0 12.0 inOldO 2 .8 1.5 7.2 14.4 mx21dl 3 2.2 6.8 21.6 64.8 oaOldl 1 1.5 1.5 14.4 14.4 Totals:

> report timing

8

12.8 122.4

instance name inPin outPin incr arrival tts rampDel cap cell (ns) (ns) (ns) (pf) a[l] .00 .00 R .00 .04 comp_m... Bl_i4 A1 ZN .33 .33 R .17 .03 filOSdl Bl_i3 A2 -> ZN .39 .72 F .33 .06 oaOldl Bl_i5 A -> ZN 1.03 1.75 R .67 .11 fii02dl Bl_i6 s z .68 2.43 R .09 .02 mx21dl

XOR logic cells does, however, result in tíie simple schematic of Fig. 8.10. The synthesized version of the comparator/MUX in Fig. 8.12 uses complex combinational logic cells tìiat are logically efficient, but the schematic is not as easy to read. Of course, the computer does not care about this—and neither do we since we usually never see the schematic. Which version is best—^the hand-designed or the synthesized version? Table 8.2 shows sta­ tistics generated by the logic sjmthesizer for the comparator/MUX. To calculate tìie perfor­ mance of each cừcuit that it evaluates diưing synthesis, there is a timing-analysis tool (also

VHDL Modelling of Digital Systems

o

283

known as a timing engine) built into Ae logic synthesizer. The timing-analysis tool reports Ihat the critical path in the optimized comparator/MUX is 2.43 ns. This critical path is high­ lighted in the report and consists of the followmgdelays: • 0.33 ns due to cell filOSdl, instance name

a two-mput NOR cellwith an inverted

input. We might call this a NORl-1 or (A + B) logic cell. • 0.39 ns due to cell oaOldl, instance name an OAI22 logic cell. • 1.03 ns due to logic cell fii02dl, mstancename Bl_i5, a three-inputmajority MAJ3 (A, B, C). • 0.68 ns due to log ic cell mx21dl, instance name Bl_i 6 , a 2:1 MUX.

function,

(In this cell library, the ‘d r suffix indicates normal drive strength.) After gettmg the timing report for critical path designer implements various techniques to reduce the delay and improve the performance of the cữcuit. Note: Optimized tuning report is not shown here.

1. Diưing chip development, simulations are carried out at different stages, such as at the component level (standard cell design, analog cell design, and mem­ ory design), system level, RTL level, gate level, and postlayout gate level. 2. The current sjmthesis tools available today convert Register Transfer Level (RTL) descriptions to gate level netlists. 3. The inputs to the synthesis process are an RTL (Register Transfer Level) VHDL description, cữcuit constraints and attributes for the design, and a technology library. The synthesis process produces an optimized gate level netlist from all of these inputs. 4. Logic minimization involves the reduced number of literals which ultimately saves the silicon area. 5. The mapping process takes the logically optimized Boolean description created by the optimization step and uses the logical and timing information from a technology library to build a netlist. 6 . Consteaints are used to control the output of the optimization and mapping process. They provide goals that the optimization and mappmg processes try to meet and control the structural unplementation of the design. 7. Technology libraries hold all of the information necessary for a synthesis tool to create a netlist for a design based on the desired logical behaviour, and constramts on the design.

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Fill in the Blanks

1. 2. 3 4. 5. 6.

7 8.

9. 10.

Stochastic simulation is carried out at th e_________ level. The analyzer in simulation system checks’ tíie source for_______error. . ______ sũnulation is (he most complex and time consuming foim of simulaiiftg _______ is the process of constructing a gate-level netiist from a model (rf circuit described in VHDL. ________synthesis can be used to create technology-specific inq>leinentation from technology independent VHDL description. The process of converting the unoptimized Boolean description to a PLA for­ mat is known a s ________ . . _________ is the process of adding intermediate terms to add stoucture to a description. __________ combines the net list used for place and route with the timing file from the place and route process. For the designs o f ______ ^to_______ gates, post route timing simulation can be good method of verifying design fimctionality and timing. The ideal case is one in which the critical path w as_______ for speed and Ihe rest of the design w as_________ for small area and low fanout.

Answers 1. 2. 3. 4. 5. 6. 7. 8.

System Syntactic Circuit level Synthesis RTL Flattening Factoring post-layout timing simulation

9. 10,000-100,000 10. flattened, factored

CHAPTER

CMOS Testing

CHAPTER OBJECTIVES In this chapter, you will be introduced to • • • • • •

Motivation for testing Test principles Design strategies for testing Design for testability Boundary scan testing Built-in self test

9.1 NEED FOR TESTING— MOTIVATION Following the so-called Moore’s law [Moore 1965], the scale of ICs has doubled every 18 months. A simple example of this trend is the progression from SSI to VLSI devices. In the 1980s, the term “VLSI” was used for chips having more than 100,000 transistors and has continued to be used over time to refer to chips with millions and now hundreds of millions of transistors. In 1986, the first megabit random access memory (RAM) contained more than 1 million transistors. Microprocessors produced in 1994 contained more than 3 million transis­ tors. VLSI devices with many millions of transistors are commonly used in today’s comput­ ers and electronic appliances. This is a direct result of the steadily decreasing dimensions, referred to as feature size, of the transistors and interconnecting wires from tens of microns to tens of nanometres, with cuưent submicron technologies based on a feature size of less than 100 nanometres (100 nm). The reduction in feature size has also resulted in increased

286

o

VLSI Design

operating frequencies and dock speeds; for exanq)le, in Ỉ971, ứie first microprocessor ran at a clock frequency of 108 kHz, while current commercially available microprocessors commonly run at several gigahertz. The reduction in feature size mcreases the probability that a manufacturing defect in the IC will result in a faulty chip. A very small defect can easily result in a faulty tiansistor or iotaconnecting wke when the feature size is less than 100 nm. Furthermore, it takes only one &ui1y ừansistor or wừe to make the entire chip fail to function properly or at ứie required operating frequency. Yet, defects created during the manufacturing process are unavoidable, and, as a result, some number of ICs is expected to be faulty; therefore, testing is reqiured to guarantee faultfree products, regardless of whether the product is a VLSI device or an electronic system composed of many VLSI devices. It is also necessary to test components at various stages durmg the manufacturing process. For example, in order to produce an electronic system, we must produce ICs, use these ICs to assemble printed cừcuit boards (PCBs), and tíien use the PCBs to assemble the system. There is general agreement with the rule of ten, which says that tíie cost of detecting a faulty IC increases by an order of magnitude as we move through each stage of manufacturing, from device level to board level to system level and finally to system opera­ tion in the field. Electronic testing includes IC testmg, PCB testing, and system testing at the various manufacturing stages and, m some cases, during system operation. Testing is used not only to find the fault-free devices, PCBs, and systems but also to improve production yield at the various stages o f manufacturing by analyzing the cause o f defects when faults a re encountered. In some systems, periodic testing is performed to ensure fault-free system opera­ tion and to initiate repair procedures when faults are detected. Hence, VLSI testing is important to designers, product engineers, test engineers, managers, manufacturers, and end-users. 9.2 TESTING DURING THE VLSI LIFE CYCLE Testing typically consists of applying a set of test stimuli to the inputs of the c ir c u U under te s t (CUT) while analyzing the output responses, as illusưated in Fig. 9.1. Cữcuits that pro­ duce the correct output responses for all input stimuli pass the test and are considered to be fault-free. Those circuits that fail to produce a coưect response at any point during the test sequence are assumed to be faulty. Testing is performed at various stages in the life cycle of a VLSI device, including during the VLSI development process, the electronic system manufac­ turing process, and, in some cases, system-level operation.

Fig . 9 .1 Circuit under test.

CMOS Testing

o

287

A testable circuit is defined as a cừcuit whose internal nodes of interest can be set to 0 or 1 laá in which any change to the desừed logic value at the node of interest, due to a fault, can le observed externally. VLSI development process is iỉỉusứated in Fig. 9.2, where it can be seen that some fann of testing is involved at each stage of the process. Based on a customer or project need, ả A^SI device requừement is determined and formulated as a design specification. Designers are ttien responsible for s)0 ithesizing a circuit that satisfies the design specification and for verifying the design. Design verification is a predictive analysis tìiat ensiưes that the synthe­ sized design will perform the required functions when manufactured. When a design eưor is found, modifications to tíie design are necessary and design verííìcation must be repeated. As a result, design verification can be considered as a form of testing. Once verified, the VLSI design then goes to fabrication. At the same time, test engineers develop a test procedure based on the design specification and fault models associated with the implementation technology. A defect is a flaw or physical imperfection that may lead to a fault. Due to unavoidable statistical flaws in the materials and masks used to fabri­ cate ICs, it is impossible for 100% of any particular kind of IC to be defect-free. Thus, the first testing performed during the manufacturing process is to test the ICs fabricated on the wafer in order to determine which devices are defective. The chips that pass the wafer-level test are exttacted and packaged. The packaged devices are retested to eliminate those devices ùat may have been damaged during the packaging process or put into defective packages. Additional testing is used to assure the final quality before going to market. This final test­ ing includes measurement of such parameters as inpuưoutput timing specifications, voltage.

Fig . 9.2 Testing at various stages.

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VLSI Design

and cuưent. In addition, bum-in or sưess testmg is oữeo performed where chips are subjected to high temperatures and supply voltage. The purpose of bum-in testing is to accelerate the effect of defects that could lead to, failures in the early stages of (^)eratíoii of the IC. Faiime m o d e a n a ly s is (FMA) is typically used at all stages of IC manafacturiiig testing to iden­ tify improvements to processes that will result in aD increase in the number of defect-free devices produced. Design verification and yield are not only important aspects of the VLSI development process but also important in VLSI testing. Design Strategies for Test A VLSI design can be described at different levels of abstraction, as illusttated in Fig. 9.2. The design process is essentially a process of transforrmng a higher level description of a design to a lower level description. Startmg from a design specification, a behavioural (architectuie) level description is developed in very high-speed in te g r a te d c i r c u it h a r d w a r e d e s c r ip tio n lan­ guage (VHDL) or Verilog or as a c program and simulated to determine if it is function­ ally equivalent to the specification. The design is then described at the register-transfer level (RTL), which contains more structural uiformation m terms of the sequential and combina­ tional logic functions to be performed in the data paths and control cừcuits. The RTL descri{vtion must be verified with respect to the functionality of the behavioural description before proceeding with synthesis to the logical level. A logical-level implementation is automatically synthesized from the RTL descnptíon to produce the gate-level design of the circuit. The logical-level unplementation should be veri­ fied in as much detail as possible to guarantee the coưect functionality of the final design. In the final step, the logical-level description must be transformed to a physical-level descrip­ tion in order to obtain the physical placement and interconnection of the transistors in the VLSI device prior to fabrication. This physical-level description is used to verify that the final design will meet timmg and operating frequency specifications. There are many tools available to assist in ứie design verification process including computer-aided design (CAD) synthesis and simulation tools, hardware emulation, and formal verification methods; however, design verification takes time, and insufficient verification fails to detect design eưors. As a result, design verification is economically significant as it has a def­ inite impact on time-to-market. It is interesting to note that many design verification techniques are borrowed from test technology because verifymg a design is similar to testmg a physical product. Furthermore, the test stimuli developed for design verification of the RTL, logical, and physical levels of abstraction are often used, in conjunction with the associated output responses obtained from simulation, to test the VLSI device during the manufacturing process. Yield and Reject Rate Some percentage of the manufactured ICs is expected to be faulty due to manufacturing defects. The yield of a manufacturing process is defined as the percentage of acceptable parts among all parts that are fabricated: Number of acceptable parts Total number of parts fabricated

CMOS Testing

a.

289

^ There are two types of yield loss: catasttophic and parametric. Catastrophic yield loss is dhie to random defects, and parametric yield loss is due to process variations. Automation of and improvements in a VLSI fabrication process Ime drastically reduce the particle density that creates random defects over time; consequently, parametric variations due to process fluc­ tuations become the dominant reason for yield loss. When ICs are tested, the following two undesữable situations may occur: 1. A faulty device appears to be a good part passing the test. 2. A good device fails the test and appears as faulty. These two outcomes are often due to a poorly designed test or the lack of design fo r test­ ability (DFT). As a result of the first case, even if all products pass acceptance test, some faulty devices will still be found in the manufactured electronic system. When these faulty devices are returned to tìie IC manufacturer, they undergo FMA for possible improvements to the VLSI development and manufacturing processes. The ratio of field-rejected parts to all parts passing quality assurance testing is refeưed to as the reject rate, also called the defect level: ^ _ Number of faulty parts passing final test Total number of parts passing final test The reject rate provides an indication of the overall quality of the VLSI testing process. Generally speaking, a reject rate of 500 parts per million (PPM) chips may be considered to be acceptable, while 100 PPM or lower represents high quality. ChaUenges in VLSI Testing The physical implementation of a VLSI device is very complicated. Any small piece of dust or abnormality of geometrical shape can result in a defect. Defects are caused by process variations or random localized manufacturing imperfections. Process variations affecting ừansistor channel length, transistor threshold voltage, metal interconnect width and thick­ ness, and intermetal layer dielectric thickness will impact logical and timing performance. Random localized imperfections can result in resistive bridging between metal lines, resistive opens in metal lines, improper via formation, etc. Recent advances in physics, chemistry, and materials science have allowed production of nanometre-scale structures using sophisticated fabrication techniques. It is widely recognized that nanometre-scale devices will have much higher manufacturing defect rates compared to conventional complementary metal oxide semiconductor (CMOS) devices. They will have much lower cuưent drive capabilities and will be much more sensitive to noise-induced errors such as crosstalk. They will be more susceptible to failures of ứansistors and wires due to soft (cosmic) eưors, process variations, elecữomigration, and material aging. As the integration scale increases, more transistors can be fabricated on a single chip, thus reducing the cost per transistor; however, the difficulty of testmg each transistor increases due to the increased complexity of the VLSI device and

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mcreased potential for defects, as well as the difficulty of detecting the faults produced by those defects. Manufacturing tests fall into a number of categories. 9.3 TEST PRINCIPLES A fault is a representation of a defect reflecting a physical condition that causes a cuciiit to fail to perform in a requữed manner. A failure is a deviation in the perfonnance of a cừcuit or system from its specified behaviour and represents an ừreversible state of a conqx>nent such ứiat it must be repaừed in order for it to provide its intended design function. A drcuit error is a wrong output signal produced by a defective cữcuit. A cữcuit defect may lead to a fault, a fault can cause a cữcuit eưor, and a cữcuit eưor can result in a system failure. 9.3.1 Exhaustive Testing To test a cữcuit wiứi n inputs and m outputs, a set of input patterns is applied to tíie cữcuit under test (CUT), and its responses are compared to the known good responses of a fault-free cữcuit. Each mput pattern is called a test vector. In order to completely test a cữcuit, many test patterns are requữed; however, it is difiBcult to know how many test vectors are needed to guarantee a satisfactory reject rate. If tiie CUT is an «-input combinational logic cữcuit, we can apply all 2" possible input patterns for testing stuck-at faults; this approach is called exhaustive testing. If a circuit passes exhaustive testing, we might assume that the circuit does not contam functional faults, regardless of its internal structure. Unfortunately, exhaustive testing is not practical when n is large. Furthermore, applying all 2" possible input patterns to an «-input sequential logic cữcuit will not guarantee that all possible states have been visited. However, this metìiod of applying all possible input test patterns to an n-input combinational logic cừcuit also illustrates the basic idea of functional testing. 9.3.2 Functional Testing In this testing every entty in the truth table for ứie combinational logic cừcuit is tested to determine whether it produces tìie coưect response. In practice, functional testing is consid­ ered by many designers and test engmeers to be testing the CUT as thoroughly as possible in a system-like mode of operation. In eitìier case, one problem is the lack of a quantitative measvưe of the defects that will be detected by the set of functional test vectors. 9 .3 .3 Structural T e s tin g

The approach of structural testing is to select specific test patterns based on cừcuit struc­ tural information and a set of fault models. Structural testing saves time and improves test efficiency, as the total number of test patterns is decreased because tìie test vectors target spe­ cific faults that would result from defects in the mamifactured cữcuỉt. Structural testing cannot

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guarantee detection of all possible manufecturing defects, as the test vectors are generated based on specific fault models; however, the use of fault models does provide a quantitative measure of the fault-detection capabilitÌM of a given set of test vectors for a targeted fault model. This measure is called fault coverage and is defined as: „ , ___ Number of detected faults Fault coverage = - r \ . Total number of feults It may be impossible to obtain fault coverage of 100% because of the existence of unde­ tectable faults. An undetectable fault means there is no test to distinguish the fault-free cữcuit from a faulty cừcuit containing that fault. As a result, the fault coverage can be modified and expressed as the fault detection efficiency, also referred to as the effective fault coverage, which is defined as: Fault detection effeciency =

Number of detected faults Total number of faults-number of undetectable faults

Fault coverage is linked to the yield and the defect level by the following expression: Defect level = 1-yield

coverage)

From this equation, we can show that a PCB with 40 chips, each having 90% fault coverage and 90% yield, could result in a reject rate of 41.9%, or 419,000 PPM. As a result, improving fault coverage can be easier and less expensive than improving manufacturing yield because making yield enhancements can be costly; therefore, generating test stimuli with high fa ult coverage is very important. 9 .3 ^ Fau lt Sim ulation

Any input pattern or sequence of input patterns that produces a different output response m a faulty circuit from that of the fault-free cừcuit is a test vector, or sequence of test vectors, that will detect the faults. The goal of test generation is to find an efficient set of test vectors that detects all faults considered for that cừcuít. Because a given set of test vectors is usually capable of detecting many faults in a cừcuit, fault simulation is typically used to evaluate the fault coverage obtained by that set of test vectors. As a result, fault models are needed for fault simulation as well as for test generation. Fault Models Fault models are necessary for generating and evaluating a set of test vectors. Generally, a good fault model should satisfy two criteria: (1) It should accurately reflect the behaviour of defects. (2) It should be computationally efficient in terms of fault simulation and test pattern generation.

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The most commonly used model in VLSI cữcuit testing is ứie stuck at fault (SAF) model. The SAF model assumes that any node (a net in a netlist) within a silicon chip has ứie poten­ tial risk of being permanently tied to power (stuck at one, SAl) or ground (stuck at zero, SAO) due to various manufacturing defects. Either SAl or SAO makes the affected node non-functional since that node cannot be switched by the circuit for logic operation any longer. Consequently, the chips that contain such nodes are regarded as bad chips and cannot be delivered to the customer. Design for test is the art of inserting some exfra testing cừcuitry inside the chip to search for such SAF nodes. An SAF is a particular fault model used by fault simulators and automatic test pattern gen­ eration (ATPG) tools to mimic a manufacturing defect within an integrated cữcuit. It is not the only model for DFT but it is the simplest and most widely used, especially for digital designs since 0 and 1 are the only concerns in these circuits. However, although very powerful, the SAF model is not a true description of how a node is malmanufactured or damaged. It does not provide physical manifestations of the defect (defect mechanism) but only ứie behaviour or effect caused by the defect. For example, metal shorting through a foreign material between a node and ground node or the failure of an internal transistor could both cause an SAO. Figure 9.3 shows an example of an SAO fault model. In this circuit, there are seven nodes (or nets); A, B, c , D, E, F, and G. The diagram at the right shows that an SAO fault is pre­ sented at physical location y, which belongs to node G. In other words, node G is always at ground electtic potential and cannot be switched by its driver Cell X to logic “1,” regardless of Cell X’s drive sfrength. Thus, this circuit is not qualified for its intended design function and should be discarded. During fault simulation or ATPG, test patterns are generated to stimulate the cừcuit and detect the effects of such SAFs. During tíiis process, every single node in the cừcuit is assumed to have the potential of being stuck at either 0 or 1. The aim of a good set of test patterns is to detect all of these faulting nodes in the circuit using a minimum of resources (CPU time, memory, disk space, and tester time, for example). Example of stuck at fault Consider the example circuit shown in Fig. 9.4, where the nine signal lines representing potential fault sites are labelled alphabetically. There are 18 (2 X 9) possible faulty cữcuits under the single-fault assumption. Figure 9.5 gives the truth tables for the fault-free circuit C ell_Y

C ell_Y

f> B-

Cr-

>

>

ẩ>

Point y, stuck at 0

Cell_x

Cell_x

DrCell_z Fault-free model

Cell_z

Stuck at fault model Fig. 9.3 Stuck at faults.

CMOS Testing

X1X2X3

y

aSAO

0

aSAl

0

bSAO

0

bSAl

0

cSAO

0

cSAl dSAO

0

dSAl

0

eSAO

0

eSAl

0

fSAO

0

fSAI

0

gSAO

0

gSAl hSAO

0

hSÁl iSAO

0

iSAl Fig. 9.5 Truth tables for the fault-free circu

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and the faulty cữcuits for all possible single stuck-at faults. Any of tíiese nodes can be shotted to power supply (stuck at 1) or shorted to ground (stuck at zero). Hence, nine nodes contrib­ ute for 18 potential fault sites. This can be seen in Fig. 9 .5 , where SAO on £mout brancli line d behaves differently from SAO on fanout branch line e, while tibie single SAO &ult on die fanout source line b behaves as if both fanout branches Ime d and line e are SAO. The row with value y denotes coưect output values of a fault free drcilit The toutfa table entries where the faulty cữcuit produces an output response different from that of ứie Ẽuihfree cừcuit are highlighted m grey. As a result, the input values for the highli^ted fruth table entries represent valid test vectors to detect the associated stuck-at faults. For example consider node is stuck at 0, ;.e., due to manufacturing defect it is permanently grounded. For the input values 110 and node a is stuck at zero we obtained the ou^ut 0 bill for tíiose inputs the fault free cữcuit should have 1 as ou^ut. Hence, it is to be understood ứiat the ckcuit has fault associated with it and should be discarded; all such wrong o u ^ values that are different to the correct values are identified along with theứ inputs. Hence we can conclude that those input test vectors detect the faults at possible 18 sites. With the excep­ tion of line d SAl, line e SAO, and line f SAl, all other faults can be detected with two 01 more test vectors, test vectors o il and 1 0 0 must be included m any set of test vectors that will obtain 100% fault coverage for this cữcuit. These two test vectors detect a total of ten Êiuỉts, and the remaining eight faults can be detected with test vectors 0 0 1 and 1 1 0 ; tfierefore, this set of four test vectors obtains 1 0 0 % smgle stuck-at fault coverage for this cừcuit.

What are various categories of manufacturing tests? Manufacturing tests fall into ã number of categories depending upon the mtended goal; >■

1. The diagnostic test is used during the debugging of a chip or board and tries to accomplish the following: Given a failing part, identify and locate the offendmg fault. 2. The functional test (also called go/no go test) determines whether or not a manufactured component is functional. This problem is súnpler than the diag­ nostic test since the only answer expected is yes or no. As this test must be exe­ cuted on every manufactured die and has a dữect impact on the cost, it should be as sunple and swift as possible. 3. The parametric test checks on a number of Dondiscrete parameters, such as noise margms, propagation delays, and maximum clock frequencies, under a variety of working conditions, such as temperature and supply voltage. This requừes a different set-up from the functional tests ứiat only deal wiứi 0 and 1 signals. Parameừic tests generally are subdivided into static (dc) and dynamic (ac) tests.

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(CONTROLLABILITY AND OBSERVABILITY)

The most common approach to testing a digital circuit is to toggle every node inside the cir­ cuit and observe the coưespondmg effect. The foundation of this approach is the SAF model. However, in practice, this is not always easily achieved. In a circuit of combinational logic, (he logic states of the mtemal nodes can be determined if the circuit’s inputs are all known. But for a circuit that includes sequential elements, such as flip-flops and latches, this is not Irue. Some of the node’s logic states depend on these sequential cell’s previous states. This leads to controllability and observability issues. In the design for testability regime, for any node in a circuit, controllability is defined as tìie capability of a node being driven to 1 or 0 through a cừcuit’s inputs. If this node can be driven faithfully to 1 and 0, it is regarded as controllable. Observability is defined as the capa­ bility of the logic state of this node bemg observed at the circuit’s outputs. If the logic state of this node can reliably be observed, this node is regarded as observable. Whether a circuit node is stuck at 1 (or 0 ) is only testable if that node is both controllable and observable. 9.5 DESIGN FOR TESTABILITY (DFT) Test engineers usually have to construct test vectors after the design is completed. This invari­ ably requkes a substantial amount of time and effort that could be avoided if testing is con­ sidered early in the design flow to make the design more testable. As a result, mtegration of design and test, refeưed to as design for testability (DFT), was proposed in the 1970s. To structurally test circuits, we need to control and observe logic values of internal lines. Unfortunately, some nodes in sequential cữcuits can be very difficult to conữol and observe; for example, activity on the most significant bit of an n bit counter can only be observed after 2"“' clock cycles. Testability measures of conữollability and observability were first defined in the 1970s to help find those parts of a digital cữcuit that will be most difficult to test and to assist in test pattern generation for fault detection. Many DFT techniques have been proposed since that time. DFT techniques generally fall into one of the following three categories: (1) Ad hoc DFT techniques (2) Level-sensitive scan design (LSSD) or scan design (3) Built-in self-test (BIST) 9.5.1 Ad hoc DFT Techniques As suggested by the title, ad hoc testing combines a collection of tricks and techniques that can be used to increase the observability and controllability of a design and that are generally applied in an application-dependent fashion. An example of such a technique is illustrated in Fig. 9.6(a), which shows a simple processor with its data memory. Under normal configuration, the memory is only accessible through the

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Fig. 9.6 (a) Design with lowtestability (b) Adding a multiplexer (selector) improves testability.

processor. Writing and reading a data value into and out of a single memory position requừes a number of clock cycles. The controllability and observability of the memory can be dramati­ cally improved by addmg multiplexers on the data and address buses (Fig. 9.6). During normal operation mode, these selectors direct the memory ports to the processor. During test, the data and address ports are connected directly to the I/O pins, and testing the memory can proceed more efficiently. The example illusừates some important design-fortestability concepts. It is often worthwhile to mtroduce extra hardware that has no functionality except improv­ ing the testability. Designers are often willing to incur a small penalty in area and performance if it makes the design substantially more observable or controllable. Design-for-testability often means that extra I/O pins must be provided besides die nonnal functional I/O pins. The test port in Fig. 9.6(b) is such an extra pin. To reduce the niunber of extra pads that would be requữed, one can multiplex test signals and functional signals on the same pads. For example, the I/O bus in Fig. 9.6(b) serves as a data bus during normal opera­ tion and provides and collects the test patterns during testing. An extensive collection of ad hoc test approaches has been devised. Examples include tìie partitioning of large state machines, addition of extra test points, prevision of reset states, and introduction of test buses. While very effective, the applicability of most of these techniques depends upon the application and architecture at hand. Thek insertion into a given Hftsign requires expert knowledge and is difficult to automate. SttTictured and automatable approaches are more desirable.

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9S2 System Level Testing o r BoanI Test Tcdiniques Like ứie VLSI fabrication process, PCB manufacturing is a capital-intensive process with min­ imum human intervention. Once a high-volume batch has been started, the process is totally immaimed. Potential problems that could cause poor yield are monitored throughout the pro­ cess. In tìie 1970s and 1980s, PCBs were tested by probing the backs of the boards with probes (also called nails) in a bed-of-nails tester. The probes are positioned to contact various solder points on the PCB in order to force signal values at the component pins and monitor ùe output responses. Generally, a PCB tester is capable of perfoiming both analog and digital functional tests and is usiially designed to be modular and flexible enough to mtegrate differ­ ent external instruments. Two steps were traditionally taken before testing an assembled PCB. Fừst, the bare board was tested for all interconnections using a PCB tester, primarily targeting shorts and opens. Next, the components to be assembled on the PCB were tested. After assembly, the PCB was tested by using a PCB tester. In the modem automated PCB production process, solder paste inspection, automated optical and X-ray inspections, and in-circuit (bed-of-naik) testing are used for quality control. With the advent of surface-mount devices on PCBs in the mid-1980s, problems arose for PCB in-cứcuit testing, as the pins of the package did not go through the board to guarantee contact sites on the bottom of the PCB. These problems were overcome with the introduction of boundary scan.

9.5.2.1 Boundary Scan Testing BouDdary-scan, as defined by the IEEE Std.-1149.1 standard, is an integrated method for test­ ing interconnects on printed cữcuit boards (PCBs) that are implemented at the integrated cừcuit (IC) level. Architecture The boundary-scan test architecture provides a means to test interconnects between inte­ grated cừcuits on a board without using physical test probes. It adds a boundary-scan cell that includes a multiplexer and latches to each pm on the device. Cells on device primary inputs are refeưed to as “input cells”; cells on primary outputs are refeưed to as “output cells.” “Input” and “output” is relative to the internal logic of the device. The collection of boundary-scan cells is configured into a parallel-in, parallel-out shift reg­ ister. A parallel load operation called a capture operation causes signal values on device input pins to be loaded into input cells, and signal values passing from the mteraal logic to device output pins to be loaded into output cells. A parallel unload operation called an update opera­ tion causes signal values already present in the output scan cells to be passed out through the device output pins. Signal values already present in the input scan cells will be passed into the internal logic. Data can also be shifted around the shift register, in serial mode, starting from a dedicated device input pin called Test Data In (TDI) and tenninating at a dedicated

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Test Data In (TDI) Test Clock (TCK) Test Mode Select (TMS) Test Data Out (TDO)

Fig. 9.7 Architecture of boundary scan test.

device output pin called Test Data Out (TDO). The Test ClocK, TCK, is fed in via yet another dedicated device mput pin and the various modes of operation are conừolled by a dedicated Test Mode Select (TMS) serial control signal. At the device level, the boundary-scan elements contribute nothing to the functionality of the internal logic. In fact, the boundary-scan path is independent of the ftmction of tíie device. The value of the scan path is at the board level as shown in Fig. 9.8. The figure shows a board containing four boundary-scan devices. Notice that there is an edge-connector input called TDI connected to the TDI of the first device. TDO from the first device is permanently connected to TDI of the second device, and so on, creating a global scan path terminating at the edge connector output called TDO. TCK is connected in parallel to each device TCK input. TMS is connected in parallel to each device IMS input. Captured data is serially shifted out and externally compared to the expected results. Forced test data is serially shifted into the boundary-scan cells. All of this is controlled from a serial data path called the scan path or scan chain. • Potential benefits realized from the use of boundary-scan are shorter test times, higher test coverage, increased diagnostic capability and lower capital equipment cost. The internal structure of a cell is shown in Fig. 9.9. The cell has four modes of operation: normal, update, capture, and serial shift. The memory elements are two D-type flip-flops with front-end and back-end multiplexing of data. 1. During normal mode, Data in is passed straight through to Data_Out. 2. During update mode, the content of the Update Hold cell is passed through to Data_Out.

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vr ỉ i.

o

2M

'í • Fig. 9.8 Boundary scan test (board level). Scan Out (SO)

Data In (PI)

= 0, Functional mode Mode = 1 ' Xest mode (forBC_l)

Data Out (PO)

—► Scan In ShiftDR ClockDR (SI)

UpdateDR

c s

Ư

Fig. 9.9 Internal structure of the cell. 3. During capture mode, the Data in signal is routed to the mput Capture Scan cell and the value is captured by the next ClockDR. ClockDR is a derivative of TCK. 4. During shift mode, the Scan Out of one Capture Scan cell is passed to the Scan_In of the next Capture Scan cell via a bard-wừed path.

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Note that both capture and sh ift operations do not mterfere widi ứie nonnaỉ passing of data from the parallel-m terminal to the paraliel-out terminal. This allows on the fly capture of operational values and the shifting out of these values for inspection widiout interference. Example: The principles of interconnect test using boundary-scaii are illustrated in Fig. 9.10. Figure 9.10 depicts two boundary-scan compliant devices, U1 and U2, which are connected with f(Mir iníCTconnects (wkes). U1 includes four outputs ứiat are driving the four iiq)iits of U2 with various values. In tíiis case, we assume that the cừcuit mcludes two fadts: a short between wue 2 and 3, and an open on wữe 4. We will also assume ứiat a short between two wires behaves as a wữed-AND and an open is sensed as logic 1. To detect and isolate tìie above defects, ứie ỉ«ster is shifting into the U1 boundary-scan register the patterns shown in Fig. 9.10 and appXymg diese patterns to the inputs of U2. The mputs values of Ư2 boundary-scan register are sỉúíỉed out and compared to the expected results. In this case, the results (underlined) on wues 2,3, and 4 do not match the expected values and, therefore, the tester detects the faults on wửes 2, 3, and 4.

Response iil

Stimulus U1

Ỉ0001

wừel

10001

Short 10000

10010 10100

11000

wire3 Open vnTeỹ

10000 11111

Fig. 9.10 Interconnect test example. 9.5.3 Built in Self-Test (BIST) Built-in Self-Test, or BIST, is the technique of designing additional hardware and software features into integrated cữcuits to allow them to perform self-testing, i.e., testing of theừ own operation (functionally, parametrically, or both) using theữ own cừcuits, thereby reducing dependence on an external automated test equipment (ATE).

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BIST is a Design-for-Testability CDFT) techmque, because it makes the electrical testing of j}áiíp easier, faster, more efficient, aid less costly. The concq)t of BIST is applicable to just ị^out any kind of cữcuit, so its implementation can vaiy as widely as the product diversity ihut it caters to. As an example, a common BIST approach for DRAM’s includes the incoipoỊỊẹtínn onto the chip of additional cừcuits for pattern generation, timing, mode selection, and | 0 ./iio-go diagnostic tests. Ị The general fonnat of a built-in self-test design is illustrated in Fig. 9.11. It contains a fliwms for supplying test patterns to the device under test and a means of comparing the device’s response to a known coưect sequence. ^ There are many ways to generate stimuli. Most widely used are the exhaustive and the ran­ dom qjproaches. In the exhaustive approach, the test length is 2", where n is tìie number of ^ u ts to the cừcuit. The exhaustive nature of the test means that all detectable faults will be detected, given the space of the available mput signals. An iV-bit counter is ã good example of an exhaustive pattern generator. For cứcuỉts with large values of N, the time to cycle through ihe complete input space might be prohibitive. An alternate approach is to use random test­ ing ứiat implies tìie application of a randomly chosen subset of 2 ” possible input patterns. This subset should be selected so that a reasonable fault coverage is obtained. An example of a pseudorandom pattern generator is the linear-feedback shift register (or LFSR), which is shown m Fig. 9.12. It consists of a serial connection of 1-bit registers. Some of the outputs are XOR’d and fed back to the input of the shift register. An N-bit LFSR cycles through 2'^^ states before repeatmg the sequence, which produces a seemingly random pattern. Initializa­ tion of the registers to a given seed value (different from 0 for oiư example cừcuit) determines what will be generated, subsequently. The response iuialyzer could be implemented as a comparison between the generated response and the expected response stored in an on-chip memory, but this approach represents too much area overhead to be practical. A cheaper technique is to compress the responses before comparing thèm. Storing the compressed response of the coưect cữcuit requữes only ã minimal amount of memory, especially when the compression ratio is high. The response

Fig. 9.11 General format of BIST.

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So 1 0 1 1 1 0 0 1

s, 0 1 0 1 1 1 0 0

S2 0 0 1 0 1 1 1 0

Fig. 9.12 Three-bit linear feedback shift register and its generated sequence. analyzer then consists of circuitry that dynamically compresses the output of ứie cữcuit under test and the comparator. The compressed output is often called the signature of the cừcuit, and the overall approach is dubbed signature analysis. An example of a signature analyzer that compresses a single bit stream is shown in Fig. 9.13. Inspection reveals that this cừcuit simply coimts the nunber of 0-»l and l->0 tran­ sitions in the input sừeam. This compression does not guarantee that the received sequence is the coưect one; that is, there are many different sequences with the same number of ừansitions. Since the changes of this happening are slim, it may be a risk worth takmg if kept within bounds. Another technique is illustrated in Fig. 9.14a. It represents a modification of the linear feedback shift register and has the advantage that the same hardware can be used for boứi pattern generation and signature analysis. Each incoming data word is successively XOR’d with the contents of LFSR. At the end of the test sequence, the LFSR contains the signature, or syndrome, of the data sequence, which can be compared with the syndrome of ứie correct circuit. The circuit not only ũnpỉements a random-pattem generator and signature analyzer.

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but also can be used as a normal register and scan register, depending on the values of the control signals Bo and Bi (Fig. 9.14(b)). This test approach, which combines all the different techniques, is known as built-in logic block observation, or BILBO. Figure 9.14(c) illustrates the typical use of BILBO. Using the scan option, the seed is shifted into the BILBO register A while BILBO register B is initialized. Next, registers A and B are operated in the random pattem-generation and signature-analysis modes, respectively. At the end of the test sequence, the signature is read from B using the scan mode. Dn

D,

D,

Fig. 9.14(a) BIBO register.

Bo

B,

Operation mode

0

0

Normal

0

1

Scan

1

0

Pattern generation or signature analysis

1

1

Reset Fig. 9.14(b) BILBO modes.

Finally, it is worth mentioning that self-test is extremely beneficial when testing regular structures such as memories. It is not easy to ensure that a memory, which is a sequential circuit, is fault free. The task is complicated by the fact that the data value read from or written into the cell can be influenced by the values stored in the neighbouring cells because of cross coupling and other parasitic effects. Memory tests, therefore, include the reading and writing of a number of different patterns into and from the memory using alternating addressing sequences. Typical patterns can be all zeros or ones, or checkerboards of zeros

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Fig. 9.14(c) BILBO application.

and R/w control Fig. 9.14(d) Memory self-test.

and ones. Addressing schemes can include the writing of the complete memory followed by a complete read-out or various alternating read-write sequences. With a minimal overhead compared with the size of the memory, this test approach can be built mto the integrated circuit itself, as illustrated in Fig. 9.14(d). This approach significantly improves the testing time and minimizes the external control. Applying self-test is bound to become more impor­ tant with the increasing complexity of integrated components and the growing popularity of embedded memories. Advantages of implementing BIST include: 1. Lower cost of test, since the need for external electtical testing using an ATE will be reduced, if not eliminated. 2. Better fault coverage, since special test structures can be incorporated onto the chips. 3. Shorter test times if the BIST can be designed to test more structures in parallel. 4. Easier customer support. 5. Capability to perform tests outside the production electrical testing envừonment. 6 . Allow the consumers themselves to test tìie chips prior to mounting or even after tìiese are in the application boards.

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Disadvantages of implementing BIST include: 1. Additional silicon area anH fab Ịưocessing requừements for the BIST cữcuits 2. Reduced access times 3. Additional pin (and possibly bigger package size) requirements, since the BIST circuitry need a way to interface with the outside world to be effective 4. Possible issues with the correctness of BIST results, since the on-chip testing hardware itself can fail. Issues that need to be considered when implementing BIST are: 1. 2. 3. 4. 5.

Faults to be covered by the BIST and how these will be tested for How much chip area will be occupied by the BIST circuits External supply and excitation requừements of the BIST Test time and effectiveness of the BIST Flexibility and changeability of the BIST (i.e., can the BIST be reprogrammed through an on-chip ROM?) 6 . How the BIST will impact tìie ỊM-oduction electrical test processes that are already m place.

1. Testing typically consists of applymg a set of test stimuli to the inputs of the cữcuit under test (CUT) while analyzing the output responses. 2. A defect is a flaw or physical imperfection that may lead to a fault. Due to unavoidable statistical flaws in the materials and masks used to fabricate ICs, it is impossible for 100% of any particular kind of IC to be defect-free. 3. Failure mode analysis (FMA) is typically used at all stages of IC manufactur­ ing testing to identify improvements to processes that will result in an increase in the number of defect-free devices produced. 4. A fault is a representation of a defect reflecting a physical condition that causes a circuit to fail to perform in a required manner. 5. A failure is a deviation in the performance of a circuit or system from its speci-, fied behaviour and represents an iưeversible state of a component such that it must be repaừed in order for it to provide its intended design function. 6 . In functional testing every entry in the truth table for the combinational logic cừcuit is tested to determine whether it produces the correct response or not. 7. The yield of a manufacturing process is defined as the percentage of accept­ able parts among all parts that are fabricated. 8 . Structural testing saves time and improves test efficiency, as the total number of test patterns is decreased because the test vectors target specific faults that would result from defects in tìie manufactured circuit.

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9. An SAF is a particular fault model used by Ẽnilt simulators and automatic test pattern generation (ATPG) tools to mimic a mamifactiirm g defect widiin an integrated cữcuit. 10. Boundary-scan, as defined by the IEEE Std.-1149.1 standard, is an integrated method for testing interconnects on printed cừcuit boards (PCBs) that are implemented at the mtegrated cừcuit (IC) level. 11. Built-in Self Test, or BIST, is the technique of designing additional hardware and software features into integrated cứcuits to allow them to perform self­ testing, i.e., testing of thek own operation (iunctionally, paramebically, or both) using theữ own cừcuits.

1. A _____________is a flaw (or) physical imperfection that may lead to a fault. 2. ____________ is used at all stages of IC manufacturing to result in an increase in the number of defect-free devices that are produced. 3. The ratio of number of acceptable parts to total number of parts fabricated is 4. 5. 6. 7.

__________ testing involves testing the cữcuit with all possible input patterns. __________ technique increase observability and conừollability of a design. __________ is used to test interconnects. __________ is a technique in which self-testing isdone on the IC at the cost of additional hardware and software. 8 . __________ are the disadvantages of BIST. 9. __________ are the ideas to increase speedof faultsimulation. 10. are examples of fault models. Answers 1. Defect 2. Failure mode analysis 3. Yield 4. Exhaustive 5. Ad hoc DFT 6 . Boundary scan testing 7. Built-m self-test 8 . Reduced access times, additional silicon area 9. Parallel and concuưent simulations 10. Stuck at faults, short cừcuit and open cữcuit faults

CHAPTER

Issues in Chip Design

CHAPTER OBJECTIVES In this chapter, you will be introduced to • • • • • • •

Requkements for chip design System on chip Power consumption The clock Chip reliability Analog integration in digital environment Crosstalk delay

10.1 REQUIREMENTS OF A SUCCESSFUL CHIP DESIGN In the field of modem VLSI circuit design, constructing a chip from concept to silicon is an ulfra complicated task that involves many factors. For a successful project, the chip must be: • Structurally correct to achieve its intended design functions • Functionally coưect at the designed clock speed in various working environments (volt­ age, temperature, and process comer) • Reliable throughout its life (e.g., 100k hours or eleven years) • Manufacturing-friendly • Further, it must be built such that It can be handled safely in an assembly line and vari­ ous other environments without being damaged (e.g., it is protected from electrostatic discharge or ESD and latch-up).

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It can be packaged economically. It stays within its power budget. Cost is minimized. It is manufactured within its time schedule. «

List out some goals of the chip design. When a company makes a decision to invest in a project to create a product (designing a chip), the ultũnate goal is to generate maximum profit from ứiis invest­ ment. The approach to pursumg this goal is by conducting busmess “faster, better, and cheaper.” >■

1. Faster means that the new chip must operate faster than its predecessors or faster than similar chips produced by competitors, which requữes it to perfoim specific tasks in less time. 2. Better refers to the fact that the chip must support more functions (do more) than its predecessors. 3. Cheaper means that the cost of developing and manufacturing the new chip must be kept to a minimum.

10.2 SYSTEM-ON-CHIP (SoC) SoC or system on chip is the design approach of integrating the components of an electronic system into a single chip. In the past, chips could only perform dedicated simple functions, such as simple logic operations, decoding/encoding operations, analog-to-digital conversion, digital-to-analog conversion, and so on. As time went by, more and more functions were integrated into a single chip. This integration trend is so significant that it has reached the point where a single chip can perfomi the functions of an entire electronic system, such as an MPEG decoder, a network router, or a cellular phone. As a result, a colourful name was cre­ ated for such chips: system on chip (SoC). SoC designs often consume less power, cost less, and are more reliable than the multichip systems that they are designed to replace. Further­ more, assembly cost is reduced due to the fact that there are fewer packages m ứie system. The key to the SoC approach is integration. By integrating increasingly more preassembled and verified blocks, which have dedicated functions, into one chip, a sophisticated system is created in a timely and economical fashion. Figure 10.1 is a block diagram of a SoC that shows the various blocks on a chip. As seen in the figure, integrating predesigned and verified blocks into a large chip is the essence of SoC approach. A typical SoC chip has one or more microprocessors or microconứollers on board, the brain of the SoC chip. The on-chip processor (e.g., an RISC conừoUer)

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Fig. 10.1 A S o C block diagram.

coordinates the activities inside the chip. In some cases, a dedicated DSP engine, which targets algorithm-intensive signal processing tasks, may also be found on a SoC chip. Having a large niưnber of memory blocks is another characteristic of a SoC chip. These memories (ROM, RAM, EEPROM, and Flash) support the SoC’s software functions. Another indispensable com­ ponent of a SoC chip is the timing source, which includes an oscillator and phase lock loop (PLL). It is almost always true that one or more PLLs are found on any SoC chip since most SoC designs are based on synchronous design principle, and clocks are the key design feature. A SoC needs external interfaces, such as industry standard USB, Firewire, Ethernet, and UART, to communicate with the outside world. A direct memory access (DMA) controller

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can be used to route data dừectly between the external uilar&ces and monories, bypassing die on-chip processor and thereby increasing the data tfaroug^p^ ư a SoC is designed to ìaterũcc with devices that have dữect contact wiứỉ human activities, some an^og ctmqxMiaits, such as ADC or DAC, are essential. In some cases, on-chip voltage regulators and power management cừcuits can be found in ã SoC as well. To tie the components of a SoC togedier, an on-chip bus architecture is requừed for internal data ttansferring. This is either a proprietary bus or an industry-standard bus such as the AMBA bus from ARM. Network on a chip (NoC) is a new approach to SoC design. In an NoC system, modules such as processor cores, memories, and specialized IP blocks exchange data usmg a network as a public-ưansportation subsystem. The network is constructed from multiple point-to-point data links interconnected by switches such that messages are relayed from any source module to any destination module over several links by making routing decisions at the switches. The NoC approach brings a netwoikiiig solution to on-chip communication and provides notable ừnprovements over conventìoDaỉ bus systems. From the viewpomt of physical design, the on-chip interconnect dominates botìi the dynamic power dissipation and performance of deep submicron CMOS technologies. If a signal is requữed across the chip, it may requừe multiple clock cycles when propagated in wines. A NoC link, on the other hand, can reduce the complexity of designing long interconnecting wữes to achieve predictable speed, low noise, and high reliability due to its regular, well-confrolled structure. From the viewpoint of system design and with the advent of multicore processor systems, a network is a natural architectural choice. A NoC can provide separation between the tasks of computation and communication, support modularity, and IP reuse via standard inter­ faces, efficiently handle synchronization issues, and serve as a platform for system test. Just as the major hardware blocks are critical, so is the software of a SoC. The software controls the microcontroller, microprocessor, and DSP cores; the peripherals, and ứie inter­ faces to achieve various system functions. One mdispensable step in SoC development is emu­ lation. Emulation is the process of using one system to perform the tasks in exactly the same way as another system, perhaps at a slower speed. Before a SoC device is sent out to fabrica­ tion, it must be verified by emulation for behaviour analysis and making predications. Ehưing emulation, the SoC hardware is mapped onto an emulation platform based on a FPGA (or the likes) that mimics the behaviour of the SoC. The software modules are loaded into the memory of the emulation platform. Once progranuned, the emulation platform enables both the testing and the debugging of the SoC hardware and the software. In summary, ứie SoC approach is primarily focused on the integration of predesigned, preverified blocks, not on the design of individual components. In other words, the keyword is integration, not design. *

lljQggQQL ► What are the driving forces for SoC? One of the major driving forces behind the SoC trend is cost. Integrating more functions into a single chip can reduce the chip count of a system and tìius shrink the package and board cost. It could potentially lower the overall system cost and

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make tìie product more ccmjpetitive. In today’s consumer elecứonic market and in others, b e ^ price always provides advantage of gaining market share. During ứie past decade (from the late 1990s) or S Ơ , the SoC approach has been proven to be one of tíie most efiective ways of reduẹỉng tìie cost of elecfronic devices. The other forces behind this trend include pursuing higher chip performance or higher operating fre­ quency. This is owing to the fact that SoC can eliminate interchip communication and shorten the distances among the onchip components, which positively enhances the chip speed. In some cases, the demand for overall lower system power usage is also a factor for choosing tìie SoC approach. And, portability is another advantage of the SoC method. When a system is migrated from an old process to a new one, SoC can greatly reduce the workload compared to the fransfer of several chips. Overall, SoC chip implementation has enabled many technology innovations to reach the consumer in shorter and shorter timeframes.

I0J.1 Role of the Embedded Processor in the SoC Embedded microprocessors are the brains of the SoC. A system-on-chip is built primarily around the processors. The key difference between the embedded processor and the generalpxưpose processor is that embedded processors are used in an environment that is suưounded by many other on-chip components, whereas the general-purpose processor is a stand-alone chip. As its name suggests, the general-purpose processor is designed for general usage. In contrast, the embedded processor is designed for a specific application. The performance of the general-purpose processor can be improved at the expense of power usage and silicon area. In other words, for the general-purpose processor, performance is the highest priority. However, for the embedded processor, cost and power consumption are more significant. A low-power processor is especially attractive to the SoCs used for mobile applications. Several approaches have been employed to improve the performance of embeddedprocessor-based systems. The most commonly used increases clock frequency. However, this can result in increased power consumption. Additionally, since the performance of the external memory has not kept pace with processor technology, this processor and memory mismatch gap limits the overall system performance gain from the clock speed increase. Another approach is a multicore system with several processor cores on chip to improve performance. But this is companied by the expense of larger areas and higher power usages. Multi issue processors with two or more execution units offer another alternative. But they also have a large-area penalty. Also, the software must be revised to make best use of the mul­ tiple pipelines. The multithreading approach, which supports multiple threads of software on a single core, provides some balance of the trade-offs. This approach obtains its performance gain by keeping the processor hardware as busy as possible. Another direction in embedded processor development is the configurable core. It enables SoC designers to create silicon that is optimized to the end application and gives designers the

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freedom to retain necessary functionality while removing unneeded features. This produces an optimal balance of speed, area, and power for ã specific application. The configurable core can also have extendibility so that SoC designers CỈU1 achieve íiirtíier gain in application by defining custom extensions to accelerate critical code execution. Typically, embedded processors are delivered to semiconductor customers as IPs by IP ven­ dors. Cuưently, the most popular processor platforms used for embedded SoC applications are the ARM and MIPS cores. In the configurable core market, the ARC core is most significant An issue closely related to the on-chip processor is embedded memory, which is critical for SoC software development. During the past several decades, the processor’s performance has been improved greatly. However, memory performance has not caught up with Ae pace. As this performance gap widens, chip designers have placed greater emphasis on tìie development of embedded memory devices. The advantages of using embedded memories are as follows: inter chip communication is eliminated; response time is faster, chip pin count is reduced, ứ»e num­ ber of chips at the system level is reduced so less board space is required, on-chip multiport memories can be easily realized, and, finally, memory capacity is specific for an application, resulting in reduced power consumption and greater cost-effectiveness at the system level. The main disadvantages of embedded memories follow: 1. Size. They are generally larger in size (compared to stand-alone memory, in area per bit). 2. Complexity. They are more complex to design and manufacture. 3. Design and technology trade-offs. Because the optimized technology for a memory cell is often not the same as that for on-chip logic devices, there are trade-offs between design and technology. 4. Processing. Processing becomes more complex as designers integrate different types of memory on the same chip. Cuưently, embedded SRAM is widely used in SoC designs due to its easy integration with logic devices. Embedded DRAM is not as popular due to the complexity of DRAM process technology. Embedded DRAM capacitors that store data require several processing steps that are not needed when making logic devices. Also, the threshold voltage of DRAM transistors must be high enough to ensure that they do not cause memory cell capacitor leakage. This constraint on low subthreshold current may result in a speed penalty on the logic portion of the device. Until recently, DRAM has been the least-used embedded memory technology. However, it may become a more widespread solution as on-chip memory demand increases. The non-volatile embedded memory options include embedded ROM, embedded EPROM, embedded EEPROM, and embedded flash memory. Their reprogrammability and in-cữcuit pro­ gramming capability provide highly flexible solutions to rapidly changing market demands. 10.3 CHIP'S POWER CONSUMPTION: AN IMPORTANT ISSUE Ideally, when designing a chip, we want the chip to use the least power possible without sacri­ ficing chip performance. In general, better performance and higher speed require greater power consumption. Greater power consumption in turn demands more sophisticated cooling systems, more expensive packaging, and larger batteries if the chip is used for mobile applications.

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Therefore, one of the challenges m designing VLSI chips is to minimize the power usage ^ all tnftans possible and ứie chips envkomnent-friendly. There are certain techniques for domg this but they are perfonned at the expense of other design merits such as area, speed, or design complexity. However, in some cases, smarter architecture at the system level can achieve the goal of significantly reducing the power usage without negatively impacting other design aspects. This issue of cutting down a chip’s power usage will become increasingly important as future devices are more power sensitive. It will become more of a problem, too, as leakage current gains influence on the overall power consumption of shrinking process geometries. 103.1 Power Network In order for ứansistors to perform theữ assigned tasks, a certain level of voltage must be pre­ sented at the transistors Vdd terminals. At the same time, the electtical current travelling through the cừcuit elements must have a return pass. Thus, the teansistors’ Vss, or ground, termmals must also be connected. A power network is a physical metal structure whose function is to deliver the necessary power (or current) to all of the transistors on the chip. It is the bridge between the power supplies provided outside the chip and the fransistors located inside the chip. A power network is comprised of wide metal lines inside of which current can flow without a substantial resistive force. Figure 10.2(a) is a detailed picture of a power network for the small designs. In this figure, it is seen that the Vdd and Vss terminals of the standard cells, which are located on the top and bottom sides of each are connected to their dedicated busses. In adjacent rows, the cells are placed in a vertically opposite orientation so that they can share the common Vdd and Vss bus. Figure 10.2(b) is the power network of a large chip. As shown, it is complicated: every macro and memory cell has its own power network, which must be connected to the main chip power network. As addressed in Chapter 1, the main concerns for a power network are IR drop and elecfro migration problems (EM). The typical IR drop requirement is within 5%. In a 1.1 V power supply design, therefore, Vdd cannot fall below 1.05 V, and Vss ground bounce cannot exceed 0.05 V. If the IR drop varies outside this range, there is no guarantee that the circuit will operate properly. The typical method of curing IR drop is to widen the metal lines since wider metal lines result in less resistance. The drawback is an increase in area. Tools are available that can do the IR drop and EM analysis on a power network. Designers must rely on these tools to construct and fine-tune a design’s power network for meeting the IR drop and EM requirement without increasing the area too much. This process will likely require several iterations. An EM check is performed with the calculation of cuưent flowing through each piece of metal on the chip. Then the current densities are checked against the predetermined limit set by the particular process technology. The solution for curing EM violations is also the wid­ ening of metal geometry since the current density is reduced when the cross-section area is increased. Unlike the IR drop problem, which has an immediate negative impact on chip per­ formance, the EM problem is a long-term phenomenon, which will eventually affect the chip’s lifespan. In mixed-signal SoC mtegration, the power-planning problem becomes even tougher due to the requirement of separating the analog power supplies from the main digital chip

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Fig. 10.2 (a) A power network (b) The power network of a large chip. supply. When there are considerable numbers of such analog macros present in the chip, the problem can quickly become an affliction. Consừucting a reliable power network is the most tedious and labour-intensive work in chip physical design. Although there are tools available to ease this pain, it is still mainly sfressfiil manual work. 10.3.2 Power Optimization Power optimization is a design sữategy that aims at reducing the cữcuit power consumption without significantly degrading cừcuit performance. A typical example of power optimization is placmg the part of the circuit that is not needed at any particular moment into an idle state (the clock gating technique). Another commonly used power optimization metíiod is to add extra cừcuits to control the leakage cuưent, using multiple Vt threshold voltage transistors. A third example is to always run cữcuits at low operating frequencies unless it is absolutely necessary to run them at higher speeds (this is more or less a system level technique that is especially use­ ful for general purpose CPU chips). In the past, during the logic synthesis process, tíie optimi­ zation targets were speed and area. Nowadays, the optimization targets have widened to speed, area, and power. In some cases, power minimization might even be the number one priority. 10.3.3 Chip Power Usage Analysis Design for power is a design strategy that addresses the concern of the ever-mcreasing power consumption by VLSI chips. As process geometries shrink, chip designers can pack more stuff

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insiHft a single chip. Consequently, the power consumption by the chip increases coưespondmgly To make things even worse, current chips are operating at much higher frequencies ptimpared to chips of ten or twenty years ago. And the power they bum is directly propor­ tional to the operating frequency. Thus, it is not imcommon to see a chip’s power consumption exceed tens of watts, or even hundreds of watts. Under these circumstances, a great amount of heat is generated by the chips and coolmg is a serious challenge. On another front, more and *mẶ:e mobile applications, which operate on batteries, require low-power operation to achieve longer working hours. For these reasoas, the issue of design for power has moved from backstage to front stage. TTie formidable challenge posted in this frontier is reducing chip power consumption without significantly degrading chip performance. One of the key issues in the design for power chal­ lenge is the analysis of chip’s power usage. Power analysis is the process of analyzing chip or block power consumption based on the cữcuit topology, the cữcuit operating speed, the cữcuit Diode’s switch pattern, and the physical layout of the cữcuit. f! Ideally, power analysis should be carried out at the transistor level using a transistor-level simulator such as SPICE or the likes. However, for most designs, this is not practical due to the capacity limitation of those simulators. In real design practice, special power analysis tools are available that base their power analysis calculations on power models of standard cells and macros. To obtain reliable power analysis, users must provide the tools with accurate operat­ ing frequencies and node switching patterns.

10^ CLOCK A clock is an electric signal that oscillates between a high state and a low state. It is usually a square wave with a predetermined period (frequency), as shown in Fig. 10.3. In synchro­ nous digital cứcuits, the clock signals coordinate the actions of all the circuit components on a chip. The cừcuits become active at either the rising edge, the falling edge, or both edges of the clock signals for synchronization. The issue associated with clock signals is the most important design factor in any VLSI chip design. Synchronization is a task in timekeeping that requires the coordination of events to oper­ ate a system in a harmonic fashion. In an elecfronic circuit, in which millions of events occur every second, the synchronization of these events is the key to achieving the desired functions. During the process of synchronization, for some applications, relative timing offsets between events must be known or determined. For others, only the order of the events is significant. The synchronous design principle can significantly simplify the implementation task in chip design. The design and verification burden are eased greatly. This is especially true for large SoC designs in which design complexity is dreadful. As an example, the synchronous design principle enables the technique of static time analysis (STA), which is an essential tool for achieving timing closure. Synchronous design style also enables the method of formal veri­ fication, which is an important approach for logic verification. Without synchronous design principles, or clocks, it is impossible to construct the complicated SoC chips that we build today.

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Poiod of frequency

/ V _ fu

Clock signal

7

Rising edge

Falling edge

v_

>

Fig. 10.3 A clock signal waveform.

As just addressed, in today’s VLSI chip design envữonment most integrated cũcuils of sufficient complexity requữe clock signals to synchronize different parts of the cfajp and to accoimt for propagation delays. However, as chips get more complex and clock q>eeds approach the gigahertz range, the task of supplying accurate and synchronized clocks to d l of the cừcuit components becomes more and more difficult. Furthermore, the voltage and cunent spikes associated with clock switching become harder to conữol becaiise millions of compo­ nents are switching at roughly the same time. As a result, the asynchronous self-clock cứcuit design approach has been explored with great interest. Figure 10.4 shows the principal ideas of synchronous and asynchronous design styles. In the synchronous design approach, the actions are coordinated by the clock signal as data is moved from register to register. In confrast, in clockless asynchronous designs, the actions are coordinated by a handshake mechanism between the blocks. When a block must initiate a data transfer, it first sends a request signal (REQ). The intended block issues an acknowledge sigỵial (ACK) when it is ready for tìie transfer. All of the data communication inside the asynchronous block is accomplished though certain handshake mechanisms without using the clock. The advantage of this method is that it eliminates the design overheads associated with clock structure. In some cases, the asynchronous design approach can potentially increases

Synchronous design style

Asynchronous design style

Fig. 10.4 Synchronous and asynchronous design styles.

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die daia throughput as well. It also provides the superior modularity that is prefeưed for SoC d^gns. Due to the clockless feature, it is more robust against the process, temperature, and voltage variations in terms of wứe delay. It definitely lessens the power supply noise by reduc­ ing the cuưent peak around die clock edges. The overall power consumption is also ưũnmed since die clock-related power usage is now nonexistent. However, the asynchronous design style cannot be easily implemented in large designs due to the lack of the corresponding EDA tools. Additionally, the testing of the asynchronous design is more difficult tíian that of the synchronous cừcuit. Currently, there is a design approach c^ed globally asynchronous locally synchronous (GALS) that combines the advantages of both asynchronous and synchronous. Figure 10.5 presents this technique. In this configura­ tion, certain low-level blocks are synchronously designed. Then asynchronous wrappers with handshake mechanisms are consteucted around such blocks. At the chip level, conununication is accomplished through asynchronous interconnection. Clocks are also essential for certain types of analog cữcuits to function. For example, analog-to-digital converters and digxtal-toanalog converters all work on clock signals. The mtemal cừcuitry of these converters, and Oius the signal conversion, are triggered by the clock edge.

Asynchrooous interconnect Fig. 10.5 A globally asynchronous locally synchronous (GALS) system. 104.1 Clock Distribution The quality of the clock signals is the most important factor for ensuring a chip’s successful operation. In a design netlist, there are hundreds of thousands or millions of cells. Those cells can be classified as two types: combinational cells and sequential cells (including memories).

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The sequential cells are used for storing information and ứiey must operate (Ml clocks. After the placement stage of the design implementation process, all of ứie cells, mcluding the sequential cells, are spread around the entừe chip. The task of clock distribution is to distribute flie clock signals to all of these sequential cells. This work is commonly called clock tree synthesừ. Figure 10.5 shows the principle idea of how a clock tree is constructed. As dq)icted, a clock network may be constructed in ừee fashion. Starting from the clock source, the first level of clock buffers are laid out, then the second level, then the thữd level, and so on. In most designs, there are many clock domams, and each domain has hundreds or ứiousands of sequential cells attached to it. This many cells cannot be driven by a single buffer from the clock source, even with the sữongest buffer in the library. A tree structure is used to deal with this problem by letting each buffer drive only the number of loads that it is allowed to drive. As a result, the quality of the clock signal, in term of slew rate (the rising and &lling time of the clock edges), is not significantly degraded when it reaches tìie leaf sequential cells. Figure 10.6 shows the commonly used clock tree structures m the clock disưibution net­ works: trunk, branch-tree, mesh, X-ứee and H-tree. Figure 10.8 is an example of how a real clock ữee looks in a design block. In this simple example, there is one level of clock buffers between the clock root and the leaves. Another type of clock distribution network is the clock grid. In this approach, a grid of metal structure, which covers the entire chip, is dedicated to the distribution of clock signals, as graphically shown in Fig. 10.9. A tree structure usually consumes less wuing and thus less capacitance and less routing resources, which results in lower power and less latency. However, a tree structure must be carefully tuned and it is very load (placement) dependent. In contrast, a grid structure uses significantly more routing resources and thus has large capacitance and large latency, but it

H-live

Leaf

EIỈ

Clock Tree

Fig. 10.6 A basic clock tree.

Fig. 10.7 Com m only used tree structures in clock distribution networks.

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Fig. 10.8 An example of a clock tree in chip design.

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tends to be less load dependent as any leaf cell can always find a nearby tapping point to connect to directly. As a result, a grid structure ckick ^âriỉnitiỉm network is typically used only for high-end applications, such as microprocesscns, ^ o e a s a tree sfructure is widely used for ASIC-based designs. The clock distribution netwoik consumes mcne ứian 10% of the total power used by the chip in large designs. During each dock cycle, the capacitance associ­ ated with the entire clock structure must be chiu-ged to the siqjpiy voltage and subsequentiy dumped to ground, wifli the stored energy lost as heat. To ease this problCTi, resonant clock distribution has been actively studied by some groups. In this method, the toadỉtíonal tree- or grid-driven clock structure is augmented with on-chip mductors to resonate wMi the clock capacitance at the clock’s fundamental frequency. The energy of the fundamental fre q u e n c y resonates back and forth between its electric and magnetic form rather than being dissipated as heat. The clock driver is only used for adding the energy lost during the operation.

10.5 CHIP RELIABILITY A VLSI chip not only needs to function coưectly during the first few days, weeks, or months, but also has to function reliably for its entire lifespan. The lifespan of any chip designed for commercial use is usually defined as 100,000 hours or 11.4 years. However, diiring the design, fabrication, assembly, and test of the IC many factors can conteibute to its early failure. This aspect of chip development is referred as chip reliability. The difference between test-related failures and reliability-induced failures is that test related failures are detectable prior to prod­ uct shipment; whereas reliability induced failures occur after shipment. Reliability failures are those that are physically imdetectable with present test technology. They occur diuing the actual usage of the chip. The key environmental agents that can affect chip reliability are voltage, cxurent, tempera­ ture, and humidity. Transistor gate oxide breakdown (GOI), hot earner stress (HCS), nega­ tive bias temperature instability (NBTI) of pMOS devices, stress-induced voiding (srv), metal damage caused by electromigration, and the breakdown of the inter metal dielectric are often the physical mechanisms behind reliability failures. Typically, IC reliability is represented by a bathtub curve shown in Fig. 10.10, which shows the failure rate of ICs with respect to time. This curve has three individual regions: early life failure, useiiil life, and wear out. Each of these regions has its own potential failwe mechanism. Early life failures, also called infant mortalities, are typically caused by defects and contaminants introduced during the manufacturing process. With today’s well-controlled fabrication and assembly processes, very few early life failures occur. However, the materials that make up the gate and capacitor oxides, contacts, vias, and metal lines in the fabrication process can wear out over time with the application of constant voltage and current. This effect is cumulative and can eventually lead to opens and shorts in the cữcuit or change the electrical characteristics required for the product to function accurately. This is the failure mechanism in the wear-out region. It indicates the end of the chip’s useful life. The failure rate in the useful life region is low and near constant, which implies low-level residual defects. Failures in this region are also due to electrical overstress or ESD events. This

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Fig. 10.10 Product reliability.

type of damage can occur when the ICs are handled or transported without the use of ESD protection such as ground straps; ESD-resistant trays, tubes, or reels; or properly grounded machines in assembly. Protection from ESD must be part of the circuit design consideration and manufacturing/assembling environment. Ideally, the shape of the bathtub curve should have a brief region of early life failure and a very long region of useful life. Chip reliability is a complicated issue that involves both the work of the chip designer and the quality of the fabrication at foundry. The foundries are steongly motivated to mitigate any physical mechanism that may cause a chip to fail. They need to understand the physics of every failure mechanism and identify wafer processing steps that may detrimentally influence the mechanisms. Once the wafer processing steps are optimized for maximum chip lifetime, the foundries develop design rules intended to prevent chip designers from overstressing the devices and causing the expected lifetime to fall below the target. The design rules are embod­ ied in the form of maximum operating voltage, transistor channel length constraints under certain bias conditions, maximum cuưent per unit line width in the metal interconnect, maxi­ mum current per via or contact, and certain constraints upon very wide metal lines. Failure to comply with these reliability design rules can lead to shorter chip lifetime. The semiconductor industiy is approaching physical, material, and economic limits as aggressive scaling continues. This results in formidable reliability challenges. Some of the emergmg reliability challenges include increased gate leakage cuưents as oxides become so thin that direct tunnelling occurs between the channel and the gate, the trade-off of reduced reliability safety margms for increased performance, the need for improved design for reliabil­ ity capability, the need to address the chip’s increased sensitivity to background radiation that results in increased single-event logic state upset probability, and the need to address bum-in as more products are used at near bum-in temperatures. VLSI circuits designed for environments with high levels of ionizing radiation have spe­ cial design-for-reliability challenges. A single charged particle of radiation can knock thou­ sands of electrons loose, causing electronic noise, signal spikes, and, finally, inaccurate circuit operation, especially in the case of digital circuits. This is a particularly serious problem in the

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circuits being used in the artificial satellites, spacecraft, military aứcraíi, nwrlear power sta­ tions, and nuclear weapons. To ensure the proper operation of such systems, manufacturers of these circuits must employ various methods of radiation hardenitig The resultant systems are said to be radiation hardened, or RADHARD for short. There are two approaches on designing RADHARD cữcuits. One is at the physical or pro­ cess level, the other is at the circuit or system level. At tìie physical or process level, tech­ niques include: 1. Manufacturing the circuits on insulating substrates rather than the usual semiconductor wafers. Silicon oxide (SOI) and sapphữe (SOS) are commonly used. Whereas a normal commercial grade chip can withstand between 5-10 krad of radiation, space-grade SOI and SOS chips can survive doses many orders of magnitude greater. 2. Shielding the package against radioactivity to reduce the exposure of the bare device. 3. Replacing capacitor-based DRAM with more rugged SRAM. 4. Choosing a substrate with a wide band gap (silicon carbide or gallium nitride) that has a higher tolerance to deep-level defects. 5. Using depleted boron (consisting only of isotope boron-11) in the borophosphosilicate glass layer protecting the chips, as boron- 1 0 readily captures neutrons and undergoes alpha decay. The methods used in circuit- and system-level RADHARD cừcuits include: 1. Error-coưecting memory, which has additional parity bits to check for, and possibly cor­ rect, coưupted data. 2. Redundant elements at the system level. For example, several separate microprocessor boards may independently compute an answer to a calculation; ứieừ answers are compared. Any system ứiat produces a minority result is requữed to recalculate. Logic could be added such that, for repeated errors in the same system, the board would be shut down. 3. Redundant elements at the circuit level as well. A single bit may be replaced with tìiree bits and separate voting logic for each bit to continuously determine its result. This increases chip area. But it has the advantage of being fail-safe in real time. In the event of a single-bit failure, the voting logic continues to produce the coưect result. 4. A watchdog timer hard reset as the last resort to other methods of radiation hardening. During normal operation, software schedules a Write to the watchdog timer at regular intervals to prevent tìie timer from running out. If radiation causes tíie processor to oper­ ate incoưectly, it is unlikely the software will work correctly enough to clear the watch­ dog timer. The watchdog eventually times out and forces a hard reset to the system. In general, most radiation-hardened chips are based on their more mundane commer­ cial equivalents with some manufacturing and design variations that reduce suscq)tibility to radiation and electromagnetic interference. Typically, the hardened variants lag behind the cutting-edge commercial products by several technology generations became it takes exten­ sive development and testing to produce radiation-tolerant designs.

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10^ ANALOG IHTEGRATION IN THE DIGITAL ENVIRONMENT Analog circuits are those cừcuits that monitor, condition, amplify, or transform continuous sig­ nals associated with certain physical properties, such as temperature, pressure, weight, light, soimd, and speed. Analog cừcuits play a major role in bridging the gap between real-world phenomena and electronic systems. Typically, most SoC chips are digitally oriented. If certain analog signal processing work is requứed, tíien the coưesponding analog circuit must be integrated into the chip. For instance, in a SoC targeting a HDTV application, analog ou^ut signals are required to drive the analog CRT monitor. Analog video or graphic input signals must also be converted to digital format to be processed by the on-chip DSP engine. In such cases, analog components of high-speed analog-to-digital converters (ADCs) and digital-to analog converters (DACs) are required as part of the chip. Other examples are high-speed serial links such as SErializer and DESerializer (SEDES). If this function is required for an SoC, then high-quality analog signal con­ ditioning cừcuits must be present in the chip as well. Moreover, in communication-oriented SoCs, radio frequency (RF) circuits are an indispensable part of the chip. Furthermore, almost every SoC has one or more phase lock loops (PLLs) on board as timing sources. The PLL is a very analog-intensive component as well. Compared with the approach of using separated chips for analog functions, integrating them into the SoC signifi­ cantly reduces the overall system cost. However, this approach is not without its own prob­ lems. The key challenge is analog performance. This is because SoCs are primarily digital oriented and are on digital processes. Thus, on-chip analog circuits cannot be optimized as well as in an analog-friendly process. The principal difficulty in using a digital CMOS tech­ nology for analog design is that the digital process is only optimized and characterized for the simple trade-offs among speed, area, and power dissipation. By contrast, analog circuits entail a multidimensional design space: noise, speed, voltage swings, supply voltage, gain, linear­ ity, power dissipation, and inpuưoutput impedance, where almost every two parameters trade with each other. Compared with a digital circuit, which is only sensitive to timing variation, an analog circuit is additionally subjected to voltage level variation. Consequently, the design complexity associated with an analog circuit is much greater than with its digital counter­ part. The device and circuit properties of interest in analog design include DC behaviour, AC behaviour, linearity, device matching, temperature dependence, and noise. Furthermore, since the manufacturing process itself is not completely predictable, designers must account for its statistical nature. This is especially true for analog designs. Unlike boardlevel analog circuit designs, which permit the designers to select devices that have each been tested and characterized completely, the device values for an IC can vary widely; the design­ ers cannot control these. The underlying cause of this variability is that semiconductor devices are highly sensitive to xincontrollable random variances in the manufacturing process. Uneven doping levels or slight changes to the amount of diffusion time can have significant effects on device properties. Consequently, analog IC circuits must be designed in such a way that the absolute values of the devices are less critical than the identical matching of the devices. To cope with the inherent variability of the individual devices built on chips, special design techniques are needed for analog IC designs, such as using devices with matched geometrical

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shapes so that they have matched variations, nuddng defaces laige so that statistical Varia­ tions become an insignificant fraction of the overall device properties, using the ratios 0 Í resistors (which do match closely) rather tìian the absolute resistors values,~segmentmg laige devices into parts and interweaving them to cancel variations, and using cominon centroid device layouts to cancel variations. For digital processes, the variety of available active and passive devices is often limited and the devices are only characterized and modelled according to simple benchmaiks, such as current drive and gate delay. Such a shortage of appropriate analog devices and ứie lack of analog characterization in the digital process can make the implementation of analog fimctions on a chip very challenging. Another major issue is noise isolation. Typically, SoCs contain large digital contents with complicated clock structures. When theừ digital cừcuits toggle at the moment of clock switohmg, a lot of noise is generated. The on chip analog ckcuits must be guarded from ứũs noise. The power supply voltage distortion caused by digital switching must be conữolled within certam levels for both the analog and digital components to work harmoniously in the same chip. The integration of the RF function in SoC environment fiirther complicates the issue. The performance issue of RF is multidimensional owing to the different requừements for the vari­ ous RF building blocks; low-noise amplifier (LNA), mixer, oscillator, and power amplifier. The implementation of a highly integrated radio transceiver on a CMOS digital process is one of the most difficult challenges in the area of SoC integration today. As a trend, more and more analog circuits will be foimd in future SoCs. Technically, there are many issues in the integration of analog and digital circuits. The know-how of this integration will be the key dif­ ferentiating factor among competing companies.

10.7 SYSTEM-LEVEL STUDY OF A PROJECT After a product is successfully defined from marketmg research, it is often followed by a system-level study. Sometimes this system-level study can start early during the production definition phase. The main focus of a system-level study is feasibility analysis. For a typical SoC applica­ tion, this study addresses issues in three critical areas: algorithm, architecture, and software inte­ gration. Algorithm design is an essential task in signal processing applications such as wkeless telephony, multimedia codecs, DSL, and cable modems. The optimal algorithms should meet tíie design functional requirements with minimiun resource claim. Architecture design is the work of putting together the right processors, custom logic, on-chip buses, memories, and peripherals in order to make most effective use of the silicon. It is performed through absttact modelling of tíie SoC architecture, which consists of those processors, algorithms, custom logic, buses, memories, and peripherals. The goal is to find the optimal architecture based on the trade-ofif between soft­ ware tasks and hardware functions with respect to performance, throughput, and latency. Software integration addresses the analysis of the interaction between the hardware and software components of the SoC. System-level design does not involve implementation detail. It is the approach of viewing the chip in a big-picture perspective. It abstracts away the full

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ệt^ítU of the design retaũũng just 6 0 0 *1# features to validate that functions embodied by the ilffBtgn r.an perform the specified go^ and CMI satisfy the performance criteria. The aim pfthis high-level study is to eosure âmt &e chip is built on a solid foundation, the chip is con­ cocted fundamentally coưect, and the chip architecture is the optimal solution based on the bade-off between perfonnance and resources required.

WHY IS VLSI SO CHALLENGINfi? As CMOS technology continually scales down to smaller geometries and the density of design integration predictably and ruthlessly scales up according to Moore’s Law, IC design produc­ tivity must increase at the same rate so tíiãt much larger chips are designed within the same man-hours budget. This increase in design productivity must come from new creative design methodologies and advanced EDA tools since the physical structure and mental capability of tiie human brain has been vữtually unchanged for the past hundreds of thousands years. Based on historical evidence to date, design productivity has kept up with technology and design density scaling very well, especially in the front-end design area. However, there are signs of slowdown in back-end productivity. Apparently, this evolution is tougher on physical design than it is on its front-end counterpart. Besides the design size factor, the difficulties in the physical design regime are due to the issues related to manufacturing technologies, such as device and interconnect parasitics, physical and electrical design rules, device reliability, and process variation. In the practice of real SoC design, these process-related issues surface as the challenges of timing closure, crosstalk, electromigration, mask optimization, antenna effect, voltage drop, inductance effect, and chip packaging. The challenge of timing closure is caused primarily by the parasitic capacitance of the onchip metal interconnection. In processes of 0.25 n^m and below, interconnect wire delay starts to dominate the gate delay on chip timing paths. However, the delay caused by wire parasitics is unknown at the logic synthesis stage. In the past, this problem was dealt with by the wire had model, which estimates wire parasitics based on a cell’s fan-out and design size. Statisti­ cally, this model is reasonably accurate, but the deviation in an individual wire could be off by a large amount. Since timing closure is judged by the worst case of millions timing paths on-chip, this kind of variation is unacceptable. Recently, the concept of logic effort has been infroduced in design practices to cure this problem. In this approach, during the logic synthe­ sis process, the gate sizes are not fixed as in the conventional approach. Instead, the timing budget, or capacitance load budget, for each gate is determined and fixed, while the gate sizes float. By following this method, the gates sizes are adjusted in a later physical design stage based on real wire parasitics when they are available. This approach provides a better chance for timing closures with faster turnaround times and smaller overall chip sizes. Crosstalk emerges as a major threat to design integrity as process technology continually shrinks. This is due to closer proximities and the taller aspect ratios of the interconnect wires. Because of this, the area in which they are facing each other increases. Consequently, the capacitance of the parasitics increases as well. This leads to two potential problems; crosstalk noise and crosstalk delay. The term crosstalk noise describes the phenomenon of wrong logic

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values that are latched into a flip-flop due to die switcfaing of neighbouring aggressor wii«s. Crosstalk delay, on the other hmd, is the additional delay hit cansfid by neighbouring wừes that switch in opposite directions between the aggressor and victim. Crosstalk problems can be avoided by shielding and spacmg. Additionally, proper gate siz­ ing can significantly reduce the number of aggressots (overdriven nets) and victims (undepdriven nets). When active transistors drive cuưent mto wữes, the electrons interact witíi the lattice imperfection. This electron cuưent can be viewed as electron wind ứiat slowly moves the atoms. Metal atoms are deposited (as hillocks) over time in the dữection of electron flow. In the opposite direction, however, voids grow between grain boundaries. In the long term, voids can reduce wire conductivity, whereas hillocks cm ÌBưoduce mechanical stress or cause shorts with neighbouring wires. This is the electromigration (EM) problem in IC design. Conteolling cuưent density inside of the wkes is the most effective method of harnessing elec­ tromigration. Widening the wires and, hence, reducing the cuưent density, can significantly ũnprove mean time before failure (MTBF). For this reason, wide wires are commonly used for a chip’s power and clock infrastructure in design practice. The current-handling cqiability of a via is generally less than that of a metal wừe of the same width. Therefore, routers are tuned to insert more vias at layer changes for high-ciuxent wires. In current process technologies, fransistor feature sizes are already smaller than the wave­ length of light that is used for creating the patterns. As a result, the actual pattern on the silicon deviates significantly from the original GDSII mask data. To coưect this distortion, a mask fea­ ture called optical proximity coưection, or OPC, is added to the mask creation process. Another technique of pushing the lithographical barrier is phase shift masking (PSM), which can help reduce fransistor gate length. In the future, using OPC and PSM will become more pervasive. The antenna problem is introduced during the IC manufacturing process. The IC chip is manufactured layer by layer from the subsừate up. After the base layers are finished and the transistors are formed, additional metal layers are deposited for completing the interconnec­ tions. During this process, a logic net might consist of a number of disconnected metal pieces before the connection is fully completed by all the needed layers. During this period, the static charge on a wire connecting to a silicon gate can result in high voltage and may cause the fransistor to break down. This half-assembled wire at an intermediate stage of metal process­ ing can act as an antenna that picks up electric charge. The longer the wire, the more charge it could build up. A diffusion contact such as a gate output or special-purpose diode could prevent such charge buildup. In practice, to address this issue, antenna design rules are for­ mulated. A typical antenna rule puts a maximum on the ratio between the metal wire length in a layer and the area of the ttansistor gate. The simplest way to address the antenna problem is to protect each gate input with a diode that has a diffusion contact. However, this results in a large overhead of area and adds parasitic load to the driver. The second approach is to direct the router to jump to higher metal layers near each gate input so that the lengths of the half-assembled wires are short. In this way, the designer avoids the size and load penalties of the diodes. Voltage drop, or IR drop as it is commonly called, is caused by the resistance of the on-chip network and the electrical current flowing through it. This problem mostly occurs on power networks due to the large cuưents they must carry. In today’s technology, the power supply voltage could be as low as 1 V. The typical IR drop requirement is within 5% of the supply voltage on both Vdd and Vss- Assuming that a chip

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C(msumes a current of 50 A (50 w of power when VpD = 1 V), this will teansfer into 1 mil effective resistance requirement for the power netwoik. The sheet resistance is determined by die interconnect material (which will be copper in the foreseeable future) and tíie thickness of the layer. The layout design tool controls tiie resistance by modulating the wữe width and the number of vias at the intersection of ứie layer change. In the past, the on-chip power infrastruc­ ture was created according to rule of thumb and was often times significantly overdesigned. In fiiture designs with even larger on-chip ciưrents, it will be increasingly more difficult to attack die IR drop problem by overdesigning and not increasing the overall chip size. Therefore, more accurate power simulation aad estimation tools are needed to provide a detailed picture of the current distribution on the chip. Another source of voltage drop is the wữe’s self-inductance. The slope of the power sup­ ply current introduces the voltage drop hy AV = L ■{dl/df). Reducing this self-inductance (and thus AV) requữes the package to have more power pins all over the die. Apart from reducing diis self-mductance, the ciurent slope can be trimmed by decoupling capacitors, either onchip, in the package, or on the board. The hierarchical approach is a very powerful way to deal with large complicated designs since it scales down the complexity of the problem. It also enables a group of people and com­ puters to work in parallel, which results m faster design convergence. This is especially true for system- and logic level design, in which there may be many levels of hierarchy. However, this ^jproach is not very effective in the physical design domain in which design is often performed in a much flatter fashion, usually with only two levels of hierarchy. The primary difficulty of using miiltíple levels of physical hierarchy is insufficient automation. Up till now, no feasible block-level, automatic place and route tool exists ứiat can handle blocks of various sizes and sh^es while meeting timing requừements and other constraints efficiently. Each hierarchical boundary adds some inefficiency due to the nonideal fit of the modules and the suboptimal placements and connections. It is also harder to hide the parasitic and physical effects, such as crosstalk, the antenna, and the wide metal spacing rule, behind the hierarchical abstractions. In conclusion, it is difficult to deny that VLSI physical design is indeed a very challenging, if not the most challengmg, task m the entire chip design process.

10.9 CROSSTALK DELAY By definition, crosstalk is a phenomenon in which a signal transmitted on one circuit, or one channel of a transmission system, creates an undesired effect m another circuit or channel. Electrically, crosstalk is caused by undesired capacitive, inductive, or conductive coupling from one cữcuit or channel to another. As shown in Fig. 10.11, two electric circuits are very close to each other physically in layout. The metal wires of the two circuits share some common silicon area. As a result, the signals travellmg through each of the wires can potentially interfere with each other through the coupling capacitor between them. In some cases, the impact of the aggressor (the signal that activates the interference) on the victim (the signal that receives the interference) is the delay addition or subtraction in the victim’s signal propagation time. This is called crosstalk delay. This deviation of delay could potentially cause a timing eưor.

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Real wavefoim

Ig error could happen

Fig. 10.11 Crosstalk delay.

1. The important goal of chip design is to conduct business of “faster, better, and cheaper” chips. 2. SoC or system on chip is the design approach of integrating the components of an electronic system into a single chip. 3. Greater power consumption in turn demands more sophisticated cooling sys­ tems, more expensive packaging, and larger batteries if the chip is used for mobile applications. 4. Power optimization is a design strategy that aims at reducing the circuit power consumption without significantly degrading circuit performance. 5. A clock is an electric signal that oscillates between a high state and a low state. It is usually a square wave with a predetermined period (frequency). 6 . Synchronization is a task in timekeeping that requires the coordination of events to operate a system in a harmonic fashion. 7. The quality of the clock signals is the most important factor for ensuring a chip’s successful operation. 8 . The task of clock disữibution is to distribute the clock signals to all of these sequential cells. This work is commonly called clock tree synthesis. 9. A free structure usually consumes less wiring and thus less capacitance and less routing resources, which results in lower power and less latency. 10. The key environmental agents that can affect chip reliability are voltage, cur­ rent, temperature, and humidity. Transistor gate oxide breakdown (GOI), hot

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carrier stress (HCS), negative bias temperature instability (NBTI) of pMOS devices, sfress-induced voiding (srv), metal damage caused by electromigration, and the breakdown of the mter metal dielectric are often the physical mechanisms behind reliability failures. 11. Analog cừcuits are those cừcuits that monitor, condition, amplify, or transform continuous signals associated with certain physical properties, such as temper­ ature, pressure, weight, light, sound, and speed. 12. Crosstalk is a phenomenon in which a signal transmitted on one ckcuit, or one channel of a transmission system, creates an undesired effect in another cữcuit or channel.

Fill in the Blanks 1. 2.

3. 4. 5 6.

7. 8. 9. 10.

_________ is the design approach of integrating the components of an elec­ tronic system into a chip. _________ is the process of using one system to perform tasks in exactly the same way as another system. _________ are the brams of SoC. A _______ is a physical metal sfructure whose function is tó deliver neces­ sary power to all transistors on the chip. . ________ are the main problems for interconnects. For more lifetime,______ of the devices should be high. __________ are used in asynchronous block on the chip. ___________operate on clock signal. IC reliability is measured b y _________ curve. is main focus of system level study.

Answers 1. System on chip 2. Emulation 3. Embedded microprocessor 4. Power network 5. IR-drop and electromigrations 6 . Reliability 7. Handshake mechanisms 8 . Sequential cells 9. Bath tub 10. Feasibility analysis

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Low-Power CMOS VLSI

CHAPTER OBJECTIVES In this chapter, you will be introduced to • • • • •

Sources of power consumption Architectural solutions Pipelining Clocks and control Approaches to low power design

11.1 INTRODUCTION Advances in VLSI fabrication in recent years have greatly increased the levels of integration making possible ứie implementation of highly complex algorithms such as Viterbi decoders, discrete cosine transforms, etc. Smaller integrated circuit device and feature sizes have lead naturally to increased speeds. Expectations and demand have grown for the continuing develop­ ment of both speed and ftinctionality. In particular, the communications market is expanding rapidly with each provider seeking advantage in enhanced system performance. However, this and other markets also have a requirement for low power consumption since many products are portable and so battery operated. Unfortunately, the rapid development in VLSI has not been reflected m developments in battery technology and so the impetus is upon VLSI designer to adapt emerging technologies to provide complex high-throughput low-power systems. A further motivation for low-power design is simply that there are limits to how much power a component can dissipate without the need for special cooling. High performance

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CMOS designs are already exceeding these limits and, for these, the costs of the ultimate system are dominated by the costs of the cooling apparatus. Significant market advantage can be gained by using low power ICs which avoid the need for this additional hardware. Fortunately, many aspects of the emerging integrated circuit technologies lend themselves to low-power design. Smaller feature size (developed for increased integration) also pro­ vide faster devices and smaller capacitances. Lower supply voltages (being developed to allow even more integration) also have a significant impact upon power consumption and speed. Increased levels of integration in themselves allow the designer to use the vacated area for exưa circuits to compensate for the device speed reduction due to lower supply voltages. The overall power consumption of an integrated circuit can be influenced at all levels of its design fabrication technology, cừcuit optimization, logic design, control and clocking sttategies, architectural partitionmg and layout, and the underlying system’s algorithm. This article will look at ứie power consumption of an integrated circuit and at how sfrategies for lowpower can be found at each of these levels. 11.2 SOURCES OF POWER CONSUMPTION There cire two types of power consumption in digital CMOS. The first may be thought of as useful m that it establishes information by charging and discharging signal lines; the second type is waste and comes from short-circuit ciurents which flows directly from the power sup­ ply to ground. The useful power dissipation is illustrated in Fig. 11.1 for a simple CMOS mverter. When tìie input signal is low, the p-type transistor is ON (and the n-type OFF) allowing the output capacitor to charge up to the supply voltage; when the input goes high, the n-type is switched ON (and the p-type OFF) and the output discharges to ground. The power dissipated in this manner is known as dynamic power smce it only occurs which the output switches, power is

T

L

In

r V

Out

V Fig. 11.1 Dynamic power dissipation.

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tìie product of voltage (V) and current. In this case, the voltage is the supply voltage (Vdd) and the current is the rate at which charge moves from the power rail to ground. The charge moves by charging and discharging tìie output; if tíiis has capacitance c then the amount of charge is (CVdd) and the ciurent is that charge multiplied by how often the ou^ut switches. Thus, dynamic power dissipation is: VDDĨ^iQVDDẢd

( 11.1)

where the summation is over each gate, and Ai is the average rate at which the output of gate i charges and discharges. The power due to short-cữcuit cuưent has the simple equation: Vd d ' ^ U sc

( 11.2)

where the sununation is over each gate and // JC is the average short-circuit cuưent flowing through gate i. Thus to design components with low power consumption, we must consider how to reduce tìie values of VpD, c , A and Isc11.3 SOLUTIONS 11.3.1 Reduce V0 0 The firststrategy isto reduce Vddsad this seems the bestplace to startsince it appears as a squared termin equation 11.1 (although the relationship iscomplicated by thefact that A is also voltage dependent). Clearly the design engineer does not normally have control over VpDHowever, developments in fabrication are already moving from the existing standard of 5 V towards a new level of 3.3 V and experimental processes are looking at even lower voltages. It is worth considering the issues in this development. 11.3.2 Power Supply Reduction One of the main motivations in technology development has been to increase the levels of integration by reducing feature sizes. However, as gate lengths are reduced (without reducing voltage levels) the electric field strength increases m tiie gate region. This leads to reliability problems as the high electric field strengths accelerate the conducting electrons to such speeds that they cause substeate cxurent (by dislodging holes on impact in the drain area) and actually penetrate the gate oxide. The latter effect gradually alters the characteristics of the device lead­ ing eventually to latch-up and so to destruction. There are three approaches to enabling further feature size reduction. The first is drain engineering in which the doping profile is crafted in the channel region to reduce the degradation due to hot electrons; the lightly doped drain (LDD) technique allows the smallest gate length. The second approach is to use new cừcuit techniques which avoid the high electric fields across individual fransistors. The thữd approach is to reduce

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ứie supply voltage; ứiis solution is much Ifae sinqilest fiv circuit designras but accqrtance has been delayed as ứie indusby wished to maintain ccwnpatihility with existing products. The reduction in V d d does not lead to a quadratic leductiiHi in power as mỉgỉit be tfaougjit from equation 1 since some the oứier terms are depradent iqKm die siqq>ly vohage. To under­ stand the actual effect, consider ữie activity level of each gate (A). This can be iee:qiFessed as the product of ữìe frequency ( / ) witii which new inputs are presented to a whole dicuit (for synchronous circuits, die clocking frequency) and a probability for each node (prị) ứiat it will change on any given cycle. The maximum possữ>ie frequency of a circuit (/max) represents tbe fastest throughput of data and ữìis is limited by its critical path or longest delay; thus is inversely proportional to cừcuit delay. This brings IIS to a common measure of cucuit quality: the pow er-delay product By leairangÌDg equation 1, w e have: Power delay _= /> _=Vdd^ 2 (C, p{r,)) ftBeoL JtBsa.

(11.3)

Thus, variation in VoD actually leads to a quadratic change in the power-delay product.

11J J Variation of the Threshold Voltage From the standard ttansistor current equations, ứie speed of a cừcuit is a function of ( V g s - K) where Vcs is the gate-source voltage (limited by Vũd) and Vr is ứie threshold voltage. Thus, it is also desirable to reduce tíie magnitude of the threshold voltages either to minimize tíie reduction m speed or to allow further reduction m VddThere are otíier reasons for reducing the ứưeshoỉd voltages. Rather than thinking about reducing one parameter at a time it is insttuctive to consider how to improve a technology as a whole. If the voltage levels (power and ứireshold) were scaled by ứie same amount as feature sizes ứien delay would be reduced by the same factor and power consumption (for ứie same cừcuit) by its square. This principle avoids the high elecữic fields which lead to the hot-electton effect because die voltage levels are reduced also; it is known as constant electric-field scaling. For example, a cữcuit designed in a technology of VoD = 5 V, IF, I = 1 V, and gate length = 1 |i could be reimplemented m one of Vdd - 2.5 V, I = 0.5 V, and gate lengứi = 0. 5 V wiứi twice the speed and a quarter the area and power consumption. Of course, all good ứiings come to an end. One feature which does not scale is the roll-ofif rate of sub-tìưeshold ciưrent as tiie following explains. In ứie weak inversion region (where Vgs is below V, ) tìiere is no drift current; however, there is diffusion current which has ứie form: h s (sub-threshold) a e x p ( F g 5 - Vỵ)

(1 1 -4 )

where V\- is ứ»e lowest gate voltage for the weak inversion region. The important point is ứiat ửiis exponential roll-off rate is not effected by voltage scaling. For silicon it is in the region of 70-90 mV per decade of current.

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Fig. 11.2 Threshold voltage roll-off.

Figure 11.2 shows how threshold voltage can be defined as the intersection between the linear ciurent and the axis, and how the sub-threshold cuưent rolls-off. If the threshold volt­ age is reduced (achieved by changmg the subsfrate and channel dopant concentrations) then the whole curve moves towards the left. Thus, for low threshold voltages, the device cannot be properly switched OFF (when Vos = 0 V) and there is significant short-circuit cuưent. As an example, a minimum sized gate for a “typical” 1.5 CMOS process with V d d = 3 V has Id s - 30 jiA at Vos - Vi with a roll-ofif rate of about 80 mV/dec. Thus, if the threshold voltage was set at 0.15 V, a component of one million such devices would have a power con­ sumption of about 1 w due to sub-threshold currents alone. The implication is that the thresh­ old voltage must be kept high to prevent significant power consumption due to sub-threshold currents at Vos = 0 V and this imposes a practical minimum of about half a volt. An alternative perspective is that by reducing V t to lower levels it would be possible to reduce Vdd even further. Thus, it may be possible to tolerate some short circuit cuưent because of the resulting reduction in dynamic power consumption. This has yet to be demonsữated. 11.3.4 Optimal Power Voltage The hot-electron effect establishes an upper limit on power supply voltage due to reliability criteria but, as suggested above, the low-power designer would prefer a lower limit. Here are two suggestions to be applied to any given technology. To optimise the power-delay product, it has been found that the optimal power supply volt­ age for a given technology is three times its threshold voltage. This seems intuitively reasonable

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in that it allows one threshold for each device type and ớne extoa for noise maigin. To avdd significant sub-threshold current, the minimum Vf shoidd be at least 0.5 V, ghãng an optimal power supply voltage of 1.5 V. ■ A second approach considers a phenomenon, known as velocity saturation, in tỉie velocity of the charge earners reaches a maximum with mcreasing elecưic field strengdis. ỈB other words, an increase in voltage does not increase tíie current ỉmd so does not improve &e device speed. This then sets a limit above which it is unproductive to raise tìie supply voltage and this limit depends upon the fabrication technology and the effective channel length. 11.3.5 Compensating for Lower Speed As the industry moves from the standard 5 V processes to ones with lower supply voltages, design engineers need to compensate for the loss of performance if they wish to achieve the same throughput. There are two architectural approaches: first, apply the standard speed opti­ misation techniques only more so; second, use parallelism. Pipelining is a standard technique for increasing the overall speed of a cừcuit by introducing clocked latches into sequences of combinatorial logic so that the data flow is staggered and controlled by a clock signal. Data may then be processed at a frequency ( / ) which is the inverse of tíie longest delay between any two adjacent latches. A designer will typically insert as many latches as are necessary to make the critical-path delay (J) low enough to allow the desừed frequency. If the target sup­ ply voltage is then lowered, then the cữcuit speed will be reduced and the critical-path delay will be increased. To compensate for this, a designer would then have to insert or redisttibute latches so that the desired frequency is again attained. Figure 11.3 illusưates how inserting exừa latches in the midst of a delay path in a cữcuit going at half its original speed allows a

-Delay T

Delay T

Fig . 1 1 .3 Pipelining.

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ibigner to maintain throughput, of course this will only be possible if the original cừcuit had ẵốt aừeady not “engineered” to peak performance. The idea of using parallelism is simply to have more operations being conducted at the ^ower speed to achieve the same overall performance. This is essentially a frade-oflf between éứcuit area and throughput. The use of parallelism is illustrated in Fig. 11.4. Here we assume àat tìie critical path delay Ợ ) through the combinatorial logic block has (nearly) doubled due to a reduction in the power supply voltage. To achieve the same throughput, the data is mterleaved so that new data is presented to one block while the previous data is still beữig processed by the other. The outputs of the two blocks are selected by a multiplexer so that the valid data is latched at the original frequency. Notice that although the total capacitance of the cừcuit has been (approximately) doubled, the term A (in equation 11.1) has been halved because of the speed reduction: these two effects compensate for each other in the dynamic power equation. Of course, this sfrategy may sound attractive in the context of rapidly increasing levels of integration, but in tenns of commercial viability it must be remembered that doubling the cữcuit area can have a large impact upon component cost. While many design specifications may demand this approach for the resulting speed, many will also preclude it on the grounds of cost. In both of these examples, the design has been modified to compensate for a halving in cừcuit speed resulting from a reduction in power supply. To illustrate with a very rough

Delay I T

Fig. 11.4 Parallelism.

o

Ì3 t

VlSIDesign

calculation, assume diat tỉiis is done with a standard s V proceK without changing any odier £abrication parameters. If speed is takoi to be prc^KxtKHial to (V d o - ^ t ) and = 1 V, t i^ a halving of speed is achieved by reducing Vd d fiom s - 3 V. IgDOTỈng the relatively small changes in Z c , A i due to the extra ciicuiby, the ^namic powar (xmsuiqptitMi is reduced to (3/S)^ = 0.36 its original value, ư ứte threshold voltage cmild also have been reduced to say 0.5 V, ứien tbe supply voltage could be reduced to 2.5 V and ứie dynamic power to wily 025 of its original value. 1 1 3 . « V o H a fe Sw ing

A final way of reducing power loss connected wiứi tìie siqjply voltage is to reexamine equa­ tion 1. TTie second VoD term actually refers to the voltage swing of the internal nodes, tf diis were reduced, then the total power consumption would also be reduced. One example of this concerns an internal bus architecture which is designed for operation at about 2 V with an internally generated supply for ứie bus itself. Modified tíuesholds, and special driving and sensing circuiứy, allow the bus to swing less that 1 V. This not only saves power m itself^ bat also increases the bus speed making operation at 2 V more attractive. 113.7 Reduce c The second sữategy is to reduce capacitance. This comes natiưally with smaller feature sizes and so a cữcuit designer will generally wish to use the minimum geometries possible in the given technology. 1

1

Partitioii Blochs

As a general rule, it is best to partition large blocks mto smaller ones. The design on the left in Fig. 11.5 is a large memory block; tíie shaded area is the address generation and bit detec­ tion circuitty, and the unshaded region is the memory array. The power calculation for each memory access is based upon ứie capacitances of ứie bit and word lines which run vertically and horizontally across the whole array. If, instead, ứie array is brokendownmto four sub­ units (each wiứi its own support cừciiitty) and only one unit is addressedwitheachaccess, then tiie product of activity and capacitance is reduced by a half. 11J.9 Locality of Reference There is anoứier architectural strategy ứiat can significantly reduce the capacitance of a design; it can be summarised in tìie phrase locality o f reference. This is a design philosophy m which signals are generated and used locally in terms of ứieừ physical location on the silicon sur­ face smce the further a signal has to ứavel, ứie higher is tìie capacitance of that coonection. Wĩửi signals being processed locally, there is greater opportunity for parallel execution. Wiứi

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parallel execution, there is greater throughput that could be ứaded off for a lower supply volt­ age and so lower power consumption. Designing with locality of reference is desừable for another reason related to the new fabri­ cation technologies. Communication within a component is achieved using metal interconnect. For large feature sizes, the RC delay on such lines is relatively small compared with the tran­ sistor delays in the cừcuit. However, while transistor delays scale down with feature size, the RC delays actually increase as fringing capacitance begins to dominate the total capacitance (and does not scale) and the resistance increases as the interconnect lines become narrower. Thus, in sub-micron technologies, the communication delays predommate. Thus, using local­ ity of reference as a design style avoids the major potential source of delay. Architectural strategies based upon this idea may include: processing of data locally to where it is stored, commiinication only witíi physically adjacent functional units, and dedica­ tion point-to-point buses rather than shared ones. Pigiưe 11.6 illustrates this idea. The architec­ ture on the left consists of a large number of units connected by a global shared bus; this is not uncommon. Consider the communication bus alone. The architecture on the right has fourteen

a Fig . 1 1 .6 Locality of reference.

K±

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much smaller buses that together have roughly the same total as the single bus on the left. If only one was active, then the activity-capacitance product would be l/14tìi; tf they were all active, then the power consumption would be tfie Sĩone but up to 14 times as mudi information could be transíeưed. It is clear that low-power systems will include the use of dedicated function specific cucuits which transform particular sections of the total algorithm onto localized areas of silicon— will not have central processing xmits communicating by global buses with laige memories. 11.3.10 Clocks and Control In architectures with distributed processing, tíie question aises as to whether there should be global control and clock signals. On the one hand, there needs to be synchromsation between communicating paữs of processors; on the other hand, the global distribution netwoik has a very large capacitance and is switched frequently. There are several possible sưategies. A new latch circuit was introduced in 1987 which allows ừT4e single phase clocking (TSPC). This implies that only one clock signal needs to be distributed whereas previously designs had relied upon having at least the complement of the clock available (either distributed in parallel or generated locally). Thus, by using TSPC, a design can greatly reduce ứie capacitance of its largest network. TSPC has already been used to implement extremely fast and power-hungry designs (e.g., the DEC Alpha) but, as we have seen above, the speed advantage could be traded off against power by designing for lower supply voltages. If the problem is the widely disttibuted clock signal, ứien one solution is not to dis&ibute it so wdely. In ứũs approach, regions of tíie component which are not being used have theừ portion of die clock network gated off. The drawback to ứũs scheme is the need to generate and distribute tìie clock control signals and the added design complexity in providing a synchronous clock sig­ nal on a network which is partitioned by function rather than by equal capacitance. A variation of tìiis approach is to disable sections of the power (rattier tìian the clock) distribution network. Self-timed circuits dispense with a global clock altogether. In this scheme, units indepen­ dently store their data, process it and generate a “ready” signal. Communication between units is achieved through a handshaking protocol where the next unit will receive the “ready” signal from the previous one, take the data into its local storage and then generate an “acknowl­ edge” signal. The first unit is then free to take in new data itself, if that data is available. In this manner, data is processed by local xxnits and passed throughout the component without a global clock. While this seems to remove the high capacitance-activity of the global clock line, in practice the power dissipated in tíie ready and acknowledge signals can be of the same order. Low-power designers should not assiune that self-timed logic is necessarily preferable to clocked logic. 11.3.11 Logic Design Another approach is to use logic families which feature low capacitance. One promising fam­ ily is tìie complementary pass-transistor logic (CPL). This uses networks of purely n-type

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pass-transistors to form logic functions (without any p-types). All signals are generated in complementary values and the outputs from the logic functions drive CMOS inverters. Fig­ ure 11.7 illustrates the CPL implementation of the sum function using 12 transistors instead of the 22 needed for a conventional implementation. The power advantage comes mainly from the reduced number of gates and so the lower capacitance. This technique has been successfully applied to a 4 V, 0.5 n CMOS process to implement a 16 X 16-bit multiplier. However, there are features with this technique of which a circuit designer should be aware. Due to the threshold voltage drop in the pass transistor network, the output high logic level is below the power supply. This means that the p-type transis­ tors in the inverters are only switched oữ hy { \ Vtp \ - \ v,„ \ ) leading to sub-threshold cur­ rents as described in the previous section. This can be reduced by using cross-coupled p-type pull-up ứansistors on the complementary logic outputs (leading to increased transistor count and reduced speed) or by using a special fabrication technology with a lower threshold volt­ age for the pass-transistor n-types only (0 V was used in 16 X 16-b multiplier). Thus, the best results using this circuit technique for low-power depend upon also matching the fabrication process to it. Two further design styles related to CPL have also been reported. One overcomes the prob­ lem of the threshold voltage drop by using full CMOS pass transistors. This still has bet­ ter speed performance than conventional CMOS and so would achieve a given throughput

B

B

1

V s

s

Fig. 11.7 Sum function in CPL.

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at ã lower voltage (and so power dissipation). The sec
One recuưent problem is the design of cừcuitoy to drive a relatively large cỉqiacỉtaiice (partic­ ularly external loads). The basic solution is a sequence of buffers with incieasiiig gate widths; the design issue is what should be the size ratio (a) of each successive buffer. With speed as the main consideration, the classical answer is a = e. M ứi inưiiisic output capacitance of the CMOS buffer included this value is known to be layout dependent and in the region of 5-6. However, if power is the main issue and the overhead in changing and dischargmg intermediate nodes is considered, the optimal ratio is layout and process dependent and is about 11-Ỉ2. The following table shows the example of different ratios for a buffer chain driving an 11 pF load from an initial buffer witii input capacitance of 0.Ỉ pF; “useiiil power” is that expended in charging the 11 pF capacitance itself, and “other power” is lliat expended on intermediate nodes. Ratio (a)

e

11.5

# inverters Useful power Other power Total power Delay

5 2.5 MW 5.4 MW 8.1 MW 5.5 ns

2.5 MW 1.5 MW 4.0 MW 6 .S ns

2

Thus, there is over a 50% reduction in power dissipation, and a similar reduction in layout area, at the price of only an 18% increase in delay. 1 1 .3 .1 3 Reduce

The thừd strategy is to reduce A: the average activity on each gate. Power is only expended when a node is switched; if switching is restricted to when information changes then power is minimised. This can be summarized by the phrase transition avoidance. As a first observation, this argues against the use of circuit styles which involve precharging and dischargmg as part of logic evaluation. 1 1 .3 .1 4 Glitch Avoidance

With some digital logic, there are spurious ttansitions (known as glitches) which occur due to partially resolved functions. Fig. 11.8 shows an example. If there is a unit delay through both of these gates then when the mputs both change from 1 to 0 , the output will change

Low-Power CMOS VLSI A: 1 toO

A B

a

343

B; I toO

± != r > x: 1 toO C: 0 to 1 to 0 Fig. 11.8 Glitches.

to a 1 as the logic is resolving before returning to a final value of 0. This wastes power. The problem is reduced in general by designing circuits so that there are equal delay paths between all of the gate inputs and the system inputs, thus equalising arrival times of chang­ ing signals. Of course, this is hard to achieve in practice and impossible if there is feedback in the circuit. A more important example of power loss through spurious transitions is the ripple adder. In this logic design, each bit-adder unit passes its cany to the next unit in a carry-chain; the value of its own input is not, however, valid until all the less significant bits have been resolved; thus each carry-bit in the chain may change (along with the coưesponding sum outputs) as the valid carry signal propagates along the chain. To avoid the associated loss of power, a differ­ ent adder design should be used. 11.3 .15 Poin t-to-Po in t Buses

This concept of ừansition avoidance can be viewed at the architectural level also. Suppose there are two independent slowly-varying digital signals within a component. If these are dis­ tributed on independent data buses, then transitions only occur when infonnation changes. If, instead, the two signals are combined by a multiplexer onto a single bus for distribution, there is also likely to be a transition when the multiplexer is switched (i.e., when the control signal changes). Although point-to-point buses incur an area cost due to the exữa interconnect rout­ ing, they save significant power by avoidmg transitions which occur when mixing independent signals. 1 1 .3 .1 6 Review ing th e Algorithm

The power consumption of a complex system can be greatly influenced at the algorithmic level. Normally, component power consumption corresponds to the usual algorithmic perfor­ mance criterion of speed since algorithmic speed is a function of tíie number of operations and this translates onto the component as the amount of switching. Thus, the programmer’s

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desire to reduce the number of steps in a computation will naturally reduce tiie power con­ sumption of its implementation. The idea of locality of reference may be m a p p e d duectly into algorithmic design through the use of certam progranumng languages. Concunent objectoriented languages (e.g., ADA and VHDL) allow die creation of software modules which mostly use locally declared memory and which allow communication between modules as an alternative to parameter passing by function call. It could be most effective for low-power system design if the underlying algorithms were developed in such a language from the very beginning. 1 1 .3 .1 7 Reduce

1st

A designer needs to consider short-cữcuit current in two ways: first, how to minimise what is unavoidable, second how to avoid what is unnecessary. 1 1 .3 .1 8 Resistive Netw orks

Pừstly, some logic styles deliberately use resistive networks foimed from transistors to estab­ lish the value of the output signal (e.g., pseudo-nMOS). These styles cannot be used for lowpower design. Secondly, some strategies for avoiding power loss involve generating multiple voltage levels using resistive networks either on-chip or at the system level. This static power loss must be carefully included in the evaluation of such strategies. 1 1 .3 .1 9 Switching Current

However, even conventional static CMOS has a source of short-circuit currents. Consider Fig. 11.9. As the input to a CMOS inverter changes, there is a period during which both ứansistors are switched ON that is when the input voltage is between (V d d - V tp) and Vm During this period, there is a short-circuit cuưent and so power dissipation. This is clearly dependent upon the rise time of the input signal. For poorly designed cừcuits, this power loss can be about 20% of the total power dissipation. A simple rule-of-thumb for designers is to size the transistors so that the delay in the output signal is the same as that of the input; with this sừategy, the short-cữcuit power loss is reduced to 1 - 2 % of the dynamic power dissipation. 1 1 .3 .2 0 Glitch Propagation

The example concerning spimous transitions in Fig. 11.9 above was explained m terms of unit time delays. In fact the problem is compounded in that the output glitch propagates on to other stages. In practice, this signal often takes the form of a slowly varying voltage which covers the centre of its range causmg short-circuit cmrents in the next gate. This is another source of power dissipation and a further reason to avoid logic glitches.

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Fig. 11.9 Short-circuit current on switching.

1 1 4 APPR O AC H ES T O LO W -P O W ER D ESIGN

The first decision the IC designer needs to make is the choice of fabrication technology. Low supply voltage is good. Small feature size is very good because of the low capacitance and increased device speed due to the short channel length. Fortunately, ứie first is tending to fol­ low the second because of the hot electron effect. The simple rule-of-ứiumb is to use the pro­ cess with the smallest feature size tíiat the project can afford. If there is access to a fabrication technology with multiple (and specifiable) threshold volt­ ages, then this might be chosen to support the CPL design style or one of its derivatives. The next decision is ứie design partitioning. A designer should avoid architectures based on central processing units, and always review the specified function. The aim should be to partition the function into small independent units (avoiding high capacitance interconnects) operating in parallel (raising throughput). The method is to apply the principle of locality of reference even if this means returning to tìie algorithmic development level. The final decision must be to re-evaluate the standard techniques for logic and cữcuit design. Designing for low power means that many of the old stand-bys are redundant and that new approaches must be developed. It requires a sfrong but subtle change in emphasis. For instance, in one sense the designer must abandon the imperative for speed which in itself leads to high power consumption. On ứie other hand, if a reduced voltage level is the main mechanism for power reduction, then all the old tricks for enhancing speed may be needed to compensate for the reduced drive capability. A second change in emphasis is that area is no longer as limited a resource as it used to be. Thus, with low power as the main criterion, techniques which require extra area are not unattractive. In particular, resoiưce sharing is less important particularly when it leads to addi­ tional switching.

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1. There are two types of POWCT consumptíon in digital CMOS. The first may be thought of as useful in that it establishes infonnation by charging and discharging signal lines; the second type is waste and comes fiom shoit-dicuit ciurents which flows dừectly from the power supply to ground. 2. The idea of using parallelism is simply to have more operations being conducted at the slower speed to achieve the same overall performance. 3. An ữnportant sữategy is to reduce capacitance. This comes naturally with smaller feature sizes and so a cữcuit designer will generally wish to use the minimum geometries possible in the given technology. 4. As a general rule, it is best to partition large blocks into smaller ones.

Fill in the Blanks 1. As gate lengứis are reduced ứie electric field sttength________ in gate legion. 2. Speed of the circuit is a function o f________ . 3 . _________ effect establishes an upper limit on power supply voltage due to reliability criteria. 4. The designer will insert as m any__________ as possible to make critical patìi delay low enough to allow desừed frequency. 5. ____________is the design philosophy m which signals are generalized and used locally in terms of theữ physical location on silicon. 6 . __________ is used for reducing the complex designing. 7. In buffer design, to drive large capacitance the solution used is sequence of buffers with________ gate widths. 8 . By designing the circuits with equal delay paths________ can be avoided. 9. __________ logic families are used for low power design. 1 0 . __________ transistors are used in low power design. Answers

1. Increases 2. V g s - V r

3. 4. 5. 6. 7. 8. 9. 10.

Hot electrons Latches Locality of reference Partitioning Increasing Glitches BiCMOS Variable threshold

Nanotechnology: Electronic Devices

CHAPTER

CHAPTER O B JEC TIVES

In this chapter, you will be introduced to • • • • • •

Nano-scale MOSFETs Carbon nanotubes Single electron transistor (SET) Quantum dots Molecular electronics Fabrication and characterisation

12 .1 IN TR O D U C TIO N

In the past 40 years, ứie metal-oxide semiconductor field effect fransistor (MOSFET) has become the basic building block for almost all computing devices. The steady growtii of their popularity is due to the steady shrinking of the feature size which at present has reached 0.1 micron. How­ ever, the laws of quantum mechanics and limitations of fabrication techniques may soon prevent the fiirther decrease of feature size. Hence, researchers are investigatmg several alternatives to the transistor for ulữa-dense cừcuitty. These new devices whose dimensions are on the order of tens of nanometres are called nano-devices and tìieừ science is termed nanotechnology. Unlike today’s MOSFETs, which operate via the movement of masses of electrons in bulk matter, the new devices take advantage of the qiiantum mechanical phenomena that emerge at the nanometre scale geometries, where the discrete nature of electrons ca'inot be ignored. How will such devices look like? What will be theữ operatmg principles'’ These are the questions that we discuss in this chapter.

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The devices are classified into three broad categories based on the operating principles and fabrication tephniques: • Carbon nanotube transistors • Solid state quantum effect devices • Molecular elecừonic devices. Devices in the first class are similar to ứie conventional MOSFET but are different in dimen­ sions and in the material (carbon nanotube) they are made of. The second and third classes both use quantum effects but are fabricated differently. The solid state devices use fabrication techniques similar to those employed for MOSFETs. Even though these devices use qiiantum mechanical phenomena they take advantage of the years of experience in the MOSFET fabri­ cation technology. Molecular electronics is a new approach that requữes new raw materials and a new operating principle. The incentive for such radical change is that molecules naturally occur in nmo-scale dimensions. Unlike nano-structures built from bulk solids, molecules can be made identically, cheaply and easily. Two significant challenges are to devise molecular structures that act as switches and to assemble those switches into precise structures needed for reliable computation. In this chapter, we first give an overview of the problems faced by fiuther shrinking of the current MOS technology. Then, we discuss the working principles of each class and the prob­ lems facing tíiem. We finally summarize by giving time prediction on when these devices may become a reality for mass produced integrated cữcuits. 12 .2 N A N O -S C A LE M OSFETS

In a digital circuit, a transistor is a switch that controls the flow of current through its channel depending on the state of the gate terminal of the device ON or OFF determines the type of the device. If voltage at the gate is used to control the cuưent through tìie channel the device is called a Field Effect Transistor (FET) and if a cuưent at the gate is used as the control then it is called a Bipolar Junction Transistor (BJT). A Metal Oxide Semiconductor FET (MOSFET) is a variant of the FET and is the predominantly used transistor in today’s cừcuits. In this section, we will examine the working principle of the device to study the problems of miniaturizing the MOSFET below 0.1 micron. 1 2 .2 .1 Structure and Operation o f a M OSFET

The MOSFET is a three terminal device with source, drain and gate terminals.The structure of a MOSFET is shown in Fig. 12.1. It is built on a crystalline substrate of doped silicon. Pure silicon is a poor conductor so dopant impxưities, such as boron or arsenic, are infroduced into silicon to create an excess of mobile positive or negative charges. Negatively doped (n-type) silicon contains excess electrons and positively doped (p-type) silicon con­ tains electron vacancies known as holes which act as positive charge carriers.

Nanotechnology: Electronic Devices

Gate

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Polysilicon Drain

Fig. 12.1 An n-type MOSFET.

As shown in Fig. 12.1, an n-t5^ e MOSFET contains a lightly doped p-type channel between two heavily doped n-type source and drain regions. A metal electrode separated from the chanliel by an insulating oxide barrier serves as the gate terminal. The voltage at the gate alters the elecứic field through the channel of the MOSFET and hence the flow of ciuTent through the device. When the voltage on the gate is low, the channel cofltains few negative charge carriers and very little current flows. However, if the gate is maintained at high voltage, more carri­ ers are attracted to the region below the gate and hence the channel freely conducts resulting in larger current through the device. Thus, the MOSFET acts as a two-state device, switching between on (high channel conductivity) and off (low channel conductivity) states based on the voltage of tíie gate tenninal. Integrated cữcuit technology has progressed over the past three decades based on the sim­ ple principle of scaling. The MOSFETs can be made smaller by just shrinking all the dimen­ sions of the cứcuit including wữe lengths and widths and transistor sizes. The parameter that determines the size of the cừcuit relative to the previous generation cừcuits is the feature size. It is the minimum conductor (wừe) width that must be fabricated on the chip. All lengths are multiples of this smallest measure. In order to fit more transistors on a chip of a given area designers would like to decrease the feature size. The feature size has been decreasing con­ tinuously over the decades and has now reached 0.1 p.m. This has made possible dense chips like the Intel Pentium. However, further scaling down could cause problems as discussed in the next section. 12.2.2 Problems w ith Nano-Scale MOSFETs

Despite major challenges, the industry and many research groups want to ftirther decrease the feature size and extend the MOSFET technology. The MOSFET-based CMOS technology has been the mam stay of the industry for several decades and shifting to a new technology involves a major investment. There have been working transistors fabricated with a feature size of 25 nm, but large-scale cữcuits design presents problems that are yet to be solved.

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12.2.2.1 High Eleark Fields The power supply voltage cannot be decreased m proportion to ứie channel lengtíi (see next subsection) and hence the scaling down increases the eledric field sfrength across die gate oxide. For 0.Ỉ )xm channel length devices, the oxide field has reached a m axim um of s MV/cm, while the field in silicon has exceeded 1 MV/cm. These values will further increase as the channel size reduces into the nanometre dimensions. The high fields produce higher leakage currents ửat degrade the device performance. In worst cases the field causes avalanche breakdown of the bar­ rier and the electrons are conducted freely, producing current surges and damage to the devices. 12.2.2.2 Power Supply and Threshold Voltage As the MOSFET channel is scaled down one would like to proportionately reduce the sup­ ply voltage to keep the active power and electric field within reasonable limits. However, the threshold voltage cannot be scaled down much. This is because the quiescent state power, i.e., the power consumed by the device in the steady state should be controlled. The major power consumed in this state is due to leakage current through the device and to reduce that, the threshold voltage is kept high. But the large threshold voltage results in much finer demarca­ tions between on and off states and there will be a higher probability that the device would enter an undetermined state, which is neither on nor off. Besides the noise margin, inductive effects also make voltage scaling a critical problem. 12.2.2.3 Heat Dissipation Transistors expend their energy in the form of heat in the resistive parts. This heat, if not dissipated properly, can create hot spots on the circuit. These hot spots cause the material to overheat, resulting in deteriorated performance and malfunction, or even destruction, of the device. 12.2.2.4 Interconnect Delays The decrease in wire width increases the resistance and hence increases the delay. Shrinking would increase the interconnect delays enormously in comparison to the gate delays. The pur­ pose of scaling is not only to increase the density of the chip but also to increase its speed. The devices may not be much faster due to large interconnect delays. 12.2.2.5 Vanishing Bulk Properties The doping of the substrate is done by using an optical filter during the fabrication procediưe. As the feature size decrease the finer doping regions are tougher to demarcate and hence the bulk may be non-uniformly doped at such small scales. This can fail to create transistor would malfunction. Ĩ2.2.2.6 Shrinkage of Gate Oxide Layer For a 0.1 Jim COMS devices operating at 1.5 V, an oxide thickness if 30Â is needed. This coưesponds to roughly ten layers of silicon atoms. With such a thin oxide layer quantum

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mechanical tunnelling talffwt place and hence there is leakage through the gate. This decreases tíìe feasibility of reducing the oxide thickness fiuther. The above-mentioned obstacles are due to inefficient doping methods and the onset of quantum effects. The indusưy is toying to ckcumvent these obstacles and make devices that would account for the quantum effects. An eifort in this dữection is the silicon on insulator (SOI) device where the substrate is M l insulator that is partially depleted. Another approach is to use silicon germanium (SiGe) instead of the conventional silicon to make MOSFETs. Fiưther explanation of these devices is beyond the scope of this paper. The problem is not in the basic concept of the transistor but is caused by the use of silicon as the material. Hence, some research groups have used tiny tubes of carbon for making switching devices that are smaller and faster than the silicon MOSFET. This is the focus of the next section. 12.3 CARBO N N A N O T U B E F IE L D E F FEC T TR AN SISTO R (C N FET)

A carbon nanotube device is similar to a MOSFET in that a gate is used to control the flow of cuưent through the device by varying the field through a channel. The innovation here is the mechanism of fransport of electrons from the source to drain. Instead of having a channel whose field can be confrolled by a gate electrode, these devices have a tiny structure known as carbon nanotube. This tube can be made conducting or semiconducting based on whether it is sfraight or twisted. These devices are much smaller and more compact than silicon MOSFETs. This section explains the basic physics of a carbon nanotube and its role in the working of a CNFET. 12 .3 .1 Basic Physics o f th e Carbon Nanotube

A carbon nanotube is a cylindrical rolled up sheet of graphene, which is a single layer of graphite atoms arranged in a hexagonal pattern like a chicken wire mesh. Its sừucture is shown in Fig. 12.2. Because of the hexagonal structure the graphene molecules belong to a class known as iullerenes, which are close caged molecules containing only hexagonal and pentagonal inter-atomic bonding networks. Their hexagonal sttucture gives them great tensile strength and elastic properties. The tubes are tough and when bent or squeezed, spring back to their origmal shape. They also transfer heat very efficiently and hence are useiul in circuits as they can be cooled faster. Theừ elecừical conduction properties are also imique. They can be made to perform as a metal or a semiconductor depending on the way they are rolled. We define a few basic terms that will be useful m understandmg the carbon nanotubes. Con­ sider the unrolled the carbon nanotubes. Consider the unrolled nanotube shown in Fig. 12.3. The two unit cell vectors aj and a2 are as defined in the figure. A chữal vector is defined as the vector normal to the cữcumíerence vector in tìie dữection in which it is being rolled. Hence, the chiral vector is the horizontal vector from one open end of the tube to the other after it is rolled. The cMral vector can be described in terms of the unit vectors as shown m the Fig. 12.3. c = n a \+ ma2

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ir

#-

#• T , e r ■ :r ^ w e ¥ #■

vi'

i I

Fig. 12.2 A single walled carbon nanotube.

where n and m are integers. The nanotubes is described by these numbers as («, m). For example, the tube shown in Fig. 12.3 would be a (4,3) tube if it is rolled along the chừal vec­ tor shown. To distinguish between the metal and semiconductor tubes, a simple thumb rule has been established: • If n-m is divisible by 3, then the tube is metallic. • If n-m is not divisible by 3, then the tube is a semiconductor. The chkality also gives us a basis for dividing the tubes into three different classes. Consider the tubes shown in Fig. 12.4. A carbon nanotube described by («, m) can be classified as: • Zig-zag if either n = 0 or w = 0 • Armchair if « = /M • Chiral if n Ỷ m

By combining with the condition for the metallic properties, we see that the armchaữ type is always metallic whereas the other two types can be either metallic or semiconducting based on their chiral condition. The tubes can be made into single walled nanotubes (SWNT) or multi walled nanotubes (MWNT). The MWNTs are SWNTs wrapped one over the other. Both types of tubes can be used to make CNFETs, as we describe in the next section.

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Fig. 12.3 Chirality of a (4,3) carbon nanotube.

Side view

(a)

Front view

(b)

(c) Fig. 12.4 Three major types of tubes (a) zig-zag (b) armchair (c) chiral.

12 .3 .2 Basics o f CNFETs

Externally, a CNFET is similar to a MOSFET. Both have three terminals, source, drain and gate. A carbon nanotube between the source and drain forms the channel. The gate controls the field across the nanotube, thereby controlling the cuưent flowing from source to drain. The channel of a conventional MOSFET is substituted by the nanotube in a CNFET.

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The first generation CNFETs contained gold electrode upon which ứie tube was laid to provide the channel. The gate was located on either side or imdemeath ứie tube, separated by an insulator. A problem with this design was that tiie tube was exposed to the aữ and hence due to a property (see next paragraph) of the tube it could opoiate only as a p-type bansistor. The gate oxide also had to be thick in order to provide tíie insulation, which in turn increased the size of the device. The CNTs are naturally occurring p-type devices when they are exposed to aừ. This is because the oxygen in the aữ causes the Fermi level at the contacts to shift closer to the valence band. The result is that the holes see ã smaller banier than tíie electrons, and thus are able to tunnel through the device faster than the electrons. Since a conductor of holes is a p-type device, the undoped CNFET exposed to aừ gives a p-type CNFET. The second generation CNFETs were a major improvement. The CNFET looks as shown in Fig. 12.5. The gate elecfrode is placed on top of tíie tube to isolate it from tìie atonospheric aừ. This decreased the overall capacitance of the cừciiit as well. In order to design conventional CMOS ckcuits, we need an n-type device along with the p-type. This can be done m two ways, annealing and dopmg. Annealing is the process of heating tibe tube to a temperature of 4500"C in nỉti-ogen envi­ ronment for a few seconds. This process drives out the oxygen absorbed by the tube and hence shifts the Fermi level up to the conduction band and the barrier seen by the elecữons is reduced. Hence, the electrons are more freely conducted than the holes by the tube, which behaves as an n-t)^e device. Another technique to convert a p-type tube to n-type is doping. In tìũs technique, tíie tube is doped with an elecừon donor such as potassium. The extra elecừons reduce the banier strengtìi and once the tube is doped heavily enough, the electrons tunnel through the barrier and ứie device acts as n-type.

Nanotube

dioxide Silicon wafer Gate oxide Fig. 12.5 Structure of second generation CNFET.

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Although we have succeeded m converting the p-type tubes to n-type, exposiưe to air will revert the tubes back to theữ origmal p-type behaviour. Hence, the tubes need to be covered ionce they are converted to n-type. This is mother reason why the second generation CNFETs are more successM, as the gate provides a natural cover to the tube. 12.3.3 Fabrication

CNFETs were envisioned and created in laboratories over 10 years ago, but the real hurdle was the lack of a mass production technology that would enable integrated cừcuits to be made. The main problem was that the tubes cannot be placed at exact locations automatically and there was no way to know whether a tube placed at some specific location is going to be metallic or semiconducting. This proved a major hiưdle until the Avouris group at IBM came up with a method called constructive destruction. They use MWNTs with metallic and semi­ conducting tubes rolled one over the other. Once the MWNTs are placed in the right locations the unwanted tubes are peeled off. If a tube needs to be made metallic, then the metallic tube is left and the semiconducting tube is destroyed through chemical depositions. If a semicon­ ducting tube is required at a location, then the metallic tube in the MWNT is destroyed. In this fashion, the type and location of tubes in a circuit no longer remains a problem.

UA SO LID STATE Q U A N T U M DEVICES Why ckcumvent the quantum effects when they are an eventuality? Can we use them to our advantage in building new devices? These are the questions that motivated some pioneers of nanotechnology. A number of nanometre scale bulk effect semiconductor devices have been proposed as replacements for the cuưent MOSFET. These take advantage of the quantum effects. An essen­ tial common feature of all these devices is a small island in which eỉecừons are confined. This island is analogous to the channel of a MOSFET. The extent of confinement of the electrons in the island defines two subcategories of such solid-state devices: • Single electron transistor • Quantum dots The composition, shape and size of the island gives the device its distinctive properties. Confrolling these factors permits the designer of the device to employ quantum effects in differ­ ent ways to control the passage of electtons on to and off the island. In this section, we first explain the common principles and terminology of these devices. Then we explam the differ­ ent classes of devices.

MAA Islands, Potential Wells and Quantum Effects The place of confinement of elecfrons is called the island. The smallest dimension of the island ranges from 5 to 100 nm. The island is embedded between two narrow walls of some material,

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or an insulating defect zone in the substrate. These bomđráes cxeate potmtial om gy bairiera, which impede the movement of electrons tíưougỉỉ liie iitĩaBiá, Tlwa is shown in Fig. Ỉ2.6. ElecừoDs can cross the potential hairier if tbey attain higjia' enogy tfian die potential energy of wails of the barrier. Within ứie island die electrons form a puddle that is much smaller than the dimensions of the island. The puddle is sumnmded by a dq>letíon region because electrons in the puddle are repelled from surface charges that collect on ứie boundar­ ies of the island. Thus, the physical features tfiat form the island need to be Ẽ b r ìc a te d onich larger than the requừed island dimensions. This factor might prevent further miniaturization of quantum effect devices. There are two useful properties exhibited by electrons confined to these islands. The first is the qu^tisation of energy levels. In a MOSFET an electron can occupy any energy level in ứie channel as energy levels are continuous. But in the quantum case, the energy is quantized in tíie well regions. In Fig. 12.6, this is ứie region where the energy of the electoon is less than the energy of the wails, which in our case forms the island. This means that the electron can occupy only certain specific states that satisfy Schrodinger’s wave equation. K“a well has large number of these energy levels, then the electron has higher probability o f staying in one of them, but if a well has very low energy levels then there is low probability of the electoon staying in the region. For nano-scale devices, if an electron needs to cross the barrier onto the

Semiconductor

Narrow B a n ^ ^ Smicondu

Barrier Mde Bandgap Semiconductor

Semiconductor

Barrier Wide Bandgap Semiconductor

Fig. 12.6 Potential structure of a quantum well showing the allowed and unoccupied energy levels on either side of the wall.

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island, it needs to be charged enough to occupy one of these energy levels. Hence, it is pref­ erable to have larger number of energy levels on either side of the island. Thus, quantisation needs to be considered while designing these devices. The second effect is tiinnfilling. If the potential barriers are thin enough the electrons can (70SS them without any external eneigy source and this effect is called tunnelling. However, for an elecừon to tunnel through a barrier, there must be a vacant state with the same energy on the otfier side of the barrier. Nano-scale devices use this fact for the conduction of cuưent by designing thinner baniers and forcing tiumelling as we shall later see. These two effects, energy quantisatíoQ and tunnelling sừongly influence the working of nano-elecừonic devices. When a bias voltage is applied across the island, it induces mobile elecừons in the conduction band of the source region to attempt to move through the potential well in the island region to get to the region of lower potential in the drain region. The only way for electron to pass through the device is to tunnel on to and off the island through the two tunnel baniers that define the island and separate it from tìie soiưce and drain. This is illusfrated in Fig. Ỉ2.6. Figure 12.6 shows the allowed energy levels in various regions of device. The bulk semi­ conductor has closely packed energy levels but the island region has very sparsely spaced ones. This confine the number of electrons allowed onto the island. Tunnelling can occur from die source to the drain only if there is unoccupied energy levels this would not prove to be a problem for these devices. So the real barrier is tìie first baưier from the source to the island. Once an elecfron is able to teavel from the source to the island it is usually free to complete its passage through the device by tunnelling once again from the well to the drain. Before we study various devices we need to leam a few basic principles of tunnelling. Consider the barrier graph shown in Fig. 12.7. It shows the potential banier distribution of a two-tunnel banier device. It is crucial to the operation of the tunnelling devices that the energy of the quantum states in the potential well on the island can be adjusted relative to the bands in the source and the drain. Since the source contains eiecưon, we know that the source conduction band is occupied (metals have occupied conduction bands). The allowed energy levels in the well are as shown. As we increase the bias voltage across the island, the energy of all the states in the well is lowered relative to the energies of the electrons in the source. When the bias voltage is suf­ ficient to lower the energy of an unoccupied one-electron quantum state inside the well to be withm the range of energies for the source conduction band, the quantum well is said to be in resonance or “on” state and cuưent can flow onto the island and out to the drain. If the energy is not sufficient the electton are blocked and the device is said to be “off”. This two state operation of the device determined by an applied bias characterises the operation of a two terminal resonant tunnelling device. The quantum dot (QD) and the single-electron transistor (SET) are resonant tunnelling devices. The point to note here is the decrease in potential of the energy levels in the well relative to those in the source. This can also be done by adding an exữa gate termmal that lowers the potential as shown m Fig. 12.7(c). This gate is the thứd terminal that is added to the paữ of tuimel junction an SET. The SET is coniined only to a smgle dimension barrier, but if the confinement of electron is done in all

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(a) Occupied conduction band

Source

(b)

(c)

\

Occupied conduction band

J Source

Lowest energy states in well Occupied EQnductian band

Occupied TVansmitted conductionband Electrons Occupied' conduction band Drain

Source

Transmitted Electrons Occupied conduction band

Drain Potential lowering due to gate voltage

Fig . 1 2 .7 Potential structure of a quantum well showing the allowed and unoccupied energy levels with various

bias conditions (a) small source-drain voltage-no conduction (b) large source-drain voltage-conduction (c) small source drain voltage, large gate voltage-conduction.

three dimensions, then we have a quantum dot. As we see the two devices are different and yet quite similar m theừ operation principles. These are tìie governing principles of both the quantum devices. The methods by which the well to confine the electron is created and ứie means by which the bias is applied is what distinguishes one device from another. 12 .5 S IN G LE-ELEC T R O N TR AN S IS TO R (SET)

This section describes the principles and physics behind the SET. We present typical I-V char­ acteristics and the conductance graphs of the device. 1 2 .5 .1 Principle o f th e SET

The structure of a SET is shown in Fig. 12.8. The device consists of two tunnel junctions characterised by a jimction are separated by an island which is coupled to a gate bias, while a source-drain bias is applied across the tunnel junctions as shown.

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Source

Gate oCg

R't, C-)

Dram Fig. 12.8 Schematic of a SET.

A SET can be visualized as having a double baưier potential. The double junction is a cừcuit consisting of two tunnel junctions in series, which form an island between them. The junctions are biased with a voltage source connected between the source and drain. For very small bias no ciurent flows as the electrons do not have enough energy to overcome the bar­ rier. We initially assume that no bias voltage is applied to the gate terminal. Increasing the source to drain bias voltage steadily, at some point it becomes possible for an electron to tun­ nel through the first junction. This elecừon enters the island thus increasing the energy level of tíie island from Ne to {N + \)e. This in turn forces an extra electron to exit from the second barrier, thus returning the island to its earlier energy state Ng. Since the source to drain bias voltage has not changed, another electron enters the island through the first junction resulting in a steady cuưent through the double junction. If we make the second tunnel junction barrier higher than the first barrier, then certain number of electrons will have to be accumulated on the island before any electron can tunnel through to the drain. This phenomenon of blocking an electron from immediately leaving the island is called coulomb blockade. The source to drain voltage increase necessary to overcome the coulomb blockade is called the coulomb gap voltage. As we increase the drain source voltage, due to the quantisation of the electronic charge an increase in cuưent occurs only at increments of the coulomb gap voltage as depicted by the conductance graph of Fig. 12.9. Hence, the waveform looks like a staircase called the coulomb staircase. Suppose, we keep the drain source voltage below the coulomb gap voltage. If the gate voltage is increased that increases the initial energy of the system, while the energy of the island with one excess electron decreases gradually. At the gate voltage coưesponding to the point of maximum slope on the coulomb staircase, both of these configurations equally

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I on

Coulomb Gap Voltage

Source-Drain Voltage

Fig . 12 .9 Plot of conductance of an SET as a function of source to drain voltage.

qualify as the lowest energy states of the system this lifts the coulomb blockade, allowmg the electrons to tunnel into and out of the island. We find that the coulomb blockade is lifted when the gate capacitance is charged with the exactly minus half an electron, which is not as surprising as it may seem. The island suưounded by insulators which means that the charge on it must be quantized in units of e, but metallic gate is supplier of plentiful of electrons. The charge on the gate capacitor merely represents a displacement of electrons relative to a background of positive ions. More about the mathematics of the set is explained in the next subscription. If we further increase the gate voltage so that the gate capacitor becomes charged with -e, the island again has only one stable configuration separated from the next lowest energy states by the coulomb energy. The coulomb blockade is set up again, but the island now con­ tains an excess electron. The conductance of the SET therefore oscillates between minima for gate charges that are multiples of e and maxima for half integer multiples of e. We have a device that switches between conducting and nonconducting stages by the addition of single elecữon at gate terminal. Hence, it can be used for building logic circuits sunilar to CMOS cữcuits.

12 .5 .2

l-v Characteristics o f SET

In the previous subsection, we dealt with operatmg principles of the SET without any math­ ematical analysis. Now we will deal with the actual physics of the SET and the equations that describe the complete operation of the device. Consider the double junction system shown in Fig. 12.10. The parameters shown are the characterizing values both junction shown in cừcuits. Assume initially that C \« C 2 and

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i?2 >^2

I »'^ĩ rri

m + dQ

Fig. 12.10 Circuit of an SET.

R i« R i so that the tunnelling rate through the first junction is far greater than that through the second. Set the external source to drain bias voltage V so that the charge flow from left to right is preferred, and increase the bias voltage above the coulomb gap voltage. The governing cừcuit equations are: Vi = -

Cl

V -

Q+Cz

V2 =

C

Cl +

ne + ỒQ C1+C2

l

■v+ Ư2

ne + ÔQ Cị

+ C2

where ne + ỎQ is the charge on the central electrode. This is the result of n electrons on the electrode due to tunnelling events, and an initial charge 5Q due to external voltages coupled to the electrode via the gate capacitance. For given voltage V, electrons will tunnel onto the central electrode until Vị becomes smaller than e/(Ci + C2) at which point the junction becomes coulomb blockade. Because of the tunnelling rate assumptions above, the blockade condition is always reached before we need to consider charge tunnelling out through C2. Since tunnelling rate through C2 limits and governs the cuưent through the device and since V2 is pinned by the blockaded condition of junction 1, current through the device remains constant for a range of external V. In order to raise the number of elecữons on the cenữal electrode by 1, Vị must be raised by AVi =

e

^

C2 A

Q + C2

C

l +

F =

>

C 2

which in turn allows a cuưent increase.

/?2

(Q + C '2 )^ 2

A

r

=

-

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Thus, the I-V curve of such a device shows distinct steps of widtfi AV and height AI. As the junction parameters are brought nearer, Ci~C2 and Ri~R2 , ứie tunnelling rates through the junctions become comparable, blockade conditions are less likely to build up and the I-V curve tends to be linear as shown in Fig. 12.11.

12 .5 .3 Conductance o f SET

Consider the schematic of the SET shown in Fig. 12.10. Let the external bias applied to the drain be zero (V=0). The capacitive energy of ứie cenừal electrode is ^ _ {ne + dQ) (ne + dQ) (Q + C2 Ý where n is the net number of electronic charges that have tunnelled through the first junction and ÒQ is a fractional charge due to the gate elecfrode. If we plot the electrostatic energy of the central electrode as a function of n we expect the curve to be parabola. The curves for limiting values of ỖQ are shown in Fig. 12.12. Note that due to the discrete nature of the tun­ nelling only those energies with the solid dots are allowable. The tunnelling activation energy is defined as the energy required to add another electron to the island. It is given by AE = E(n + 1) - E(n)

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Fig. 1 2 .1 2 Energy diagram illustrating the effect of fractional charge on the central electrode of a double junction.

Charge can only change by an integral amount, into the states marked by solid dots.

when ỖQ = 0, we have E=

(Q + C2 Ý

which is the coulomb blockade energy. This is the normal condition that we have seen already. Now for 8 Q = e/2, the activation energy is reduced to 0 and both energy states E(n + 1) and E(n) are degenerate. Hence, the charge fransfer can occur freely and the conductance has a peak at this value of charge. We must note that this particular point of increased conductance is precisely the I-V curve has a step on the coulomb gap voltage at the gate terminal. 12.6 Q U A N TU M DOTS (QDs)

In the previous section, we have seen the operation of the SET and also noted that the back­ ground charge is a problem. At such small dimensions even a single-electron matter and hence the flow of electron cannot be guaranteed to be an exact number that we desire. Essentially, for logic operation we do not need the actual flow of elecừons. We need an efficient encoding system that fransfers the state of a dot through an aưay of devices. This is where the quantum dots come into the picture. Quantum dots are devices with tunnel junctions in all three dữnensions of the island. Thus, we have an elecữon box, which the excess elecứon is confined to. This excess electron determines the state of the system and when these dots are aưanged in cells it is possible to design logic circuits that can function efficiently. This will be the focus of this section. First, we will describe the structure and operating principles of a quantum dot. Then we describe a quantum cell aưay and its two state operation. We then explain the proce­ dure by which circuits and interconnects can be designed using the quantum cell aưays. 12 .6 .1 Physics o f a Quantum Dot

The quantum dot has become a buzzword in the industry and is often used to denote many nano-scale devices. But the widely accepted definition of the quantum dot is an area or region,

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which an electron can be cooiined to. The quantum dot receives its name from ứie fact that it is confined by baưier in ail three dimensions. In contrast, the SET is a two-dimensional device where the electroD movCTient is in one direction from the source to drain along a single dimension. But in quaatum dot the eneigy spacing is different in all three dimensions X, y and z. Hence, die dot is a potential well in all three dimensions. Since the dữection does not matter, we do not care for ứie flow of charge anyone. The presence of an excess electron means a change in state of tìie device. The dot-like island may be made of either metal or semiconductor. It can consists of small deposited regions, self organized droplets or nano-crystallites grown or dq)osited on a film. Using the physical ideas outlined above, we observe that making an island short in all three dimension leads to widely spaced energy levels for an electron on the island. 12 .6 .2

l-v Characteristic o f a Q u a ntu m

D ot

The I-V characteristic of a quantum dot is shown in Fig. 12.13. As we mcrease the bias volt­ age across the dot, two interesting things happen. Fừst, the current rises to a level where ứie electron flow one at a time. Thus, as we increase tiie bias voltage there is a senal of steps in which the current rises. These steps coưespond to the different energy levels for the same electron. But as the bias voltage is increased above a certain level where more than one elec­ tron can be accommodated in the dot, then the cuưent is increased by anotíier steep rise and the intermediate steps occur again. Essentially the smaller steps are for the different energy levels available in the dot and the larger steps are for the number of electtons that can flow at the same time. This shows that these possible to put as many are as few electrons in the dot by varying the squeezing voltage. That is why, the quantum dots are sometimes referred to as artificial atoms. The dots act as a nucleus that attracts elecfrons and the valency of the atom (or dot), is controlled by the external gate voltage. Hence, we have our own way of creating Source to Drain Current

Source to £>rain Bias Voltage Fig. 12.13 l-V characteristics of a quantum dot.

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an atom with the desừed niunber of electeons frapped m it or revolving around it. Thi ứie creation of new devices ứiat are not like the transistor but are useful in computii are the quantum cell aưays that are discussed in the next section. 12 .6 3 Qu antu m Cell Array (QCA)

A quantum dot by itself has very little computing value. It has similar problems as the SET. The current flow is too weak to create any significant logic function change. The device pro­ posed for computing is the qiiantum cell aưay (QCA) or quantum cellular automata. This is a set of four dots as shown in Fig. 12.14. Sometimes a fifth dot is added in the centte but we will ignore it as it does not change the functional value of the aưay.

The array consists of four tunnel barriers between the dots and eight baniers on the outside of the barrier. The cells are designed such that the bamer on the outer side of the cell are much higher than the inner barriers. Suppose, there are two excess electrons confined in the whole array. Since electrons repel each other, they tend to stay as far from each other as possible. Hence, they occupy the diagonal dots as this gives them the largest separation. By altering the inter-barrier potentials the electrons can be shifted from theừ positions as shown in Fig. 12.15(a) to those in Fig. 12.15(b) the electrons are separated by their maximum distance and hence are in equilibrium. Thus, we have two states in which the cell can be polarized. These two states can be classified as the two binary values. Let us suppose that the state in Fig. 12.15(a) is 1 and that in Fig. 12.15(b) is 0. Now let us see what happens when two cells are placed close to one another. Consider the setup shown in Fig. 12.16. Let the initial polarization of a cells be as shown now if they are bought together and the configuration m cell 1 is changed by manipulatÌDg the inter-bamer potentials, and then due to the repulsive forces of the elecfrons, the electt-ons in the cell 2 are also polarized in the same fashion. We have a device that had two state of opera­ tion and can transmit it to a neighbouring device. It thus sounds like a transistor. This gener­ ates a whole range of possibilities for designing logic cữcuits. Some of these are described in the following subsections.

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o • #o

• © © • (a)

Fig. 12.15 (a) A QCA depicting logic state 1 and (b) QCA depicting logic sbite 0.

Cell 1

Cell 2

Cell 1

•o ( ỏé ( (b)

o# om • o •o w Cell 1

Cell 2

•o •o o® 09 (c) Fig. 12.16 Transmission of set through cells (a) shows a stable configuration of cell array. (b) cell 1 is changed in value by changing the inter barrier potentials; this is an unstable configuration (c) the cell 1 forces cell 2 to be of the same value this is stable configuration.

1 2 .6 .4

Quantum Wires

A quantum wire can be assembled as a series of quantum cells. By changing the polarization of the cell at one end of the wire the whole wừe can be made to ữansmit the uiformation to the other end. Though the unconventional, this is an effective way to send the information over a physical distance. 12 .6 .5 Quantum Com puting

To compute a logic function using the cells, we can construct a majority gate. Consider the config­ uration. This is an inverter. If the input is polarized in a certain fashion, then the output is always polarized Ũ1 tìie opposite fashion. A majority gate can be consttucted as shown in Fig. 12.19.

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Output

Input

O0 o« om o« o# 0#

• o • o •o •o •o •o Fig . 1 2 .1 7 A quantum wire as row of cells.

omom

Input

0

•o •o •o •o o* 0« • o •o 09 O0 •o •o •o

Output

1

Fig . 1 2 .1 8 An inverter gate in QCA logic.

1 Input A

mo om om o # 0 om mo mo • o om mo ^

Input B

Device Cell Output

A—

OuẠut

(b)

0

Input c (a) Fig. 1 2 .1 9 A majority gate in quantum cellular automata logic (a) the cell array showing that the majority of the

electron interactions determine the value of the cell and (b) symbol of the gate.

The cells are aligned in a fashion to minimize the repulsive forces from the adjoining cells and hence the output will align to the state, which most of the inputs are aligned to. This allows a design of logic function using neural networks. Further explanation of such imple­ mentation is beyond the scope of this book.

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VLSI Design

1 2 .7 OB STAC LES FO R T H E S O LID STATE Q U A N T U M DEVICES

Although the solid state quantum devices show great promise, just like any nascent technology, they pose problems to solve before real industry applications. We outline some problems. • Background charge: Random charge accumulates in the semiconductor regions close to the qxiantum devices. This can make the device inoperable as it would aher or damage the intended charge distribution. Improved materials such as silicon on insulator (SOI) could alleviate this problem, but this not been tried yet. • Extreme sensitivity o f tunnelling current to width potential harriers'. This is a common problem to all the quantum effect devices. It requữes such high precision iithogr^hy that may be difficult to guarantee in the near term. • Extreme sensitivity o f making islands and tunnelling barriers uniformly: The large-scale production of these tunnelling devices need highly uniform distributions of barriers across the chip. This cannot be guaranteed unless the cutting bad itching techniques reach very high resolution. • Cryogenic operation: This is a problem for certain single electron devices. The operation of the quantum devices has been demonstrated at very low temperatures. To get them work at room temperature would mean that imparting the electrons lot more energy that could jeopardize the tunnel current. Some advances had been made towards the room temperature operation of these devices, but mass production still be a problem. • Valley current'. When the quantum devices are of the resonance, the tunnelling cxirrent might not be completely cut off. There will be a small cuưent through the device and fur­ ther miniaturization it may become difficult to determine between the on and off states. This is analogous to the leaking cuưent in the present day MOSFET technology. • Sensitivity to input voltage fluctuations’. The quantum devices can very sensitive to the input voltage fluctuations unlike the MOSFETS. Even a little blip could ừough the device accidentally off resonance. Despite these obstacles, the solid state quantum devices hold researchers are relentless in mak­ ing the integrated cữcuits with these devices. 12 .8 M O LEC U LA R ELEC TR O N IC S

One of the major obstacle for the solid state quantum devices is that the lithogr^hy is not precise enough guaranteed uniform devices all over the chip. The main principle in ứiis tech­ nology is to make the ideal molecules combine into steuctures that making compiling devices. Individual molecules naturally occur in nanometre scale structures. These molecules are exactly identical and can be originally combined to form structures that form structures as solid state transistors. This has given investigators to design, model, fabricate and test new devices. Molecular electronics is a speculative research idea but considerably advances have been made since its inception.

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In this section, we describe v ^ o u s types of molecular devices and some common ways of Ễibrícatíon. We give a brief description of ứie molecular wữes and insight into the working of the various devices. The unders^dmg of molecular electronics is heavily mterwmed with oiganic chemistry, but we do not elaborate on the actual reactions and formulae that govern these devices. The idea of this section is to acquaint the reader to the vast potential of molecu­ lar computing. 1 2 J .1 Molecular S w H d iiiif D e vitts

There are four broad classifications of molecular switching devices: 1. Quantum effect devices: which can operate by controlling the electric field across the device. 2. Electromechanical molecular devices: which employ electrical imd mechanical forces to change the configuration, or to move switching molecule or group of them, to turn a CIỈTrent on or oif. 3. Photoactive molecular switching devices: which use light to change the shape, orientation and the configuration of the device, thereby changing tìie current through the device. 4. Electrochemical switching devices: which use electrochemical reactions to change the shape and orientation and coníìgxưation and hence alter the current through the device. In this device paper, we focus on the fiiist two categories of devices as they are most closely related to the solid state devices that we have described in the previous sections. The other two devices have limitations. The photoactive devices are fast and small but they cannot be switched individually as light cannot be confined to small regions. Elecfrochemical devices have to be inunersed in ã solvent to operate which would prove messy for building integrated chips. 12

Fabrication and Assembly o f Molecular Structures

The whole field of molecular elecfronics is based on tile concept of that we can find chemi­ cal processes that can make the molecules bond in the exact same way as we intend to. There are many ways that have been ttied but the two major ones are mechanosynthesis and chemosynthesis. Mechanosynthesis is the fabrication of nanostructures, molecule by molecule, using nano­ probes (high precision controlling instruments) such as scanning tunnelling electron micro­ scope (AFM). These sensitive tools have made manipulation at the molecular levels possible. By manipulating individual molecules using nanoprobes, structures or devices that act as switches and ừansistors can be built. Chemosynthesis is another way of making these nanostructures. It is the chemical selfassembly of molecules into nanostructures. It includes certain biochemical methods that organically synthesize molecular electronic devices from individual molecules. This technique shows promise but research is still needed.

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12 .8 .3 Molecular Wires

The molecules can be made to assemble, but they must cooimuiiicate with each other. Molecu-. lar wừes are essentially a series of molecules that connect two devices and can conduct eiecừons between them. Many alternatives have been ưied to build a simple chain of molecules, but the major problem was that molecules that conduct well do not have good bonding proper­ ties and those that bond well and form chains do not conduct well, ư the wừes are just one molecule thick then they would exhibit very high resistance, which would be a pioblan. The most promismg discovery in ứiis field is a buckyball. This is a C60 molecule that has certain useful properties. It can conduct electrons and can also attach itself to otiier C60 mole­ cules as they have good coordination. Rows of these buckyballs can be made to combine with each other and form what is known as a bucky tube. It is sũniỉar to a carbon nanotube where the carbon atoms are chemically bonded to create filllerenes. These are vừtually flawless hex­ agonal arrays of conducting atoms and best example of molecular wữes. Other alternatives such as thiol functional groups at either end of ứie molecular wữe have been tries. These structures adhere to the metallic electrodes and form bonded connection act­ ing like an alligator clip. A sample molecular wire with these linkages is shown in Fig. 12.20. The wữe is composed of benzene like rings with acetylene linkages. To manipulate and fabricate tiny molecular switching devices it is easier to embed them in wữe like structures. Hence, the field of molecular wừes is intimately linked to the future of molecular elecưoDÌcs. 12 .8 .4 Qu antu m Effect Molecular Electronic Devices

These devices in principle work with the same ideas of resonant tunnelling and single-electron switching effects as the solid-state quantum devices we discussed earlier. The idea is to create potential wells within molecules such that electrons can be coniined to them. These potential wells must be controlled by elecừical field to make them switch between on and off states. There have been significant discoveries showmg this to be possible and demonstrating such effects as coulomb blockade with devices made from molecular elecưoDÌcs.

Thiol groups to adhere to electrode

Repeated aromatic group with acetylenic linkage

Thiol groups to adhere to electrode

Fig.12.20 An atomic wire with thiol groups serving as clips to the electrodes.

Nanotechnology: Electronic Devices

Tunnel barriers

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Tunnel barriers

Fig . 1 2 .2 1 A potential barrier distribution created from the inserted groups in an atomic wire.

Alternatively, a qxxantum well can be embedded in a molecular wừe like the one shown in Fig. 12.20, by inserting pairs of barrier groups that break the sequence of conjugated orbitals. This would produce a potential distribution as shown in Fig. 12.21. When the molecule is subjected to a voltage bias the barrier can be lowered and resonant tunnellmg can be made to take place. The problem with such devices is that the charging energy on either side of the well can be larger than the energy level spacing within the well. This would mean that the source and the drain may not have matching energy levels and hence the device may tunnel in but may not tunnel out. Still, these provide flexible and uni­ form ways of building potential barriers which might be the ftiture ways in which the quantum devices can be built. 12.8.5 Electromechanical Molecular Electronic Devices

Elecfromechanical molecular devices use force to deform or manipulate the molecules and make them function in a certain fashion. The input can be mechanical rather than electrical, but the interesting thing is that they can stop the flow of current through two sections of the wừe based on a condition. There are different tj^es of such devices based on what inputs they take. We illustrate some of them below. 12.8J. 1 Single Molecule Amplifier This is another application of the buckyball that was described in the previous section. The C60 molecule can be held between a scanning tunnelling microscope (STM) tip and substrate and when the tip is pressed upon, tíie buckyball is deformed and its conductivity decreases. Thus, the buckyball can be made to go on and off resonance by using a mechanical force. In real circuits this mechanical force would be provided by a piezoelectric gate or an actuator that can be controlled by an electeic field.

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12.8.5.2 Atom Relay The concept of an atom relay is shown in Fig. 12.22. There is a mobile atom between two wừes. Based on a controlling gate condition it switches the wứes in connected on or off state. The atom shuttles between the conducting and nonconducting phases, thus produc­ ing the effect of a switch. A thữd wứe analogous to the gate tenninai can also a d d e d and charged positive or negative. If the gate atom repels the switching atom then tìie switching atom moves to the off state whereas when it attracts the atom, the wke switches back to on state. However, the cừcuits that employ atomic relays are limited to two dimensions. Without crossing wires '.nly a few logic functions can be implemented and this is a major drawback of this type of devices.

G a te

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Wire o Wừe Input_____ y __ Output

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Wire Input

Wire Output

00000^00000

Switching atom

Reset (a) “ON”

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Switching atom

Reset (b)“OFF”

Fig. 12.22 An atomic relay showing the action of the gate (a) the switching atom is in the ON phase as gate attracts it and (b) the switching atom is in OFF state as gate repels it; the reset terminal is to reset the swilching atom to the ON state.

12.8.5.3 Refined Molecular Relays These devices are based on similar atomic movements as in an atomic relay but they might use the rotation of a molecule for the purpose of movement. The switching atom in the atomic relay can be made more reliable by attaching it to a rotating group or a rotamer. This rotamer is a part of a larger molecule. When the rotamer is in the wire, the switch is on and conducts cuưent, but when the gate is charged the rotamer is rotated out of the wire and tìie switch is turned off. There is a third molecule that prevents the rotamer from rotating freely due to thermal fluctuations. This allows the relay to be designed in three dimensions pennittmg the circuit to be made denser. However, there are issues such as the sừength of bonds between the rotamer and how sfray bonds might alter the coníìgiưation.

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C N FET

The CNFETs are devices that work on a similar principle as the MOSFET except the channel is made of a carbon nanotube. Carbon nanotubes are structures that can be made metallic or semiconducting based on the way in which they are rolled. The semiconducting tubes are used in the ữansistors. Both p- and n-type devices have been fabricated and IBM claims to have found a way to mass-produce them. This makes them worthy contenders to replace the MOSFET. However, several problems remain; • Further scaling is a problem. • Multi-level interconnects, such as different metal layers are still unavailable with carbon nanotubes. • New fabrication technology is not at the production level. Despite these problems, the industry is eagerly looking forward to production of experimental carbon nanotube chips. Singie-Electron Transistor

In this section, we explained the basic principle and operation of the SET. The SET is ailed by a problem of background charge which will be discussed later. The oper­ ation of SET cữcuit can be upset by the presence of one single stray charge and hence they are not likely to be used for large CMOS type applications but are quite useful for designing memories. QU AN TUM DOTS

The quantum dots are the zero dimension devices that are either empty or contain an electron. They require a new way in which we perceive the computing by dis­ carding the idea of the transistor switch. An aưay of these dots, called quantum cells, is used for the computational purposes. We try to communicate information not by transmitting cuưent but just by transmitting the state of the device this elim­ inates the many problems faced by the switching devices and hence the quantum dots appear to have a bright future. These devices are used to have a bright filture. These devices can be used to construct logic gates and quantum wires and effec­ tively functioning logic circuits. However, they have problems that are explained in the next section.

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Molecular electronics

The inefficient etching techniques from bulk materials led to the idea of making ứie switching devices from exactly identical molecules, which naturally occur in nanoscale elements. These molecules can be made to self-assemble or can be placed by manual intervention through nano-probes. Moreover, wừes can be made by joining conducting atoms called buckyballs. Certain molecular devices use quantum effects to conduct electrons. Potential baưiers can be made within a row of atoms and they even exhibit tunnelling. Other devices using mechanical forces to alter the current through a wire have been made. Relays using switching atoms are possible. Overall, the field of molecular electronics is promising but very nascent in nature. For it to unseat the solid state devices may need a series of discoveries in various fields.

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Fill in the Blanks 1. In carbon nanotube gate controls the flow of current by varying__________ through the channel. 2 . __________ is the process of heatmg tìie carbon nanotube to drive out ứie oxygen absorbed by it. 3. The place of confinement of electrons in SET is known a s _________. 4. ___________ a n d _____________ are useful properties exhibited by elec­ trons confined to islands in SET. 5. Quantum dot and single electro ữansistors are_________ devices. 6 . The source to drain voltage increase necessary to overcome coulomb blockade is called__________ . 7. ____________ can be assembled as a series of quantum cells. 8 . ____________ temperatures is major problem for quantum devices. 9. Molecular structures are fabricated using________ _ o r _________.

Answers

1. Field 2. Annealing 3. Island 4. Quantisation of energy levels, tunnelling 5. Resonant tunnelling 6 . Coulomb gap voltage 7. Quantum dot 8 . Quantum wke 9. Operating at high 10. Mechanosynthesis, chemosynthesis

Question Bank

Ỉ. What are four generations of Integration Circuits? • SSI (Small-Scale Integration) • MSI (Medium-Scale Integration) • LSI (Large-Scale Integration) • VLSI (Very Large-Scale Integration) 2. Give the advantages of IC. • Size is less • High Speed • Less Power Dissipation 3. Give the variety of Integrated Circuits. • More Specialized Circuits • Application Specific Integrated Circuits (ASICs) • Systems-On-Chips

4. Give the basic process for IC fabrication. • Silicon wafer preparation • Epitaxial growth • Oxidation • Photolithography • Diffusion • Ion implantation • Isolation technique • Metallization • Assembly processing and packaging

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5. What are the various silicon wafer preparations? • Crystal growth and doping • Ingot trimming and grinding • Ingot slicing • Wafer polishing and etching • Wafer cleaning. 6. What are the dUĩerent types of oxidation? Dry and Wet Oxidation. 7. What is the transistors CMOS technology provides? n-type ữansistors and p-type transistors. 8. What are the dUferent layers in MOS transistors? Drain, Source and Gate.

9. What is Enhancement mode transistor? The device that is normally cut-ofiF with zero gate bias. 10. What is Depletion mode device? The device that conducts witíi zero gate bias. 11. When the channel is said to be pinched-off? If a large Vos is applied this voltage with deplete ứie inversion layer. This voltage effec­ tively pmches off the channel near the dram. 12. Give the dUTerent types of CMOS process. • p-well process • n-well process • Silicon-on-Insulator Process • Twin-tub Process 13. What are the steps involved in twin-tub process? • Tub Formation • Thin-oxide Construction • Source and Drain Implantation • Contact cut definition • Metallization. 14. What are the advantages of SilicoD-on-Insnlator Process? • No latchup • Due to absence of bulks transistor structures are denser than bulk silicon.

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15. What is BiCMOS Technology? It is the combination of Bipolar technology and CMOS technology.

16. What are the basic processing steps involved in BiCMOS process? • Additional masks defining p base region • N Collector area • Buried Subcollector (SCCD) • Processing stqjs in CMOS process 17. What are the advantages of CMOS process? • Low power dissipation • High packing density • Bidirectional capability 18. What are the advantages of CMOS process? • Low input impedance • Low delay sensitivity to load. 19. What is the fundamental goal in device modelling? To obtain the functional relationship among the terminal electrical variables of the device that is to be modelled. 20. Define Short Channel devices. Transistors with channel length less than 3-5 microns are termed as Short chaimel devices. With short channel devices the ratio between the lateral and vertical dimensions are reduced. 21. What is pull down device? A device connected so as to pull the output voltage to the lower supply voltage usually 0 V is called pull down device. 22. What is pull up device? A device connected so as to pull the output voltage to the upper supply voltage usually Vdd is called pull up device.

23. Why nMOS technology is preferred more than pMOS technology? N-channel ừansistors has greater switching speed when compared to pMOS transistors. 24. What are the different operating regions for a nMOS traosistor? • Cutoff region • Non-saturated Region • Saturated Region

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25. What are the different MOS layers? • n-dififiision • p-diffiision • Polysilicon • Metal 26. What is Stick Diagram? It is used to convey information through the use of colour code. Also it is the cartoon of a chip layout.

27. What are the uses of stick diagram? • It can be dravm much easier and faster than a complex layout. • These are especially important tools for layout built from large cells. 28. Give the various colour coding used in stick diagram? • Green - n-diffiision • Red - polysilicon • Blue - metal • Yellow - implant • Black-contact areas. 29. Compare between CMOS and bipolar technologies. CMOS Technology

Bipolar Technology

• • • • • •

• High power dissipation * Low mput impedance (high drive current) • Low voltage swing logic • Low packing density • Low delay sensitivity to load • High output drive ciurent • High g„ (g„ and Vi„) • High ft at low cuưent * Essentially unidirectional

Low static power dissipation High input impedance (low drive current) Scalable threshold voltage High noise margin High packing density High delay sensitivity to load (fanout limitations)

• • • •

Low output drive ciurent Low gm ịg„ and Vi„) Bidirectional capability

A near ideal switching device

30. Define Threshold voltage in CMOS? The Threshold voltage, V, for a MOS transistor can be defined as the voltage applied between the gate and the source of ứie MOS ừansistor below which the drain to source current, IDS effectively drops to zero.

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31. What is Body effect? The threshold voltage V, is not a constant w.r.t. the voltage difference between the Sub­ strate and the soiưce of MOS ứansistor. This effect is called substrate-bias effect or body effect. 32. What is Channel-length modulation? The current between drain and soxưce terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied

Vd s ,

increasing

Vd s

causes

the depletion region at the drain junction to grow, reducing the length of the effective channel. 33. What is Latchup? Latchup is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between Vdd and Vss with disastrous results. Careful conteol dxuing fabrication is necessary to avoid this problem. 34. Define Rise tíme. Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steadystate value. 35. Define Fall time. Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state value. 36 Define Delay time. Delay time, td is the time difference between input teansition (50%) and the 50% output level. This is the time taken for a logic ừansition to pass from input to output.

37. What are two components of Power dissipation? There are two components that establish the amount of power dissipated in a CMOS circuit. These are; (i) Static dissipation due to leakage cuưent or other current drawn continuously from the power supply. (ii) Dynamic dissipation due to • Switching transient cuưent • Charging and discharging of load capacitances. 38. Give some of the important CAD tools. Some of the important CAD tools are; (i) Layout editors (ii) Design rule checkers (DRC) (iii) Circuit exttaction

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39. What is VerUog? Verilog is a general-purpose hardware descriptor language. It is similar in syntax to the c programming language. It can be used to model a digital system at many levels of abstraction ranging from the algoriửunỉc level to the switch level. 40. What are the various modelling used in Verilog? 1. Gate-level modelling 2. Data-flow modelling 3. Switch-level modelling 4. Behavioural modelling 41. What is the structural gate-level modelling? Structural modelling describes a digital logic networks m terms of the components that make up the system. Gate-level modelling is based on using primitive logic gates and specifying how they are wired together. 42. What is switch-level modelling? Verilog allows switch-level modelling that is based on the behaviour of MOSFETs. Digital circuits at the MOS-ừansistor level are described using the MOSFET switches. 43. What are identifiers? Identifiers are names of modules, variables and otíier objects that we can reference in the design. Identifiers consists of upper and lower case letters, digits 0 through 9, the under­ score character (_) and the dollar sign ($). It must be a single group of characters. Examples: A 01, a, b, in_o, s_out 44. What are the value sets in Verilog? Verilog supports four levels for the values needed to describe hardware referred to as value sets. Value levels Condition in hardware circuits 0 Logic zero, false condition 1 Logic one, true condition X Unknown logic value z High impedance, floating state 45. What are the types of gate arrays in ASIC? 1. Channelled gate aưays 2. Channel less gate aưays 3. Structured gate arrays

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46. Give the classifications of timing control. Methods o f timing control: 1. Delay-based timing control 2. Event-based tuning control 3. Level-sensitive timing control Types o f delay-based timing control: 1. Regular delay control 2. Intra-assignment delay control 3. Zero delay conưol Types o f event-based timing control: 1. Regular event conưol 2. Named event conừol 3. Event OR control 4. Level-sensitive timing control

47. Give the different arithmetic operators. Operator symbol Operation performed * Multiply Divide / + Add Subtract Modulus % Power (exponent)

Number of operands Two Two Two Two Two Two

48. Give the different bitwise operators. Operator symbol Operation performed Bitwise negation & Bitwise AND Bitwise OR Bitwise XOR or Bitwise XNOR Bitwise NAND Bitwise NOR

Number of operands One Two Two Two Two Two Two

49. What are gate primitives? Verilog supports basic logic gates as predefined primitives. Primitive logic function keyword provide the basics for structural modelling at gate level. These primitives are instantiated like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, xnor, and buf (noninverting drive buffer).

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50. Give the two blocks in behavioural modelling/ ' ’ 1. An initial block executes once in the simulation and is used to set up initial condi tions and step-by-step data flow. 2. An always block executes in a loop and repeats during the simulatioiL 51. What are the types of conditional statements? 1. No else statement Syntax : if ( [expression] ) true - statement; 2. One else statement Syntax ; if ( [expression]) true - statement; else false-statement; 3. Nested if-else-if Syntax : if ( [expression 1]) true statement 1; else if ( [expression!]) true-statement 2 ; else if ( [expressions] ) true-statement 3; else default-statement; The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed. 52. Name the types of ports in Verilog. Types of port Keyword Input port Input Output port Output Bidirectional port inout 53. What are the types of procedural assignments? 1. Blocking assignment 2. Non-blocking assignment 54. Give the different types of ASỈC. 1. Full custom ASICs 2. Semi-custom ASICs * standard cell-based ASICs * gate-aưay based ASICs 3. Programmable ASICs * Programmable Logic Device (PLD) * Field Progranunable Gate Aưay (FPGA). 55. What is the full custom ASIC design? In a full custom ASIC, an engineer designs some or all of the logic cells, circuits or lay­ out specifically for one ASIC. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for tìie entire design.

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56. What is the standard cell-based ASIC design? A cell-based ASIC (CBIC) Uses predesigned logic cells known as standard c standard cell areas also called flexible blocks in a CBIC are built of rows of cells. The ASIC designer defines only the placement of standard cells and th( connect in a CBIC. All the mask layers of a CBIC are customized and are unique to a particular customer. 57. Differentiate between channelled and channel-less gate array. Channelled Gate Array

Channel-less Gate Array

1. Only the interconnect is customized. 2. The interconnect uses predefined spaces between rows of base cells, 3. Routing is done using the spaces.

Only the top few mask layers are customized. No predefined areas are set aside for routing between cells. Routing is done using the area of transistors unused Logic density is higher.

4. Logic density is less.

58. Give the constituent of I/O cell in 22V10. 2V10 I/O cell consists of 1 . a register 2. an output 4:1 mux 3. a tristate buffer 4. a 2:1 input mux It has the following characteristics: • 12 inputs • 10 I/Os • product time 9 10 12 14 16 14 12 10 8 • 24 pins 59. What is a FPGA? A field programmable gate aưay (FPGA) is a progranunable logic device that supports implementation of relatively large logic circuits. FPGAs can be used to implement a logic cừcuit with more than 20,000 gates whereas a CPLD can ũnplement cữcuits of upto about 2 0 ,0 0 0 equivalent gates.

60. What are the different methods of programming of PALs? The programming of PALs is done in three main ways: • Fusible links • uv-erasable EPROM • EEPROM (E2PROM) - Electrically Erasable Programmable ROM

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61. What is an antifuse? An antifuse is normally high resistance (>100 MW). On ^ lic a tia a of appropriate pro­ gramming voltages, the antifuse is changed permanently to a low-resistance structure C200-500 W).

62. What are the dUĩerent levels of design abstraction at physical design? • Architectural or functional level • Register transfer-level (RTL) • Logic level • Cữcuit level 63. What are macros? The logic cells in a gate-aưay library are often called macros. 64. What are Programmable Interconnects? In a PAL, the device is programmed by changing the characteristics if the switching ele­ ment. An alternative would be to program the routing. 65. Give the steps inASIC design flow. a. Design entry b. Logic synthesis system partitioning c. Prelayout simulation d. Floor planning e. Placement f. Routing g. Exữaction 1. Post layout simulation 66. Mention the levels at which testing of a chip can be done. a. At the wafer level b. At the packaged-chip level c. At the board level d. At the system level e. In the field 67. What are the categories of testing? a. Functionality tests b. Manufacturing tests 68.

Write notes on functionality tests. Functionality tests verify that the chip performs its intended function. These tests assert that all ứie gates m tìie chip, acting m concert, achieve a desừed fimctioa These tests are usually used early in the design cycle to verify ứie fimctionality of the drcuit.

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69. Write notes on manufacturing tests. Manufacturing tests verify that every gate and register in the chip functions coưectly. These tests are used after the chip is manufactured to verify that the silicon is intact. 70. Mention the defects that occur in a chip. a. Layer-to-layer shorts b. Discontinuous wừes c. Thin-oxide shorts to substrate or well 71. Give some circuit maladies to overcome the defects. a. nodes shorted to power or ground b. nodes shorted to each other c. inputs floating/ou^uts disconnected 72. What are the tests for I/O integrity? a. I/O level test b. Speed test c. IDD test 73. What is meant by fault models? Fault model is a model for how faults occur and their impact on circuits.

74. Give some examples of fault models. a. Stuck-At Faults b. Short-Circuit and Open-Circuit Faults 75. What is stuck-at fault? With this model, a faulty gate mput is modelled as a “stuck at zero” or “stuck at one”. These faults most frequently occur due to thin-oxide shorts or metal-to-metal shorts. 76. What is meant by observability? The observability of a particular internal circuit node is the degree to which one can observe ứiat node at the outputs of an integrated circuit. 77. What is meant by controllability? The conữollability of an internal cừcuit node within a chip is a measure of the ease of setting the node to a 1 or 0 state. 78. What is known as percentage-fault coverage? The total number of nodes that, when set to 1 or 0, do result in the detection of the fault, di^ãded by the total number of nodes in the circuit, is called the percentage-fault coverage.

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79. What is fault grading? Fault grading consists of two steps. Fữst, the node to be faulted is selected. A simula­ tion is run with no faults inserted, and the results of this simulation are saved. Each node or line to be faulted is set to 0 and then 1 and the test vector set is qiplied. If and when a discrepancy is detected between the faulted cừcuit response and the good cừcuit response, the fault is said to be detected and the simulation is stopped. 80. Mention the ideas to increase the speed of fault simulation? a. Parallel simulation b. Concurrent simulation 81. What is fault sampling? An approach to fault analysis is known as fault sampling. This is used in cữcuits where it is impossible to fault every node in the circuit. Nodes are randomly selected and faulted. The resulting fault detection rate may be statistically infeưed from the number of faults that are detected in the fault set and the size of the set. The randomly selected faults are unbiased. It will determine whether the fault coverage exceeds a desừed level.

82. What are the approaches in design for testability? a. ad hoc testing b. scan-based approaches c. self-test and built-in testing 83. Mention the common techniques involved in ad hoc testing? a. partitioning large sequential circuits b. adding test points c. adding multiplexers d. providing for easy state reset 84. What are the scan-based test techniques? a. Level sensitive scan design b. Serial scan c. Partial serial scan d. Parallel scan 85. What are the two tenets in LSSD? a. The circuit is level-sensitive. b. Each register may be converted to a serial shift register. 86.

What are the self-test techniques? a. Signature analysis aild BILBO b. Memory self-test c. Iterative logic aưay testing

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87. What is known as BILBO? Signature analysis can be merged with the scan technique to create a structure known as BILBO for Built In Logic Block Observation. 88. What is known as IDDQ testing? A popular method of testing for bridging faults is called IDDQ or current supply moni­ toring. This relies on the fact that when a complementary CMOS logic gate is not switching, it draws no DC cxxrrent. When a bridging fault occurs, for some combination of input conditions a measurable DC IDD will flow. 89. What are the applications of chip level test techniques? a. Regular logic arrays b. Memories c. Random logic 90. What is boundary scan? The increasing complexity of boards and the movement to technologies like multichip modules and surface-moimt technologies resulted in system designers agreeing on a unified scan-based methodology for testing chips at the board. This is called boundary scan.

91. What is the test access port? The Test Access Port (TAP) is a definition of the interface that needs to be included in an IC to make it capable of being included in a boundary-scan architecture. The port has foxff or five single bit connections, as follows: • TCK (The Test Clock Input) • TMS (The Test Mode Select) • TDI (The Test Data Input) • TDO (The Test Data Output) It also has an optional signal. • TRST (The Test Reset Signal) 92. What are the contents of the test architecture? The test architecture consists of: • The TAP interface pins • A set of test data registers • An instruction register • A TAP controller 93. What is the TAP controller? The TAP confroller is a 16 state FSM that proceeds from state to state based on the TCK and TMS signals. It provides signals that control the test data registers, and the instruc­ tion register. These include serial-shift clocks and update clocks.

388

o

Question Bank

94. What is known as test data register? The test-data registers are used to set the inputs of modules to be tested, and to collect the results of running tests. 95. What is known as boundary scan register? The boundary scan register is a special case of a data register. It allows drcuit-boanl interconnections to be tested, external components tested, and ứie state of chip digital I/Os to be sampled.

Index

Abstraction, 80 Acknowledge signal, 316 Activation energy, 363 Actuator, 371 Adder, 206 Address, 238 Algorithm, 251, 309 Amplify, 323 Analog cell, 247 Analog design, 100 Analog-to-digital, 308 Analysis, 281 Annealing, 16 Antenna, 326 Anti-fiise, 198 Area constraint, 257 Array-based, 179 Array multiplier, 221 Aưival time, 260 ASIC, 85, 190 ASIC library, 88,185 Assembly yield, 100 Atom relay, 372

Attributes, 251 Automatic test pattern generation, 292 B Back annotation, 104 Baưel shifter, 230 Barrier, 130 Behavioural domain, 81 Bias, 357 BiCMOS, 1 Bioinformatics, 201 Bipolar, 65 Bipolar junction, 2 Blocks, 266 Block-select, 219 Board test, 297 Bonding, 32 Booth’s recoding, 222 Boundary-scan, 297 Buckyball, 371 Buffer, 146, 342 Built-in self-test, 295, 300 Built-in voltage, 133 Bulk, 47, 350

390

o

Index

Buried contact, 122 Bum-in, 36 Burst, 242 Butting contact, 122 c Cache, 232 CAD, 110 capacitors, 2 2 Carbon nanotubes, 347 Carry bypass, 214 Carry-lookahead, 219 Cany-save multiplier, 225 Cascade, 147 Cell-based, 179 Cell-based design, 188 Challenge is, 323 Channel, 54 Channel length, 125 Channel length modulation, 57 Charge-sharing, 130 Chemical-mechanical planarization, 4 Chemical vapour deposition, 4 Chips, 8 Chip select, 238 Cừcuit design, 81 Cữcuit-level, 248 Cữcuit under test, 286 Clock, 84, 185 Clock distribution, 147, 317 Clock gatmg, 314 Clock grid, 318 Clocking, 269 Clock skew, 91,147 Clock tree synthesis, 93, 318 CMOS, 3 Compiled cells, 179 Complexity, 147, 312 Complex Programmable Logic Devices, 182-185 Computer-aided design, 288 Configurable logic blocks, 190

Configuration, 142 Congestion, 95 Consfraints, 251,257 Contact cuts, 121 Controllability, 295 Cooling, 331 Coulomb blockade, 359 Coulomb gap voltage, 359 Critical path, 217 Crosstalk, 307 Crosstalk delay, 327 Crosstalk noise, 325 CRT, 323 Cryogenic, 368 Cryptography, 201 Crystal growth, 4 Custom, 179 Cut-off region, 53 Czochralski Technique, 6 D Datapath, 205 Deal-Grove model, 18 Defect, 287 Defect-free, 287 Defect level, 289 Delay, 92, 142 Delete, 207 Demarcation line, 113 Depleted, 322 Depletion Mode MOSFET, 55 Design, 79 Designer, 95 Design flow, 82 Design for power, 314 Design-for-testability, 80 Design specification, 109 Design verification, 98 Detailed routing, 96 Diagnostic test, 294 Dielecttic, 125 Dies, 8

Index

Difiiision, 4, 1 1 0 Digital design, 100 Digital signal processing, 201 ’ Digital-to-analog, 308 Dừect memory access, 309 Dissipation, 350 Domino CMOS, 146 Doping, 4 Drain, 47 DRAM, 1 Drift current, 53 Drive, 185,259 Drivers, 157 Diy etching, 4 Dual-in-Line, 35 Dynamic, 145 Dynamic power, 58 E EDA, 89 EEPROM, 172 Elaboration, 281 Electtic field, 54, 371 Electrochemical deposition, 4 Elecfrode, 351 Electromigration, 29,101 Elecfron Beam Lithography, 27 Electronic Design Automation, 266 Elecừonics, 125 Elecfrostatic discharge, 307 Embedded, 311 Emulation, 310 Encapsulation, 4 Enhancement mode, 46 Epitaxy, 9-10 EPROM, 172 ESD, 307 Etchant, 28 Evaluation, 145 Event-driven, 249 Event-driven sữnulation, 250

o

391

Exhaustive testing, 290 Exừactíon tools, 103

Fabrication, 287,341 Factoring, 254 Pailiưe mode analysis, 288 Falling edge, 316 Fall time, 157 Fanout, 254 Fault-free, 286 Fault models, 290 Fermi level, 354 Figure of merit, 45 Final addition, 221 Flat band voltage, 49 Flattening, 253 Flip-chip, 33 flip-flop, 184 Floor plannmg, 92 Formality, 90 Formal verification, 83 Foxmdry, 115 FPGA, 85,172 Fringing fields, 165 Functional test, 294 Functional testing, 290 Furnace, 16 G Gain, 323 Gate, 47 Gate4evel, 248, 265 Gate-level simulation, 104 Gate oxide, 45 GDSn, 115, 326 Generate, 207 Glitch, 91 Glitch avoidance, 342 Globally asynchronous locally synchronous, 317 Global routing, 96

392

o

Index

H Hardware, 171 Hardware description language, 84 HDL, 189 Hierarchy, 105 Hold time, 91 Hot-electron effect, 335 H-tree,318 I Impedance, 141 Implementation, 79 Inpuưoutput impedance, 323 Integrated circuits, 110 Intel Pentium, 349 Interconnect, 29, 95 Inverter, 45 Ion channelling, 15 Ion implantation, 4 Islands, 355

K Kernels, 201 L Lambda, 117 Latch, 93 Latchup, 45, 72, 307 Layout, 95, 104 Layout versus schematic, 98 Leakage, 125 Leakage current, 57 Lightly doped drain, 333 Linearity, 323 Load, 259 Locality, 106 Locality of reference, 338 Logarithmic shifter, 231 Logic, 145 Logical design, 81 Logic effort, 325 Logic-mapping, 281 Logic minimization, 253

Logic net, 326 Logic optimization, 253 Logic synthesis, optimization, 83 Lookup table, 191 Low-noise amplifier, 324 M Macro cells, 179 Macros, 93 Main memory, 232 Manchester carry gate, 212 Mask, 27, 115 Mask-prograirunable, 200 Mean tune before failure, 326 Mechanosynthesis, 369 Memory, 247 Memory cell, 234 Metallization, 4,42 Microcontroller, 310 Microfabrication, 9 Microprocessor, 3, 171, 308 Mobility, 54 Modelling, 249 Modularity, 106 Molecular beam epitaxy, 4 Molecular electronics, 347, 368 Moore’s law, 3 MOS, 109 MOSFET, 1 Motivation, 285 MPEG, 308 Multiplexers, 141 Multithreading, 311 N Netlist, 8 8 , 95,267 Network on a chip, 310 Noise, 323 NORA CMOS, 147

o Oblivious, 249 Observability, 295

Index

Ohmic, 48 Optimizatioii, 89,314 Oscillator, 309 Output conductance, 60 Oxidation, 4 p Package, 31 Package design, 103 Parallelism, 337 Parametric test, 294 Parasitic extraction, 104 Parasitics, 325 Partial product accumulation, 221 Partial-product generation, 221 Pass ừansistor logic, 45 Phase lock loop, 309 Photolithography, 4 Photoresist, 21 Physical design, 81 Physical domain, 81 Physical vapour deposition, 4 Physics, 363 Piezoelectric, 371 Pinch off, 51 Pin-tìưough-hole, 31 Pipelining, 229, 336 PLA, 89 Place and route, 94, 266 Placement, 94, 318 Plasma, 28 Plasma etching, 4 Point-to-pomt, 339 Polysilicon, 150 PosMayout, 83, 248 Potential wells, 355 Power dissipation, 323 Power distribution, 102 Power network, 313 Power plan, 93 Power structure, 93 Precharge, 145 Pre-difiused, 179

Pre-wứed, 179 PrimeTime, 92 Primitive, 249 Process, 129,317 Processor, 205 Process yield, 100 Programmable array logic, 178-179 Programmable logic aưays, 173 Programmable logic devices, 171 Projected range, 14 Projection, 25 PROM, 172 Propagate, 207 Propagation delay, 248 Proxunity, 25,266 Pull dowB, 63 Pull up, 63

Quality Assurance, 287 Quantisation, 357 Quantum cell aưay, 365 Quantum dots, 347 Quantum effect, 348 Quantum wkes, 366 R Radio frequency, 323 Rapid thermal annealing, 16 Read-Only Memory, 173 Reconfigure, 171 Redundant, 322 Refresh, 241 Register, 257 Register Transfer Level, 80, 81, 84 Regularity, 105 Reject rate, 288 Reliability, 2,117, 321 Rent’s rule, 32 Reprogrammable, 267 Request signal, 316 Resistors, 22 Response analyzer, 301

O

393

394

o

Index

Ripple cany adder, 208 Rise-Time, 155 Rising edge, 316 Routing, 96 RTL simulation, 83 Rule checkers, 103

Saturation, 51 Scaling, 109, 125 Scan design, 295 Scanning, 25 Schematic, 8 8 , 189 Schrodinger’s, 356 Script, 279 Self-inductance, 327 Semicustom, 179 Sense amplifier, 241 Sequential, 250 Sequential cells, 318 Setup time, 91 Sheet resistance, 37, 148 Shieldmg, 322 Shifter, 229 Shockley, 55 short-circuit, 344 Signature analyzer, 302 Silicon germanium, 351 Silicon on insulator, 3, 351 Simulation, 86,247 Single elecừon transistor, 347, 357 Size, 312 Software development, 79 Source, 47 Speed, 323 SPICE, 248,315 Spikes, 321 SRAM, 193 Stacked capacitor, 242 Standard cells, 93,179 Standard Delay Format, 267 Static power, 59 Static timing analysis, 91,104, 248

Step-and-repeat, 25 Stick diagram, 109 Stimuli, 291 Stimulus generator, 301 Structural domain, 81 Structural model, 252 Structural testing, 290 Structuring, 254 Stuck at fault, 292 Sub-micron, 339 Substrate, 18 Sub-threshold, 129,239 Supply voltage, 261,323 Swings, 323 Switching threshold, 63 Switch-level, 248 Sjnachronization, 315 Synchronous, 84, 309 Synchronous block, 317 Synopsys’s Design Compiler, 8 8 Synthesis, 251 Synthesizer, 252 System-level study, 324 System on chip, 308

T Tapeout, 99 Temperature, 317 Testability, 36, 295 Test bench, 87 Test controller, 301 Test data, 298 Testmg, 4, 285 Test mode select, 298 Test vector, 267,290 Test yield, 100 Thm Film Transistor, 236 Threshold voltage, 45 Throughout, 307 Time-consuming, 177 Timing, 92,247, 309 Timing report, 264 Timing verification, 101

Index

Tolerance, 322 Topology, 138 Transconductance, 60 Transconductance, output conductance, 45 Transform, 323, 331 Transistor, 2 Transistor-level, 248 Transistor-transistor logic, 65 Transition, 236 Transition avoidance, 342 Translation, 252 Transmission gate, 140,212 Tree multiplier, 226 Trench, 242 Trunk, branch-ttee, mesh, x-tree, 318 Truth tables, 292 Tub tie, 115,135 Tunnelling, 133, 321

Valley cuưent, 368 Vector-merging adder, 225 Verification, 79 VLSI, 45 Voltage, 323

u Utilization rate, 96

X

w Wafers, 5 Wafer test, 287 Wallace ữee multiplier, 228 Watchdog timer, 322 wear out, 320 Well, 117 Wet etching, 4 Wữe load model, 325 Word line, 239 Work function, 49 Wrapper, 317

Xilinx, 190 Y

Vacuum tubes, 1

Yield, 117, 288

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V a rio u s m o d e l l i n g i s s u e s of V L S I d e v i c e s a r e f o c u s e d w h i c h i n c l u d e s n e c e s s a r y de . ice t h e r e q u ir e d le v e l. W it h s u c h a n in - d e p t h c o v e r a g e a n d p r a c t i c a l a p p r o a c h p r a c t i s i n g ' c a n a l s o u s e t h is a s r e a d y r e f e r e n c e .

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T e s tin g of C M O S d e v ic e s

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Q u e s t i o n s w ith s o l u t i o n s th a t r e fle c t

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the c o m m o n d o u b ts a b e g in n e r e n co u n ters.

I n d u s tr y t r e n d s .

D e v i c e f a b r i c a t io n t e c h n o l o g y .

E m p h a s is on V H D L .

K. Lai Kishore h a s d istin g u ish e d a c a d e m ic record and sign ificant a c h ie v e m e n ts in the ed u c a tio n a l field. H a v in g o b ta in e d M a s te r 's d e g r e e and Ph .D . from Indian InsiitLite of S c i e n c e (I.I.Sc) B a n g a lo r e , he jo ined 1he te a c h in g p ro fe s sio n in 1977. in J N T U H y d e ra b a d , H e b e c a m e P r o f e s s o r in 19 90 a n d held m a n y ad m in is tra tive p o s itio n s includ in g c h a iim a n B O S , H e a d of the D epa rtm ent, Prin cipal, D irecto r A c a d e m ic & P lanning. D ir e c io r U G C A S C a n d R e g is tr a r of J N T U . P rese ntlv , he is R e c t o r l/c o f J N T U . H y d e ra b a d , H e h a d p u b lis h e d m o re than 76 r e s e a r c h p a p e r s in inte rnational / natio nal jo u rn a ls a n d p r e s e n t e d p a p e rs in international / national c o n fe r e n c e s . H e is guid ing a n u m b e r of re s e a r c h sc h o la r s . H e IS B e s t T e a c h e r a w a r d e e from the G o v e r n m e n t of A n d h r a P r a d e s h , s.v.c. A iy a M e m o al A w a rd , from lE T E , i/lent aw ard from D E C Ethopia, B a p u S e e t h a r a m M e m o ria l A w a r d from l E T E a n d h a s m a n y other a c a d e m ic distin ction s to his credit. H e wrote four other te x tb o o k s on E le c tro n ic D e v ic e s , Circuit A n a ly s is , L in e a r i.e. App licatic IS a n d E le c tro n ic M e a s u r e m e n t s a nd Instrumentation. H e h a s c o m p le t e d v a rio u s re s e a r c h project; actively invo lved in t e a c h in g and r ese a rc h . H e is a m e m b e r of I E E E , F e llo w of l E T E a n d IE. Life Ỉ of I S T E a n d l S H M .

V. S . V. Prabhakar o b t a in e d his B a che lor’s d e g r e e from O s m a n i a U n iv e rs ity . L a te r he o b t a in e d his M a s t e r ’s d e g r e e from L u n d ’s T e c h n ic a l U n ive rsity, S w e d e n with s p e c ia liz a t io n in S y s t e m on C h i p ( S o C ) . H e w o r k e d a s P r o je c t A s s o c i a t e ;n the D e p a r tm e n t of E E at IIT M a d r a s f o r t w o y e a rs. P r e s e n tly , h e is w o rk in g a s P r o f e s s o r a nd H e a d of the D e p a r tm e n t E C E , at L e n d i Institute of E n g in e e r in g a n d T e c n r o l o g y . J o n n a d a , V i z i a n a g a r a m . H e is w o rk in g for his P h . D . u n d e r Prof. K, Lai K i s h o r e in the a r e a of V L S I d e s ig n . H is r e s e a r c h in te re s ts in c lu d e V L S I D e s ig n , M i c r o e l e c t r o n i c : E le c t r o n ic D e v i c e s a n d C irc u its, Digital Integrated C irc u its. L o w P o w e r V L S I C ir c u l

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