C ontents C hapter1. BASIC INFORMATION 1-1. PRE-INST A LLATION 1-2. INSTRUCTION 1-3. INSTALLATION G UIDE SA6000II PRELIMINARY INSPEC TON SA6000II PRELIM INARY INSPECTON LIST
C hapter 2. DESC RIPTION OF SYSTEM 2-1. PSA BO ARD 2-2. BF & RX BO ARD 2-3. DSC BOARD 2-4.KEY INTERFAC E & MATRIX 2-5. REAR BO ARD 2-6. PC BO ARD 2-7. MO THER BO ARD 2-8. SYSTEM SET-UP DIALOG UE 2-9. MAIN BOARD PICTURE
C hapter 3. SUB-APPARATUS 3-1. MAIN POWER SUPPLY 3-2. MONITOR 3-3. MOD
C hapter 4. DIAG RAMS 4-1. ASSEMBLING DIAGRA MS 4-2. C ABLE DIAG RAMS
C hapter 5. SPEC IFIC ATION 5-1. MAIN FEATURES 5-2. TECHNICAL SPECIFICATIONS Servic e Manual
Published by C ustomer Servic e Depa rtment
Section 1-1. Pre- Installation
1.
PRE-INSTALLATION
1.1 INSPECTION Upon arrival, inventory the shipment with the carrier’s driver. ?? Carefully
inspect
punctured, ?? If
torn,
the
packing
material
for
obvious
si g
broken, attling packages. wet or
damage evident, is n ot
sign
and
a bill of unknown lading “condition of contents –
stamp
subject to inspection. ” ?? If
damage
is
evident,
contact
your
indicate the damage on t he damage on t he freight bill, and sign
’s driv er
Purchasing ave the carrier Departmen
all copies of the bill.
During formal inspection, you should : ?? Open
all
?? Report
packages
concealed
within eceipt for 15
damage
to
a days complete of the
inspection
carrier
within
acceptility. lia
1.2
UNPACKING
Please,
unpack
the
system
like
following
draw>
draw.
15
of
the
days
Sec tion 1-1. Pre- Installation
1.3 Basic features
?? 12
inch
?? Power
B/W
cord,
monitor
and
connection
main
unit
cable
and
equipped fuse
with
keyboar
2)
’s Guide (1)
?? User
?? Ultrasound
gel
0.25
L)
?? Setcov er
Item
Description
226P 089A
PANEL
235P 007A 235P 007B
CLAMP
BRACKET
CLAMP
CLAMP
334 M011B
CLAMP RUBBER
271 Z006C 275 K859A
ST
ACCESSARY
MNT
GEL 0.25L
SONO
CNN BNCRC AJ
CAP
215 Z715A
SET 12.5
FUSE -0T3.15L FUSE -0T6.3L MANUAL -000II E
AC
GEL
BNC
COVER
TRIAD
Inside
of
Box
Inside
of
Box
12MTR 2 Inside
of
Box
1
1 1
25
1.4M
50T 50T
Stacker Inside
1
Inside
Inside
RCA/FEMALE 2 4
SA6000II 1 FILTER
SEO
IL 1
T3.15L250V2 T6.3L250V
MANUAL
Part
2
ENGLISH 1
Box
Box
of of
of
Inside On
on
of
KKP1603 1 Inside 1
Box
BOX
1
SA6000II
SA6000II
1
of
4800HD
MONITOR
TRIAD
Box
Inside
0.25L
TO
Table)
Service Ma nual
CORD V
CORD
Box
of
12MTR
FILTER
of
Inside
12MTR 1
CABLE
BNC/MALE
CAP
325Z010A
PWR
RHT
LFT
Inside
1
BOX MEDISON
EUROPE
CORD316 MNT
LFT
BOX ALL
GROUND
CORDPWR 3250V
RHT
GUIDE
ACCESSARY
CBL -ROUNDNEW
RU48P BNC
FILTER F TER I
Quantity Location
SA6000II1
BRACKET
334 M011A
311 R003A
BASKET
Box Box
Box
of
Box
System
Inside
Box of
GLASS) Inside of Inside Inside Inside
of of of
Box Box Box Box
List
Published by C ustomer Service Department
Sec tion 1-1. Pre- Installation
1.4 Option features ?? Linear
Probe
Model
Name
Specification 7.5
MHz
/
40mm Small
Parts
L59EC
7.5
MHz
/
40mm Small
Parts
L59ER
?? Convex
7.5
Name
6.5
C37ED
4.5
?? Software
?? VCR
:
Service Ma nual
3.0
EC4 9ES
?? External
?? Foot
/
50mmSmall
Specification
C24 ES
?? Echo
MHz
Parts
Probe
Model
?? Line
Application
HL59ED
:
MHz/10R/1 0D
Cariac Trans Vaginal
MHz/50R/70DGene ral
DICOM
VGA
M onitor
Printer ony UP890 : MISTUBISH Printer VHS
Application
MHz/30R/ 0
:
HP
DeskJet
P91W
Video
Printer
Series
Type
switch
Published by C ustomer Service Department
Sec tion 1-2. Instruction
SonoAce 6000II
2.INSTRUCTION 2.1 NOTES TO USERS Tha nk yo u for p urc has ing t he SA 6000II Ultra sou nd sy ste m. T o ens ure saf e ope rat ion and l ong ter m per form ance sta bil ity , it is esse nti al tha t you ful ly und ers tan d the functions, operati on and maintenance instructions by reading this manual before operating your equipment.
?? Incorrect
operation,
manufacturer
or
responsibility
for
?? The
following
his
or
failure
agent
any ury. damage
conventions
are
of
the
user
compliance of the s yst em with s or used
main
in throughout
the
emphasis.
WARNING ! “Warning” is used to indicate the presence of a hazard which can cause severe personal injury, death, or substantial property damage if the warning is ignored. CAUTION ! “Caution” is used to indicate the presence of a hazard which will or can cause minor personal injury or property damage if the warnings ignored. NOTE “Note” is used to notify the user of installation, operation, or maintenance information which is important but not hazard-related. Hazard warnings should never be included under the Note signal word.
Service Ma nual
to
non specificatio
Published by C ustomer Servic e Depa rtment
manual
Sec tion 1-2. Instruction
2.2 SAFETY PRECAUTIONS 2.2.1 Biological safety This s ection contains inform ation about biological saf ety and a discussion of the prudent use of the system. A list of precautions related to biological safe ty f ollows; observe these precautions when using the system.
WARNING
Do not use t he system i f an error m e ssage appear s on the video di splay indicating that a hazardous condition exists. Note the error code, turn off power to the system, and call your customer service representative. Do not us e a sys tem that exh ibits erratic or inconsistent up dating. Discontin uities in the scanning sequence are indicative of a hardware failure that must be corrected before us e. Perform ultrasound procedures prudently. Use the ALARA (as low as reasonably achievable) principle. Use only acoustic standoffs that have been approved for use by MEDISON. Verify the alignment of the biopsy guide before use. See the [Probes] section of this manual. Verify the condition of the biopsy needle before use. Do not use a bent biopsy needle. Biopsy gui de shea ths co ntain nat ural rubb er lat ex. Th es e sheat hs may ca use al lergic reactions. Refer to the FDA Medical Alert on Latex Products, dated March 29, 1991, in the “Sheaths ” section of this manual.
ALARA Ed ucation Pr ogram The guidance for the use of diagnostic ultrasound is defined by the ¡ °as lo w as reasonabl y achievable ¡ ±(ALARA) princi ple. The decision as to what is reasonable has been left to the judg ement and insight of qualified personnel. No set of rules can be formulated that would be sufficiently complete t o di ctate th e co rrect re sponse t o e very c ircumstances. By ke eping ul trasound e xposure as low as possible, w hile obtaining diagnostic images, u sers can minimize ultrasonic b ioeffects. Since the threshold for diagnostic ultrasound bioeffects is undetermined, it is the sonographer ¡¯ s responsibi lity to control tot al energy transmitted into the patient. The sonographer must reconcile exposure time with diagnostic image quality. To ensure diagnostic image quality and limit exposure time, an ultrasound system provides controls that can be manipulate d during the exam to optimize the results of the exam. The ability of the user to abide by the ALARA principle is important. Advances in diagnostic ultrasound not only in the technology but in the applications of that technology, have resulted in the need for more and better inform ation to guide the user. The output indices are designed to provide that important information There are a number of variables which affect the way in which the output display indices can be used to impleme nt the ALARA principl e. These variables include values, body size, location of the bone relative to the focal point, attenuation in the body, and ultrasound exposure time. Exposure time is an espe ci ally usef ul va riab le, b ecau se it is co ntro lled by the u se r. Th e a bility to limit t he in de x values over time supports the ALARA principle.
Service Manual
Published by C ustomer Servic e Department
Sec tion 1-2. Instruction
Service Manual
Published by C ustomer Servic e Department
Sec tion 1-2. Instruction
2.2.2 Electronic Safety This equipment has been verified as a Class I device with Type BF applied part. For maximum safety observe these warnings
WARNING
Shock hazards may exi st if thi s s ystem, including all ex ternally mounted recording and monitoring devices, is not properly grounded. In a hospital, doctors and patients are subjected to dangerous, uncontrollable compensating currents. These currents are due to the potential differences be tween connected equipment and touchable conducting parts as found in medical rooms. The safe solution to the problem is accomplished with consistent equipotential bonding. Medical equipment is connected with connecting leads made up with angled sockets to the equipotential bonding network in medical rooms.
Connection Lead (Socket)
Ground Connector Earth in Medical Room
B O D Y
~ ~ Detail 2.
Service Manual
M A I N
SA 6000II Main Console Safety Ground
Published by C ustomer Servic e Department
Sec tion 1-2. Instruction Do not remove the protective covers on the system; hazardous voltages are present inside. Cabinet panels must be in place while the system is in use. All internal adjustments and replacements must be made by a qualified MEDISON customer service representative. Do not operate this system in the presence of flammable gases or anesthetics. Explosion can result. To avoid risk of electrical shock hazards, always inspec t all the probes bef ore use; check the face, housing, and cable before use. Do not use, if the face is cracked, chipped, or torn, the housing is damaged, or the cable is abraded. To avoid ri sk of elect rical sho ck haz ards, al ways disconnect the sy stem from the wa ll outlet prior to cleaning the system.
WARNING
To avoid risk of electrical shock, do not use any probe that has been immersed beyond the specified cleaning or disinfection level. See [Appendix A. MAINTENANCE] manual. To avoid risks of electrical shock and fire hazards, inspect the system power cord and plug on a regular basis. Ensure that they are not damaged in any way. To avoid risk of electrical shock hazards, accessory equipment connected to the along the dig ital i nterfaces must be certified according to the representative IEC standards ( I.e. I EC609 50/ EN609 50 fo r dat a pro ces sing eq uipmen t and IE C60601 1/EN60601 - 1 for medical equipment). Furthermore all configurations shall comply wit h the syst em st anda rd IE C606 01 - 1- 1/EN60601 - 1- 1. Ev ery body who conn ect s additional equipment to the signal input part or signal output part configurations a medical system, and is therefore responsible that the system complies with the requirement of IEC6 060 1 - 1- 1/EN60601 - 1- 1. If in do ubt, consult the t echnical services dep artment or you r local representative. Do not touch the SIP/SOP and patient simultaneously. It may cause a leakage current exceeding the m aximum allowable valu es.
Althou gh your sys tem has been manufa ctured in com plianc e with existing EMI/ EMC requirements, use of this system in the presence of an electromagnetic field can cause momentary degradation of the ultrasound image. If this occurs often, MEDISON sugg ests a rev iew o f the envi ronm ent i n whi ch th e sys tem i s be ing used, to identify possible so ur ce s of radiated emissions . These emissions cou ld be from other electrical devices used within the same room or an adjacent room. Communication devices such as cellular phones a n d pagers can cause these emissi ons. The exis tence of radio, TV, or microwave transmission equipment locat ed nearby can cause emissions. In cases where EMI is causing disturbances, it may be necessary to relocate your system. CAUTION
Electrostatic discharge ( ESD), commonly referred to as a static shock, is a naturally occurring phenomenon. ESD is most prevalent during condi tions of low humidity, which can be caused by heating or air conditioning. During low humidity conditions, electrical charges naturally build up on individual s and can create static shocks. An ESD condition occurs when an individual with an electrical energy build up comes in contact with objects such as metal doorknobs, file cabinets, computer equipment, and even other individuals. The static shock or ESD is a discharge of the electrical en ergy build - up from a ch arged individual to a le sser or non - charged individual or object. The level of electrical energy discharged from a system user or patient to the ultrasound system can be significant enough to cause damage to the system or probes. The following precautions can help to reduce ESD: anti - static spray on carpets; anti - static spray on linoleum; anti - static mats; or a ground wire connection between the system and the patient table or b ed.
Service Manual
Published by C ustomer Servic e Department
Sec tion 1-2. Instruction
2.2.3 Mechanical Safety
Be aware of the casters, esp ecially wh en moving the system . The system can weig h approximately 70kg, depending upon configuration, and it could cause inj ury to you or others if it rolls over feet or into shins. MEDISON recommends that you exercise caution when going up a nd do wn ra mps. The monitor has been designed so that it can be easily removed from the system if needed.
WARNING
?? System
The
breake
system
release.
has
certain limit
?? Moving
Only
the
spaces, If
the
to
the
brake
for
the
front
or
wheels. o lock Press and down lift on
the g brake the system. when movi However, system,
the
break
may
not
if
you
work
apply
properly.
system
wheels
are
steerable
repeated and forth back movements
system
dis co nected can
the
front
use
department
and
a
Release
behaves your
inside
withstand
abnormally
local
the
on
to
the
af ter
and
considerable
may
On
cause
shock,
the
moving
representative.
system
system.
position
but
the
rare
a
Theref
system
occasio
problem.
excessive
The inter national Electrotechnical Commission (IEC) has establis hed a set of symbols for medical electroni c equipment, which class ify a connection or warn of pot ential hazards. The classifications and symbols are shown below.
I and O on power switch represent
applied part
).
ON and OFF , respectively.
This symbol identifies a safety note. Be sure you understand the function of this control before using it. The control function is described in the appropriate operation manual.
Identifies equipotential ground.
Indicates dangerous voltage over 1000 VAC or over 1500 VDC.
Service Manual
The
shock
2.2.4 SYMBOLS
Isolated patient connection (Type BF
into
system,
Published by C ustomer Servic e Department
m
Sec tion 1-2. Instruction
Identifies the point where the system safety ground is fastenedto the chassis. Protective earth connected to conductive parts of Class I equipment for safety purposes.
Output port fo
r VGA or Parallel port
Input/Output(I/O) port used for modem or RS232C port.
Left and right audio input. Video input
Left and right audio input Video output
Print remote output
Connection for foot switch
Protection against t
he effects of immersion.
Protection against dripping water.
Connection for probes
Service Manual
Published by C ustomer Servic e Department
Sec tion 1-2. Instruction
2.3 MAINTENANCE 2.3.1 PROBE
WARNING
Always use protec tiv e e yew ear and glo ves whe n c lea nin g a nd dis inf ecting p robes and b iopsy gu ide ada pters.
CAUTION
Probes must be cleaned after each use. Cleaning the probe is an essential step prior to effective disinfection or sterilization. Be sure to follow the manufacturer instructions when using disinfectants. Do not allow sharp objects, such as scalpels or cau terizing knives, to touch probes or cables. When handling a probe, do not bump the probe on hard surfaces.
’s
The probe that you select is the most important factor in image quality. Optimal imaging cannot be atta ined with out the co rr ect pr ob e. Th e syst em i s op ti mize d fo r us e ba se d on yo ur pr ob e selection.
?? CLEANING
not use a ’ssurgeon brush when cleaning probes. The use of even soft brushes can damage the probe. During cleaning, disinfection, and strilization, orient the parts of the probe that remain dry higher than the wetted parts until all parts are dry. This will help keep liquid from entering non - liquid - tight areas of the probe.
Do
CAUTION
¨ç
Disconnect the probe from the system.
¨è
Re mo ve any sh ea th s, bi op sy gu ide ad ap te rs, or bi op sy ne ed le gu id es (b adapters are r e - usable portion of the b iopsy guide and can be st erilized.)
¨é
Discard sheaths(sheaths are single
¨ê
Use a soft clot h lightly dampened in a mild soap or compatible cleaning so lution to remove any particulate matter or body fluids that remain on the probe or cable.
¨ë
To remove remaining particulates, rinse with water up to the immersion point.
¨ì
Wipe with a dry cloth; or wipe with a water then wipe with a dry cloth.
Service Manual
must
iopsy guide
- use item)
- dampened cloth to remove soap residue, and
Published by C ustomer Servic e Department
Sec tion 1-2. Instruction
?? DISINFECTION Only
following
the
solutions. (as
OR RILIZATION ST
the9ES EC4 probe
The
following through
sterilized. reduction A in 10 pathogens
procedures
in
this
manual
Country
Cidex Cidex
the
FDA
510(k)
process)
and
its
Type
Active
ingredient FDA
chemic
510(k)
USA
Liquid
GluteraldehydeK 93434
Liquid
GluteraldehydeK9 23744
If
a mixed pre level
contact
solution of
is
used,
disinfection
for
be
sure
required
during re use. that Ensthe
appropriate
solution
disinfecti on
or
to for
observe a
the
device
strength
and
’s
sterili zation.
instructions. In neurosurgical application, sterilized probes should be used with a pyrogen sheath.
- free
Using a n o n - recom mended disinfection solution, incorrect solution strength, or immersing a probe deeper or for a period longer than recommended can damage or discolor the probe and will void the probe warranty. Do not immerse probes longer than one ho u r, unless they are sterilizable. Probes may be damaged by longer immersion times. Sterilize probes using only liquid solutions. Using autoclave, gas(EtO), or other non MEDISON- approved methods will damage your probe and void your warranty.
¨í
Mix the disin fecti on solutio n (or sterili zation soluti on, for steril izable probe) compat ible with your probe according to label instructions for solution strength. A disinfectant qualified by the FDA 510(k) process is recommended.
¨î
Immerse the probe into the disinfectio n solution (or sterilization solution, for sterilizable probe) as shown in the figure below for your probe.
¨ï
Follow the instructions on the disinfection (or sterilization, for sterilizable probe) label for the duration of probe immersion. Do not immerse pro bes longer than one hour, unless they are sterilizable.
¨ð
10. Using the instruct ions on t he disinfect ant or st erilization label, rinse the probe up to the point of immersion, and then air dry or towel dry with a clean cloth (or a sterile cloth, for steriliza ble probe).
¨ñ
11. Examine the probe for damage such as crack s, splitti ng, fluid leaks, or sharp edges or projections. If damage is evident, discontinue use of the probe and contact your customer service representative.
Service Manual
using
disinfectants cause are of recommended both its biological b
Plus USA
The
CAUT ION
should
and
materials.
Solutions
WARNING
be
sterilization
qualified
product
can
-
Published by C ustomer Servic e Department
so
is dur
Be
su
Sec tion 1-2. Instruction
Service Manual
Published by C ustomer Servic e Department
Sec tion 1-2. Instruction
2.3.2 BIOPSY GUIDE ADAPTOR AND NEEDLE GUIDE The external surfaces of reusable biopsy guide adapters can be sterilized using one of the -6 following procedures. A 10 red uction in pathogens shoul d be reached by following the procedures in this manual.
sterilization
WARNING
Always use protec tiv e e yew ear and glo ves whe n c lea nin g a nd dis inf ecting p robes and b iopsy gu ide ada pters.
CAUTION
Biopsy guide must be cleaned after each use. Cleaning the biopsy guide adapter is essenti al steps prior to effective disinfection or steriliza tion. Be sure to follow the manufacturer ’s instructions when using disinfectants. Do not use bleach to clean or sterilize the biopsy guide adapter. Using bleach on the adapter may cause damage and will v oid your warranty.
To clean and sterilize stainless steel biopsy guide ?? CLEANING ¨ç After
use,
¨è Disassembl e use
remove the
parts.
¨é Usi ng
a
¨ê Rinse
biopsy guide
guide
into
assembly
its
from
component
the
parts,
p i
These not parts be resterilized. ca
s mall
reusable
the
biopsy
brus h
and
wat er,
s crub
each
part
to
re
components.
with
water
to
remove
remaining
particulates.
?? STERILIZITION ¨ç Sterilize ¨èAfter
method
the
damage MEDISON
clean
biopsy
guide
and
adapter
by gas autoclaving (Ethylene
follow terilization the proper procedure po st
Oxi (Ste
for
th
used.
¨é Inspect
To
the
sterili zation,
is
b iops y
gui de
evident,
ad apt er
fo r
dam age
s uch
discontinue adapter us e of and thecontact biops
a
yo
representative.
sterilize
stainless
plastic
biopsy
guide
?? CLEANING ¨ç After
use,
¨è Disassemble use
parts.
¨é Usi ng
a
Service Manual
the
with
the
biopsy
These
s mall
reusable ¨ê Rinse
remove
parts
brus h
biopsy guide
into
cannot
and
guide
be
wat er,
its
assembly
from
the
component ard the parts, single if
resterilized.
s crub
each
part
to
components. water
to
remove
p
remaining
particulates.
Published by C ustomer Servic e Department
re
Sec tion 1-2. Instruction ?? STERILIZATION
Reusable CAUTION
plasti biopsy
radiation
¨çSterili ze sterilant time
The
guide
compatible terilization cold will
the
components
following
10
through
ultrasound
product
Plus
by
the
hours)
the
damage
be
sterilized
these
by
o
auto
parts.
using atible a terilization chemically cold com solutio FDA
and
are
FDA
can
Sterilization
510(k)
solution
process
recommended
510(k)
is
reco
temperature
used.
because ectiveness of
process)
and
its
bo (as chem
materials.
Country
Cidex Cidex
by
disinfectants
qualified
Solutions
permanently
qualified
(usually
adapters
solution.
Type
Active
ingredient FDA
510(k)
USA
Liquid
Gluteraldehyde K934434
USA
Liquid
Gluter ldehyde
K923744
¨ è After sterilizatio n, follo w the proper -post sterilization procedure for method used.
the steri lizat ion
¨ é Inspect the comp onents fo r damage such as cracks, rust or breakage. If damag e is evident, discontinue use of the biopsy adapter and ntact co your local MEDISON representative. ??
2.3.3 SYSTEM SURFACES The exterior sur fac es of most MEDISON ultrasound systems can recommended disinfectant with a wipe method. You can use the following procedure to disinfect system sur
be disinfected using a
faces on these systems.
WARNING
Always use protective eyewear an d gl ov es wh en cl ea ni ng an d di si nf ec ti ng an y equipment.
CAUTION
Use only recommended disinfectants on system surfaces.
?? CLEANING ¨ç Turn ¨èUse
off
a
the
sof t
surfaces
on
system
cloth the
and
lightly
disconnect dampened
the the system wall outlet. power cord in
a
mild
soap
or
d
system.
?? DISINFECTION ¨çMix for
Service Manual
the
disinfection
solution
solution h. streng A disinfectant
compatible qualified
with by
your
the
FDA
Published by C ustomer Servic e Department
syste 510(
Sec tion 1-2. Instruction ¨è
Wipe the system surfaces with the disinfection solution, follow ing disinfec tion label instructions for wipe durations, solution strengths, and disinfectant contact duration. Ensure that the solution strength and duration of contact are appropriate for the intended clinical appl ication .
¨é
Air dry or towel dry with a sterile cloth according t o the instructions on the disinfectant label.
2.3.4 Protect Circuit
??
??
Fuse Replacement ¨ê
Open the fus e drawer on the upper side of the appliance inlet, there will be the two fuse holder.
small
¨ë
Push the fuse holder toward the arrow direction, and Pull the fuse holder toward the upper side of the appliance inlet.
¨ì
Remove the old fuse by pulling up.
¨í
Install the new fuse by pushing to the fuse holder.
¨î
Insert the fuse holder to the appliance inlet. At this time, the arrow direction on the upper sid e of the fus e ho lde r shoul d be in a cco rda nce wit h that on t he f use dra w. Also, the same method is used to e xchange t he ot her f use h older.
¨ï
Close the fuse drawer
Regular Fuse Electricity
Service Manual
Input Electricity
Fuse Electricity
100- 120VAC
50T6.3L / 250V
200- 240VAC
50T3.15L/250V
Published by C ustomer Servic e Department
Sec tion 1-2. Instruction
Fuse Drawer
Kauttu. Box Nur Sicherung 250V Use Only With A 250V Fuse Employer Uniquement Avec FusibleDe 250V
AC INLET
Figure-A. Appliance INLET
Close
x 2EA Open
Fuse Holder
Figure-B. Side view of Appliance INLET
Service Manual
Fuse
Figure-C. Inserting Fus e and Fuse Holder
@ s.h.kim 1996 Feb
Published by C ustomer Servic e Department
SonoAce 6000II
Section 1-3. Installation Guide
System location and check-out Avoid the following environments for operation or storage
Service Manual
Published by Customer Service Department
SonoAce 6000II
Section 1-3. Installation Guide.
3) PROBE Installation
Service Manual
Published by Customer Service Department
SonoAce 6000II
Section 1-3. Installation Guide.
3.3.1. Rear Panel ou can connect the system with peripherals, such as monitor, pr Y Panel at the rear part of the system.
inter, or VCR through the Rear
This sends video signal to Main Monitor
This sends video signal to B/W Echo Printer
This sends video signal to VCR
This is port for foot switch
This can control VCR by the Serial port
This is port for Line Printer
This is USB port. This is the access to the Intern et Line (Ethernet), and can be applied to the option, DICOM
This sends VGA signal to the monitor.
This is B/W printer remote cable port.
Service Manual
Published by Customer Service Department
SonoAce 6000II
MEDISON Co.Ltd.,
3.3.2 Echo Printer
3.3.3 VCR (Video Cassette Recorder)
[ the alphanumeric ke ‘PLAY’, press X]on
yboard or [EXIT]button on the
control panel.
Service Manual
Published by SERTECH
- 12 -
SonoAce 6000II
MEDISON Co.Ltd.,
3.3.4 Line Printer
’t b e
confusedw henyouuseL ineprinte.
3.3.5 External Monitor
Plain Monitor
3.3.6 Foot Switch
Service Manual
Published by SERTECH
- 13 -
SonoAce 6000II
MEDISON Co.Ltd.,
Preventive Maintenance Procedure for SA6000II This procedure should be completed using the same environment that is used when the customer is performing daily exams, for example: Use the same examination room, the same wall outlet, and especially during image quality evaluation, the same room background lighting conditions.
1. Press the Power On switch on the main side panel and confirm the following : ¨ç Keyboard lights up. ¨è LED on monitor lights up green color. ¨é
At first the MEDISON logo will appear and then the System execut
es up in the standard
B-mode format. 2. On the Display Monitor, confirm the following : ¨ç Adjustment of the monitor brightness and contrast controls fro
m the minimum to
maximum results in no distorti on(blooming) on the display. ¨è Display is centered on the sc
reen, with good vertical and hori
zontal resolution (linearity).
¨é There is no tearing or bedding at the corners.
1. For each Probe attached to the system, perform the following tests, and confirm proper operation : ¨ç Visually Inspect the head of th
e probe to insure that there ar e no cracks, separation, or
peeling of the insulating material on the face of the probe. ¨è Knife test : With a light coatin
g of Echo Gel on the face of t
he probe, slowly scan across
the elements with a thin flat blade, while observing the display columns of echoes, with no blank lines that would indicate missi
for the resulting bright ng or faulty channels in
the probe.
Screen image
Service Manual
Published by SERTECH
- 14 -
SonoAce 6000II
MEDISON Co.Ltd.,
¨é P EC B O R ÌÀ À E L B A ³ª  °Å ߸® ³ª ¸¶Â ö°Å îÁ õ¾ û·ÎÀ Ѽ ÎÇ ÌÀ »óÀ Õ öÈ Á ´Â Ö ¿. Ã Ê Ï½ ÎÇ À ® ¨ê C onectrhousing°úscrew °¡À ß°íÁ îÀ ¾ Ç ¤µ öÁ Á ´Â Ö . ¿À Ã Ê Ï½ Ç ¡°Ë 2.F oreachM echanilectorSP r
obeatchedtothesytem ,conf
irmthefolw ing:
¨ë O bservthahetnoseconeisnotared,mscrathed,orpelin
g.
¨ì ervO bsthatherearenoirablesurlesm a(hant3 minsi
zereae)ablptcbleisv
inthefaceoftheprobe. 3.O btainasuitableim ageon
¨í O bservthaherea trenosign
soffluidleakgaroundthese
thedisplayandconfirmthefolw
¨ç T herearenom isnglinesof
alsornosecone.
ing:
at(dropout)inthese inform
¨è T hem otrrunssm othlyandquie
ctor. tlyw ithnoabnorm lnockig
sound.
¨é E ineethpberocableandrm xam ncfiohatea therrenos,utccr
s,im protearsinhet
insulato. ¨ê Inspectethorectnusinghona
dcirm onfhatcrew s,astenf
rs,ndasm cplaareal
secur.
leaschektheeachfunctioof P
thesytembyoperatinm anul
.
Service Manual
Published by SERTECH
- 15 -
SonoAce 6000II
MEDISON Co.Ltd.,
Service Manual
Published by SERTECH
- 16 -
SonoAce 6000II
MEDISON Co.Ltd.,
SA6000II Preventive Maintenance Check List Date :
Name of Distributor :
Name of Hospital
System Serial #
Name of User
Version #
Address
Warranty Expiration
Phone #
Instructions :
All of this information is necessary for the warranty. Check appropriate box below upon the completion of each section of the procedure.
Items Ι.
Good
Bad
1. Power on Sequence and system diagnostics
2. Monitor display
3. Key Board Test
1. Appearance Condition
2. Knife test
1. 2D Mode
2. M Mode
3. Measurement Test
4. Zooming & Cine memory Function Test
5. Image Filing Function Test
1. Power Supply
2. System Calibration
3. Power Cord/Plug and 110/220 switch
1. Circuit boards, plugs, jacks, and connectors seated
2. Handles & probe holders, monitor, metal panels and wheels
Check the packing items (compare with packing list)
ΙΙ.
System exterior cleaning procedure
ΙΙΙ.
Probe appearance
Remarks
A. Functional operation & test (system initialization state)
B. Probe test (with each probe)
C. Operational Mode Tests
D . Electrical Test & Calibration
E. Mechanical operation
Service Manual
Published by SERTECH
- 17 -
SonoAce 6000II
MEDISON Co.Ltd.,
3. Seating & connection of cables & cords to peripherals F. Echo printer, External monitor, Multi-form camera, VCR
Please send this form to MEDISON by FAX or Air Mail after Fill out the above boxes completely, Confirmation Signature
Name of Distributor Service Representative
Customer
Service Manual
Published by SERTECH
- 18 -
Section 2-1. PSA Board
1. PSABOARD
PSA (Probe Select Array) has the function which interface System and Probe. Probe Select Board has two 156
- pin cannon connectors , and eac h pin is defined t o divide Probe ID and Port A/B, and it
is made by Relay circuit to select either of th
e two probes.
1.1 Generic Pin outs 1.1.1 Slot connector
It can define various kinds Probe ID and Slot Connector Pin outs
accor ding
to Port Select like
belo w ta ble.
Pin J1 (1 82 ) J1(181)
Signa l /R_ A /R_B
Function P ort A S el ec t Po rt B Se le ct
J1 (176)
/P INSA
Port A Insert
J1(17 5) J2 ( 1 7 5 )
/PINSB P IDA 0
Port B Insert P o rt A I D
J2 ( 1 7 6 )
P IDA 1
P o rt A I D
J2 (1 81 )
P I DB0
P or t B I D
J2 (1 82 ) J1,J2
Service Ma nual
P IDB1 ECHO 1 ~ 12 8
Por t B ID Echo
Published by C ustomer Servic e Depa rtment
Section 2-1. PSA Board
1.1.2 Cannon Connector
Connector
use 156 - pin connector of ITT cannon
Linear/Curved Array
1
2
3
4
5
EL97
EL105
GND
GND
EL2
EL65
EL73
EL33
EL34
EL42
GND
EL41
EL1
EL74
EL98
EL9
EL99
EL107
EL10 6
EL4
EL35
EL75
G ND
GND
EL3
EL43
EL67
EL68
GND
EL11
EL101
EL109
EL69
EL37 EL5
EL10 EL66
A B
GND EL12
C D
EL44
E
EL76
EL100
F
EL108
EL6
GND
G
EL77
EL14
EL38
EL46
H
EL45
G ND
GND
EL70
EL78
J
EL13
EL103
EL102
EL110
EL8
K
GND
EL111
EL71
EL16
EL40
GND
L
EL47
EL39
EL7
EL15
EL79 PIDA0
EL48 PIDA1
EL113
EL121
/PINSA GND
EL49
EL89
EL81
EL50
EL36
6
EL72
EL80
EL104
EL112
EL18
EL26
EL58
N P R
GND
EL57
EL17
EL90
EL25
EL115
EL123
EL122
EL 20
EL83
EL91
GN D
GND
EL52
EL6 0
U
EL51
EL59
EL19
EL84
EL92
EL116
V
GND
EL27
EL117
EL124
EL22
GND
W
EL125
EL85
EL93
EL30
EL54
EL62
X
EL53
EL61
GND
GND
EL86
EL94
Y
EL21
EL29
EL23
EL118
EL126
EL24
Z
GND
EL31
EL55
EL32
EL56
GN D
EL63
EL87
EL95
EL64
EL88
EL98
EL119
EL127
GND
GND
EL120
EL128
Service Ma nual
EL114
EL82
M
GND EL2 8
S T
a b c
Published by C ustomer Servic e Depa rtment
Section 2-1. PSA Board
1.2 Probe Switching
1.2.1 Probe Switching
It uses
Relay A GN21012 to do switching either of the two Probes.
pole/2 - thow switch
in o ne chip, and it i s La tched type. These R el
/R_ A_4 sig nal aft er r ece ivi ng t wo / R_A Relay, and switching . /R_A_A and
Relay A GN21012 have two
1-
ays make /R_A_1 , /R_A_2, /R_A_3,
, /R_B sign al fr om B F boa rd. A nd it make s Gr oupi ng ea ch
/R_A_B, /R_ AB_A and /R_AB _B are same signal . These
switching
table is same as below table.
/R_A
/R_B
Probe Port
0
1
A
1
0
B
Switching of Table Relay 1.2.2 Probe ID and Port recognition
The resistance value of Probe ID is connected from PSA to RX B/D. BF reads the value of /PINSA,/PINSB, to recognize Port, and Port Main S/W output Prot Out.
/PINSA
/PINSB
0
0
Probe Port A,B
0
1
A
1
0
1
1
B No Probe
Probe Port recognition 1.2.3 Relay Switching
Diagram
System
Probe Element Switching Port A
ECHO +
/R_A
-
Port B
+ Relay switching diagram
Service Ma nual
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Section 2-1. PSA Board
1.3 PSA B/D Configuration Diagram
SA6000II PSA
J3
J2
Service Ma nual
J4
J1
Published by C ustomer Servic e Depa rtment
Sec tion 2-2. BF & RX Board
2.BFandRXBoard
2.1 BF and RX in the whole system
SA6000- II is developed only B/W mode ultrasound diagnosis system. Ultrasound syste m has standa rd flow as Tx
- > Beamformation - > Mid - proce ssing - > Digita l Scan
Conversion - > Video Manager - > Monitor.
Tx Pulse TARGET delay line Transducer Tx Focus RF -> Baseband
MONITER
Time Gain
Rx Focus
Compensation
MID Proc
DSC
VM
Focused signal target Transducer delay line
FM
FM
StandardstructureofUltrasoundsystem
Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-2. BF & RX Board
SA6000- II is very sim ple com par ed wit h SA9 900 , bec aus e it is diagnosis system . And it is possible that integra te
only B/ W mode ultrasound
Mid - proces sing, Digita l Scan Conv ersi on, and
Video Manager in one board . So, the main boar d of SA6000 - II is three boar ds (DSC, BF, RX), and the other boards a re Power , PC, Key, Mother Board (Back Plane), PSA (Probe Select Assembly, Front Plane)
SA6000-II Structure
MONITER M o th e r B o a r d Rear Board (B a c k P la n e )
RX BF
P S A ( F r o n t P l a n e )
D SC PC
POWER
NETWORK
Standard st ructure of SA6000 - II
This chapter explains about BF and RX.
2.2 Feature of BF and RX in SA6000 - II
SA6000- II is only B/W mode popular ultrasound diagnosis system. becaus e this syste m is not suppor t
Color /Dopp ler Mode and
has Folding structure. Then it c an make 64 32- channel. Moreover this system makes 128 is possible to su
It is not necessary Steering,
Phased Array Probe. Also, this system
- channel resolut ion im age, althoug h internal struc ture is - channel effect, because it supports Syntheth ic. Also, it
pport Ap odization, maximum 64 - step Recei ving Dy nami c Apert ure, ma ximu m 16 Tx
Focal Point. Now, the Sampling frequency of RF signal is 30.8 MHz, but it is possible to be upgrade to 61.6MHz without changing circuit. The B F and R X of SA 600 0 - II has very simila r function to B F of S A9900. Bu t that o f SA 6000 Foldin g St ruct ure t o re duce price and n umber of b oard. If R x is 64 Service Ma nual
- II used
- chan nel, it is nece ssa ry tha t
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Sec tion 2-2. BF & RX Board
MCB014 is 16e a, ADC is 64ea , TGC is 64ea . But SA 6000
- II use d just 8 ea MCB 014, 3 2EA ADC , 32ea
TGC by usin g Analog Switch of 16ea MT8816.
M/ B DS C M ID PROCESSING MODULE
RF_DATA [0..15] B/ F RO_OUT A/ D C [0..31]
AD [0 .. 31 ]
TX_PN BFICs [0..127]
_D [0 .. 7]
ECHO Tx Pulser ASICs [0..127]
PS A RX TGC_OUT TGC_IN RO_OUT TGC REORDERING Rx S/W [0..63] [0..63] [0..63]
ECHO [0..127]
Data Flow of BF an d RX
Abo ve picture is the data flow of BF and RX. Tx trigger signal to be made at BFIC of BF shoots pulse through Tx pulser ASIC. Also, Echo signal to c ome from probe is p a this step it performs Reordering(or Folding)
ssed Pr e - amp step, an d in
to rein force weak sign al. Signa l to be perfo rmed
Reo rde rin g is tra nsm itt ed TGC - M/B( Moth er Board )
- BF, perform ADC at
BF, and is became
summing at BFIC.
Service Ma nual
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Sec tion 2-2. BF & RX Board
2.3 B F Boar d
BF of S A6000- II c an d ivide f our part fu nction ally, T x Pa rt, BF IC, AD C Gr oup, an d BF Controller . Tx part is part to shoot High Volt age( +/
- RX Bo ard
- 80V) i n suit able c onditi on. BF IC is part that it
sends Trigger signal to Tx Pulsing according some Focal point, and
performs summing AD input
signal to come from each Channel by Dynamic Focusing method according to Geometry of each probe, and transmits the result to Mid
- process ing Modu le of DSC . ADC Group is A nalog cir cuit par t to
be inc luded LC filter to have AD Conver
ter (AD9283 - 50). BF - RX contro ller is part that contr ols each
Digital device by using XC95144 - TQ144 CPLD to be possible Hardware programming.
Block[7] BF-CTRL /METRG /M_ETRG M_MCLK BUF's M_CLK p_mdata[15..0] p_data[15..0] h_maddr[2..0] h_addr[2..0] h_mdata[15..0] h_data[15..0]
Block[1] Block[0]
M_CL K /ETRG
Block[0]
p_data[15..0] M_CLK /ETRG h_addr[2..0]p_data[15..0] h_addr[2..0] h_data[15..0]h_data[15..0] MCB014(BFIC) tgc_out[n+3]An ti -a li asi ng AD C Filter tgc_out[n+2]An ti -a li asi ng AD C Filter tgc_out[n+1]An ti -a li asi ng AD C Filter tgc_out[n] An ti -a li asi ng AD C Filter
LVC08's+HV TX Pulser -HV TX ec o n ,n Pulser +HV TX Pulser -HV TX echo[n+7..n] Pulser
ad(n+3)_data[7..0] tx_out_p[7..0] ad(n+2)_data[7..0] tx_out_n[7..0] ad(n+1)_data[7..0] elem_sel[7..0] ad(n)_data[7..0]
MFC019's LV04's
BF Bloc k Diag ram
Ab ove pictur e is Block Diagram of BF . Ex citing signal from MCB0 14
(BFIC) is transmitted to
LV04(TTL, NOT gate) and LVC08(TTL, AND gate), and to probe element after conversion to High voltage at High Voltage Pulser ASIC(MFC019). Also, 32ea ADC to be Path that Analog signa l to come from Rx b
below part of picture is became
oard goes t o input of MCB014. Buffers a re became Gate at
Host, DSC, and Interfacing. XC is CPLD to be composed XC95144
- TQ144, and it is Controlle r. There
are more detail explanation at next section.
Service Ma nual
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Sec tion 2-2. BF & RX Board
2.3.1 Controller
Becaus e BF and R X wor k as if on e
boar d, it uses just one XL951 44 TQ - 144 in Controller . This
Controller control Digital Device as decodi ng of PC command when PC performs setting MCB014 inter register of BF or downloading data at memory of RX board. Also, it contains version information of BF Controller works with two part Host Model(it is said to be CPU model, or Halt model)
BF .
and Real
Mode. Timing Spec of input signal to be matched Host Model is same bel ow picture.
/CPU_CS /CPU_WR CPU_ADDR
ADDR
CPU_DATA
DATA Ts
TH
Ts
When it is Host Mode, Time Spec Diagram of
TH
input Signa l
Real Mode have two input signal, and it is necessary /ETRG and Time Spec of make ac cura te bf_d elay sig nal. 8e a BFIC of SA 6000 each channel. Bf_dealy is at a minimum time to necess
Master Clock to
- II per form s input R F signa l Beamf ormi ng fro m itate a t BFIC .
/EX_TRG MM_CLK
When Real Mode, Time Spec Diagram of Input Signal
As below picture, the signal of data_out_ready is connected to output pin of BFIC. This pin is the signa l to annou nce, which BFIC performed summing to focu
s RF signal came from 4ea channel and
preparation to add with BFIC is finished. Before preparation step, the signal is High Impedance state. But finished preparation step, the signal become LOW state. But the Driving ability of this output pins is shor tage , so it makes bf_delay signal at BF_CTRL. So bf_delay has more long time than point in time which all of data_out_ready become LOW.
The last data_en_b signal is delayed as number
of
BFIC * 3 M_clk, and it become rf_dvs(RF Data Valid Strobe) to go to Mid. Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-2. BF & RX Board
/ETRG M_CLK BF CTRL BF_DELAY DATA_READY_OUT
DATA_OUT_READY Board_DIR DATA_EN_A DATA_EN_A DATA_EN_B BFIC #7 EXT_A[ ] EXT_B[ ]
DATA_OUT_READY Board_DIR DATA_EN_A DATA_EN_B BFIC #6 EXT_ A[ ] EXT_ B[ ]
DATA_OUT_READY Board_DIR DATA_EN_A DATA_EN_B
DATA_OUT_READY Board_DIR DAT_EN_B DATA_EN_A DATA_EN_B (RF_DVS)
BFIC #(---) BFIC #0 EXT_ A[ ] EXT_ B[ ]
EXT_B[ ] EXT_ A[ ] EXT _B[ ]
Summing Chain and bf_delay of B FIC
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Sec tion 2-2. BF & RX Board
2.3.2 BFIC
The B eamformation o f SA6000 - ll is mad e at MC B014 s imila r Cell - base d ASI C. MCB01 4 per form out put nec ess ary sig nal aft er T x Fo cus ing and Rx F ocu sin g ca lcu lat ion. Eac h 8
- bit of t x _p_out,
tx_n_ou t, and elem _se charge Output about TX. Delay is based on Scan lin e is calc ulated by Micro
-
processor of MCB014 with Geometry of probe. Micro code to calculate Tx Delay is a litter complex, because it ha s diff erent Dela y acco rding t o Scanl ine.
But th e value i s just p hysical De lay. M CB014 at
Rx Focusing is not necessary different Dynamic Focusing according to Scan line, because the signal is finished reordering from Rx board. MCB014 can Programming about various Scan line, Tx focal point, T x foc using calculation, and Rx Dyna mic focusing calculation. This pr ogram is Microcode. It is Binary Code. It is necessary time to calculate Tx/Rx Focusing depend on Type. Therefore Scanline and Line Type information to use at MCB014 come out before one PRF tha
T1
T2
T3
n Scanline to use at DSC.
T4
LT[ ] A
A
SC[ ] /ETRG P_WR 1.0-us
160.8-us 3.0-us
Timing Diagram for Microcode Execution
When T1, As see above picture, P_WR takes Scanline A to Tx/Rx Focusing of scanline A. And it saves at
with Rising. During T2, it calculates Data
special regis ter (RX_I NIT_M EM, TX_IN IT_MEM ) of
BFIC. When T3, this saved Data, it is wrote another special Register (RX_WORK_MEM, TX_WORK_MEM) of BFIC. During T4, it i s used at Tx o r Rx Dy namic focusing.
Service Ma nual
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Sec tion 2-2. BF & RX Board
2.3.3 Tx Part
SA6000- II has 64ea MFC019 Chip same as Full Cus tom ASIC, because it supports maximum 128 element Probe. One chip has two independents Pulser, and Triggering Input is 3.3
-
- V level sig nal. One
MCB014 can suppo rt maximum 12 - channel Tx, but SA6000 - II has just 8ea MCB014. So, it use be low method t o support 1 28 P uls er. SA60 00 - II can perf orm maxim um 64ea Tx fir ing at once, and Rx element switching is not performed by 12ea elem_sel Bus of MCB014 like SA9900. Therefore it can use 128ea Pulser independently after dividing 64ea by 64ea by using elem_sel Bus. Below
picture is
diagram.
LVC08 MCB014
+HV TX Pulser -HV TX Pulser
tx_out_p[n]
+HV TX Pulser
tx_out_n[n]
-HV TX Pulser
echo[n+64]
echo[n]
elem_sel[n] MFC019 LV04
One channel Tx Part Diagram
2.3.4 AD Co nverter Group
All of the sig nal to c ome from Rx b oard to BF board is Analog signal. Therefore, it is necessary ADC to A/D Conversion. SA6000 - II needs 32ea ADC, be cause it is 64 - channel Folding structure . And it needs 8ea MCB014. Bf of SA6000 - II use s AD92 83 - 50 to AD C. The pres ent ti me, Sa mplin g Cloc k is 30.8 - MHz. But if you change L and C of Anti
- aliasing Filter and AD9283 - 80, you can use 61.6 - MHz
Sampling Clock. Th is ADC input part has Anti - aliasing F ilt er to be com posed 4 Filter. And the structure and spectrum is same below picture. f
Service Ma nual
- order L C Lo w - pass
3dB= 10 - MHz.
Published by C ustomer Servic e Depa rtment
Sec tion 2-2. BF & RX Board
Anti - aliasing Filter in SA6000 - II BF
Anti - aliasing Filter Fre quency Response for SA6000 - II BF
2.4 RX Board
RX Board compose Analog Device except SRAM Controlling part. Echo Signals from Element of Probe trans mit to Pre - amp to compose with 2ea NPN - transis tor. And it performs Reor deri ng, and goes to BF af ter passin g Time - gain Co mpensator. The standard structure is sa me be low p icture.
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Sec tion 2-2. BF & RX Board
echo[n+64]
RX-S/W
Latch (HC164)
MEMORY (32KB)
TGC_D[..]
pre_sel[n+64] D.F/F (HC175)
C A D
AX[..]
TGC-Curve
pre_sel[n] RE -
echo[n] RX-S/W
p re -Am p
to BF
ORDERING AN AL OG SWITCH
TG C AD60 4AR
MT8816
SA6000- II RX Board Bloc k Diagram
2.4.1 Element Selection and Pre - amp Part
SA6000- II is 64 Channel, but it can support maximum 128 the - other me thod to cho ose f or in put s ignal of Pr e
- element Probe. So. I t use s one - after -
- amp. Eff ective Ec ho Sig nal to co me eit her of t he
two (Echo( n) and Echo(n+64) ) become Inact ive, because PRES EL(n+64) becom e to LOW whe n PRESEL(n) become HIGH ACTIVE. This D evice is p erforme d at Cont roller of B F.
2.4.2 Reorder ing Part
SA6000- II is 64 - channel Syst em, but it can redu ce the number of TG C Device, AD Co nverter , and Beamforming IC(MCB014) until half by Reordering. The mean of Reordering is to relocate sequence. It transmits to be changed Echo Signal according to Scanline always at same locate by Analog
switch
(MT8816). SA6000 - II doesn¡ t¯use Steering Technique like Trapezoidal Mode or Phased Array. So, when it per form s Reor derin g at C D2M3 494, It tr ansmit s sum ming d ata t o TGC i
nput p art. This is
Folding. And it is possible to reduce TGC Device, AD Converter, and BFIC until half by Fol
ding
Technique. And it can use Beamformation. This method is same below picture.
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Sec tion 2-2. BF & RX Board
TGC channel(0)
TGC channel(1)
TGC channel(2)
An al og Sw it ch (C D2 2M 349 4)
elem(n-2)
elem(n-1)
el em (n )
ele m(n +1)
elem(n+2) elem(n+3)
sc = 4 n
When scanline is 0,4,8 --- , Folding and Reorderin g
TGC channel(0)
TGC channel(1)
TGC channel(2)
An al og Sw it ch (C D2 2M 34 94 )
elem(n-2)
elem(n-1)
el em (n )
el em(n+1 )
elem(n+2)
sc = 4 n + 2
When scanline is 2, 6, 10,
--- , Foldi ng and Reordering
At the above pic ture, CD2M3494 Ana log switch which charge Folding/Reordering is composed with total 16ea. The struc ture and Time Diagr am of C ontro l SA[6..0], CS[7..0], AY[2..0], RST, and STRB signals are
Signal is same b elow t wo pic tures.
made at Controller of BF. A X[0..3], DATA
signals come from S RAM(UM61256) in R X Boar d.
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Sec tion 2-2. BF & RX Board
2.4.3 Time - gain Compensation Part
The Echo signal to be reflected from far Target is very small size than signal to be near Target, because it oc curs Attenuation at medium
reflected from
. Theoretical ly, if it suppose that Dep th is z, it
has relation exp - 2z / z. And according to Depth, it compensates Attenuati
on by multiply i t by z exp 2z.
It is Time - gain Com pensation(or TG C ). The ma in compo nent is AD 45003 (it is same AD 604).
2.4.4 Memory Part
Memory is 32 Kbyte SRAM(UM61256), and it has information about Reordering Data and Element Selection. Below pictur e is signals to control SRAM, and flow of signal to be
CPU_DATA
A
DIR B BUF
/MEM_EN
/OE D
Q
MA_CLK LATCH /OE
controlled by SRAM data.
S/R pre_sel[0..7] DATA[8] D D Q /ENQ SR_CLK psel_clk0 /SR_EN LATCH DATA[6..4] /OE DATA[3..0] DATA AX[0..3]AY[0..2] ADDR SRAM Y[0..7] X[0..15] pre_sel[8..15] /CS /OE/WE RSTCSSTRB DATA D Q /MEM_CS R/O S/Wpsel_clk1 /MEM_OE /MEM_WE LATCH /OE
DIR SC[8..0] B addr_cnt [6..0] A BUF D
/OE
Q
pre_sel[56..63]
psel_clk7 LATCH /OE
/psel_oe Data on the SRAM(UM61256) circums tances
At the above picture, Address and Data of SRAM are information on h_data[15..0](cpu_data and h_data is same meaning). Control Signal from BF divide two signals.
8- bit Data Bus have like below information ?? D[7..6] ? There
?? D[5..4] ? it
has
?? D[3..0] ? There
Service Ma nual
is
Element
Control
is
according to each Bit. Selection
Bit
AX[3..0]
information
information
information
to
of
be
to
be
called
CD2M3494.
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saved
Data
of
Sec tion 2-2. BF & RX Board
Below part is 15ea Address Bit Map . ?? A14
Synthetic
On/Off
?? A[13..6] ? scanline[8..1]
– Because AX[3..0] of CD2M3494, D ATA Control and Element Selection inform ation
?? A[5..0]
is sav ed in se ries, it t akes out in t urn b y usin g ext ernal 6
- bit C ounter. Thi s Cou nter exi sts i n
Controller of BF. To take out this Data faster, it reduced time by dividing Shift Register. ?? Data
to
be
ro.dat.
2.4.5
When
you
one).
see
to The
only
Bit Data on port, A
Service Ma nual
in
Data
are
Low
enter
wrote
SRAM
at
SRAM
is
saved
by
Host
to
Binary
when
it
Format
performs
m
Part
of
which
the
port
system, port the
to ID read Port with is Active
signals
port, or B
to
is
front
select
port,7 Bit become and
it
Probe ntification Id
necessary 1
going
And
or
to
all
Probe Prob
Signal. come port,
IDbit. only If lowthere rank
But port, there Bit become is probe Low
from or
and right left probe probe port. port port It is
system port hasisto 0 read. zero)
BF
and
nothing
Back
any
A is is
and At th B is 6
prob
state. on 7 A
B
Plane. probe The
port,
and
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what
Sec tion 2-3. DSC Board
3.DSCBOARD
3.1 Specification
640
??
Overlay
??
PC
??
Support
Synthetic
??
Support
left/right
??
Support
3D
??
Support
VM
??
Support
??
Support
Edge
??
Support
Dual
??
Maximum
CINE
??
Maximum
LOOP
??
Gray
Service Ma nual
*
480
’t support 800*600 mode)
??
screen (don mode
to (RGB VGA
i nterface
16bit
with
Data
Data
PCI
not
M ode
ISA
(128
format
Acquisition
display
Left
Frame
Line
is
is
resolution
Channel
for
with
:
256
e xpansion)
M ode)
BM top/bottom mode
Enhancement
Cine(
(Address
for
Acquisition
interlace Non
scale
Data)
Volume
Read
64
(
Rendering
Image
VGA
format
Save
sync
(PCI
(PCI
Read)
signal
Zoom
Frame Frame),
Density
:
Right
128
Frame
4096
is
i
256
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,
Fa
Sec tion 2-3. DSC Board
3.2Featureand Concept of DSC
Scan conversion in Ultrasound scanner means the procedure from mapping echo informa Frame memory to displaying to monitor.
This scan conversion actualizes
tion to to high technology then
need conversion from sampling data to pixel data. Conventional DSC But
writes
to F/M as vertical direction and reading from F/M as Horizontal direction.
this DSC of SA6000II
Why this DSC
differe nt
it writes
from F/M and reading from F/M as Horizontal direction.
conventional DSC writes and reading method
Forthemoment, DSCof SA6000IIusednewtypecomponent.
FFO
FM
FM
Convent
ionaltype(abasisWrite)
FM
SSRA
FM
SSRAM
S A 6 0 0 0I It y p e( ab a s i sW r i t e )
SSRAM
Service Ma nual
FM
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3.3 DSC description & Block Diagram
3.3.1 Overall Block Diagram
DSP
DSC
VM
(Synthetic)
SRAM SRAM (Even) (Odd)
CINE SDRAM (128M x 2)
SSRAM (128K)
VCR IN
3D FIFO (PCI)
Scan Converter (I-->NI)
Image Grabber (SDRAM) Image Acq FIFO
INPUT DATA(B,M) MID ASIC (MGA015)
InputCTR (XC2S200)
Video DAC FM,LOOP CTR (XC2S200)
Image Filing (PCI)
NI Video Out
POST CTR (XC2S100) Video DAC
VGA(16bit) R(5bit) G(6bit) B(5bit)
RGB Out
InputCTR DSC DSP
FM,LoopCTR
FM (B) (SDRAM)
LOOP(M) (SDRAM)
Mode Converter
PostCTR
Scanline DSC DSP
RTC CTR (XC2S30)
Linetype , RLinetype /OF , /RP , XSYNC
SA6000 II DSC Overall Block Diagram
Above pictureof one DSC of the SA6000II showing be made with MGA 015 of MID processor, SRRAM part for Synthetic of DSC and Video manager board. This DSC of SA6000II is make B/W part of SA9900 (DSP, DSC and V /M board)
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3.3.2 Block Diagram & Signal Flow of each part
1) DSP PART (MGA0 15 : MID Proces sor) MGA015A makes I and Q data to process B/W image, spectral doppler and color doppler with RF data to be transmitted from Beamformer. But this DSC of SA6000II handled B/W data.
(1) BLOCK DIAGRAM
Synthetic Aperture Memory
BF Data
ATGC
To BF
Synthtic Aperture
DTGC
Decimation FIR Filter
1/N Decimation
DC Cancel FIR Filter
Quadrature Mixer
Zone Blend
M/N Decimation
Pixel Decimation
Log Compressi on
Envelop Detection
Dynamic FIR Filter
BHF NSF
BW Post
To DSC
Mid- Processor(MGA015A) Block Diagram of BW Part
(2 )MGA 015A Function
¨ ç Synthetic Aperture Control
Fi rs t TX /R X CY CL E
Se co nd TX /R X CY CL E
ΡΑΜ RXB/F
SUM RXB/F
TX
? Service Ma nual
ΟΥΤΠ ΥΤ
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Sec tion 2-3. DSC Board
The signal to execute first TX/RX is stored in
RAM like above diagram. After it sums
second TX/RX data with first data to be stored in RAM, transmit it to Output.
¨ è DTGC(DIGITAL TIME GAIN COMPENSAION) Response of Ultrasound becomes attenuation as deeper more and more. Using TGC to compensation this state. MGA01 5A execu tes DTGC (Digi tal Time Gain Comp ensati on), but Front
- end executes
ATGC(Analog Time Gain Compensation). DTGC execut es ou tput by multip
lica tion RF(Radio Freque ncy) from Beamfor mer and
DTGC gain.
Β/Φ ΡΦ
ουτ πυτ
DTGC
??
Feature
of
DT GC
? ΤΓΧ γαιν χοντρολ ρανγε
: −ινφ δΒ ∼ 30δΒ
? σταρτ (ορ Ινιτιαλ) γαιν ϖαλυε : −ιρανγε νφ δΒ ∼ +30δΒ ? Γαιν υπδατε ρατε ? ΤΓ Χ χυρ ϖε τψ πε
: 62ΜΗζ : πιεχεωισε λινεαρ
? Μινιµυµ γαιν ινχρεµεντ/σ τεπ
: <0.1δΒ/στεπ ωηεν στεπ= δατα ρατε, ατ 0δΒ
? ινιτιαλ ϖαλυε ρεσολυτιον
: Σαµε ασ Μινιµυµ Γαιν ινχρεµεντ/στεπ
? Μαξ ποσσιβλε γαιν χηανγε
: 10δΒ/χµ ≅λεσσ τηαν
0.1δΒ/στεπ,ατ 0δΒ
? ΣΓΧ(σχανλινε −γαιν χοµπενσατιον) :τωο 128 ωορδ λοοκ −υπ ταβλε, ϖαλυεσ, βετωεεν 0∼4095.0δΒ=128 ινδεξεδ βψ ♦ ∆ΕΧΙΜΑΤΙΟΝ ΦΙΡ ΦΙΛΤΕΡ ΜΓΑ015Α εξεχυτεσ το 61.6Μηζ χλοχκ. Ιφ νοισε χοµπονεν τ το χονταιν ιν ΡΦ σιγν αλ βεχ οµεσ δ εχιµατιον , ιτ ισ τ ρανσµι ττεδ αφτερ χηανγινγ λοω φρεθυενχψ ρατε. Ιν τηισ χασε, ΣΝΡ ισ δροππεδ, σο υσε ΛΠΦ(Λοω −Πασσ Φιλτερ) το ρεδυχε τηε νοισε.
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¨ ê 1/N DECIMATION
Noise
30.8Mhz
30.8Mhz
f
The clock of MGA015A uses 61.6Mhz. It is diff icult ne xt calculat ion because the tim e to can next calculati on is 61.6Mhz. So it uses 1/N. Decimation executes 1/N Decimation. When N is 2, for example, it indicates following diagram. It is meaning to select either of two data. The t ime t o be t ransm itte d dat a is
61.6 Mhz. The t ime t o be t ransm itted id
divided by this method ; 61.6Mhz/2=30.8Mhz.
: Output Data
: Input D ATA
DATA
t 61.6Mhz
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¨ ë DC CANCEL FIR FILTER There ar e DC co mponent around fr e quency z ero. To reject t his DC component , it us es HPF(high - Pass filer). And it executes maximum cut - off.
High pass filter
High pass filter Nosie
30.8Mhz ¨ì
f
30.8Mhz
0
QUADRATURE MIXER The operation to change RF data to componen t of base band is
¡ °quadrature
demodulator ¡ .±Mixer in quadratur e mixer is dem odulator in other wo rd. Main si gnal has to be loaded at center of frequency. If main signal is not located at center of frequency, you have to transfer that center of frequency. This is demodulator. It is method like following diagram.
¿øÇÏ ´Â ½ÅÈ£ Demodulator Nosie
f 30.8Mhz
30.8Mhz The s igna l to ex ecute qu adrature de modulat or ha s to us e Low
- Pass Filt er lik e fol lowing
diagram. Because of it needs to reject Noise component and unnecessary signal. After pas sed this Dy nam ic f ilt er, it i s se par ate d in to r oute to m ak
e BW image data and I, Q
data.
LOW Pass Filter
30.8Mhz
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¨í
DYNAMIC FIR FILTER It is called Dynamic filter, because it is changed cut
- off according to the depth.
f
3.5MHz ¨î
ENVELOPE DETECTION When the wave is transmitted li ke followi ng le
ft dia gram, make it posit ive dir ectio n wave
to reject negative direction wave like following right diagram.
0
t
0
0
t
t
¨ï
LOG COMPRESSION
OUTPUT
0 Service Ma nual
INPUT Published by C ustomer Servic e Depa rtment
Sec tion 2-3. DSC Board
Dynamic range of BW data to become Envelope display image directly. So it
detection is very large. It is impossible to
compresses the data. This course is compression. In this
time, it executes log compression. If the value is small, raises the Dynamic range, and valu e is lar ge, m akes s aturation. A s
image dept h is deeper, the noise beco
mes heavy
and the contrast small. Raising the contrast of deep depth and shallow depth makes changeless. So it makes the whole contrast similarly.
¨ ð PIXEL DECIMATION Real pixel number to execute out from M/N decimation minimum 2000. But pixel numbe
to nearest is transmitted over
r to receive at DSC is 1000~2000 degree. Befor
e
transmit to DSC, calculate real entered number as number of the pixel to need at DSC. And transmit it to DSC.
¨ ñ Zone Blending
ZONE ±¸°£
È¥ÇÕ
When there are several TX focusing, it has to focus several times. In this time, curve occurs like above left diagram. The sectio n between curve them is called Zone secti on. It mixes overlap section of Zone naturally. This is Zone blending. Foll
owing diagr am shows
gain to be g iven in each zone during mixing.
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a 0(n ) 1
n (depth)
0
a 1(n ) 1
n (depth)
0
a 2(n ) 1
n (depth)
0
a 3(n ) 1 0
¨ò
BHF(BLOCK
- HOLD
n
n
n
1
2
3
- FILLTERING), NSF(NOISE
n (depth)
- SPILCE FILLTERING)
Above diagram is BHF method. BHF(Block
- hold
- filtering) can take off the hole to be any
pl ac e in im ag e. It us es th e me th od th at co mp en sa te si mi la rl y wi th ar ou nd ga in af te r ave rage ar oun d dat a. NS F(No ise
- Sp lic e Fi lt er ing ) is op po sit e me th od with BH F. If the
gain in any place is very larger than around,
w e can th in k it is n oise. In this case, it
rejects pixel.
¤¡
¤¡
¤¡
¡¤
¡¤
¡¤
Service Ma nual
¡¤
¡¤
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Sec tion 2-3. DSC Board
¨ ó BW POST FILLTER BW da ta to b e fin ishe d all pr oce ssin g pas s LPF ( Low
- pass filt er) t o rej ect n ois e or
unnecessary signal before transmitting to DSC.
f
2) DSC PART Each FPGA block diagram of DSC as following;
(1) Input Controller Input Controller FPGA Data Generator
BW_D[0..10] (from MID Asic) Bit&Shift Saturation
SSRAM_Addr
SSRAM (256M Word)
AZM_D0..7] (to MEMCTR)
B Even FIFO (1k)
Frame Averaging
Input FIFO (1k)
Azimuth Intp
B Odd FIFO (1k)
3D Acq FIFO (MGA 015 x 2)
CINE SDRAM (128M x 2)
Loop_D0..7] (to MEMCTR)
First, Input controller is Input data process Bit shift and saturation from MID processor. Bit shift fe at ur e u se fo r s ma ll b it m or e t h
an av ail ab le b it o f MI D pr oc es so r of the DSC . In ca se C ha nn el o r
G a i n i s sm a l l , ef f ect iv e b i t of D a t a t o b e ex ecu t ed b y M i d P r ocesso r com es ou t sm a l l . The number of Mid Processor Data to come over for DSC is 11bit. If DSC uses just 8bit, it takes 8 b i t of M
i d P r oc ess or D a t a .
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B Even FIFO and B Odd FIFO is write one side by PRF and read other side by Hsync, likes ping pong method, to perform the Data by PRF
module. At this time, writing data to
1024EA by sampling CLK. (SA9900 write 2048 EA) Next
FIFO is write
step of Frame Averaging perform reading
the Previous frame ¡s¯1024 row data from Sampling Data 1024EA and CINE Memory.
As you see above Block Diagram, Cine Memory is not the same location with Frame Memory. It is same location with SSRAM, Row Data (Samplin
g Data) is saved on Cine memory.
Therefore Frame Averaging use Row Data, Finally Frame Averagi
ng data is saved to SSRAM and
Cine memory. But Address of SSRAM is 18bit(256Kword Memory), so there are some problem appear to OF and Vs ync is d ifferent when SSR A M Read/Write.
To solve it, like old 9900 DSC, write
with Ping - Pong method and read with each Vsync with for
OF. This memory structure control WEB to manage Even frame and Odd frame data,
because
SRAM¡s¯Data is 18bit. (Ping - Pong m ethod) SSR AM Add ress i s co me from Data Generation part of Input Controller. This Data Generation part write value, which concerned with Data generation
to
FPGA every times when image format is change when DSP initial time or mode change. Then SSRAMM address is m ade pe r each Hsync. 6000 II DSC is made from BW Part of
9900 Revision DSC, but it has two different parts. One is
Frame Averaging, and the other is 3D Read Pass.
As you see above Block Diagram, FA circuit of 6000 II DSC is composed of Interpolator in FPGA. But SA9900 is comp osed of SRAM. If it uses SRAM, it is not match Margin of Data on Timing. And 9900 Revision DSC is able to support Real Time 3D, and it is not use 3D Pass of old method. So 6000 II DSC uses different Pass to 3D Acquisition. At the above Block Diagram, it d oe sn ¡t¯have Pass to go from 3D Acquisition FIFO to CINE Memory directly. Also, it is necessary Scan Conversion because it has saved Row Data.
To make this, it makes Pass to write from CINE Memory to SSRAM directly. When it uses
3D, it
uses this Pass. But this Pass is able to use at Freeze mode. When it performs 3D Acquisition, first set Freeze, and move CINE Bank to S SRAM, and read Data at SSRAM like Real Mode, and perform Azimuth Interpolator, save Data to 3D Acq FIFO. And next step is to move Data to PC
by PCI CLK
Cycle like 9900 old Version. It is possible to carry Data by setting ROI box during 3D Data Acquisition. This method reduces 3D Acquisition time.
1024ea Sampling Data to get every PRF is saved at SSRAM in serial necessary capacity of ma
ximum 256 Scanline x 1024 Sampling = 25
order by /OF. Namely, it is 6 Kbytes. To get Frame
Memory Data(A , B , C , D , E) equivalent Pixel of Monitor, it is necessary SSRAM Address like a1 and a2 , b1 and b2, and so on. This Address comes out to Row direction ( and the difference of Previous Address and Service Ma nual
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Sec tion 2-3. DSC Board
point (SA6000 II is 1024 Sampling). It use s 61.6 MHz C LK to Azi mut h, but th e Outp ut is 61. 6MH z/2 . Nam ely, 1 ea( o
ne) Interpolation
Data (Z) comes out per 30.8MHz.
SL0 SL4
SL8
a1 1st H line A
b1 c1
a2 d1
C
D
d2 2nd H line
b2
B
e1 c2
E
e2 Sampling Point Monitor Pixel Point
(2) Me mory Cont roller Memory & Loop controller processing Read / Write of Loop memory, Frame memory, read zoom and edge enhance. First, writing to Frame memory for has 4byte
data bus and each 1byte saved different data of
Frame. Azimuth data from Input control FPGA write to In FIFO of memory controller This FIFO is use for don ¡ ¯t lost the data during memory cycle (Refresh, Pre charge and Act, etc.) Because of, this FIFO Length is shorter than the other FIFO. Next, Demux is demuxing 1Byte Data bus to 4Byte Data bus in order to Frame interpolation by Frame memory.
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FM & LOOP Controller FPGA AZM_D0..7] (from MemCtr) IN FIFO (63 x 8)
DEMUX (1 : 4)
16
32
Frame Interpolator
FI MUX (4:2)
DT FIFO (512)
Read Zoom
Edge Ehnance
B Out FIFO (512)
BW_SD0..7] (to PostCtr)
FM (SDRAM 64Mbit)
Loop_D0..7] (fM roem mCtr) M Input FIFO (512 )
LoopM (SDRAM 16Mbit)
M Out FIFO (512 )
Loop CTR
TMP_ABWSD (D0-D7)
FABW_D (D0-D7) Frame
1* 4 Demux (Wr)
TMP_BBWSD
Frame
Average
4 * 2 Mux (Rd)
(D0-D7)
Intp
Fm _W r
FMB_D (D0-D7, D8-D15, D16-D23,
M F
d R _
D24-D32)
FM
FI _ M U X B l oc k D i a gr am
Ab ov e p i c tu r e
ar e B l o c k D i a g r a m o f
FI _ M u x an d FI _ D e m .
The role of FI_MUX is to switch required Frame during Frame Interpolation. Because the data of Frame memory used now is 32 Bit and 8 bit us used for one Frame, 4 Frame could be stored at Frame memory. The 1 x 4 DEMUX of FI_MUX operates
Service Ma nual
this function (WR). The 4 x 2 MUX (RD) has
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the role of sending only two Frames of four Frames. The 4 x 2 Mux(RD) is controlled by FI_sel. The Frame Interpolation is to interpolation one Frame with the other Frame. The reason to execute frame interpolate is that the gap between present Frame and next Frame is so large t hat the image is not good. Read FM we can know which Frame is interpolatio n.
FI_Sel determines the selection of this Frame
The picture below is regarding Frame Interpolation.
F .M
F.M0 ( A ) A
F.M1 (B )
A F.I MUX (4*2)
F.M2 ( C )
F.I
Z (interpol ation)
B B
F.M3 ( D )
FI_SE L 0,1À Ì " 00 "À Ï ¶§ FI Bloc k Diagr am
Because Vsync is 60Hz, DSC DSP gives FI vector for one Frame Interpolation. Then the FI_Sel(0,1) is ¡ 0° 0¡ ±and give Frame A and Frame B to Frame Interpola tion input in the Frame Interpola tion MUX. The next Frame Interpolat ion Frame B. Output one Frame for each Vsync like A
makes Frame Z by interpolatin g Frame A and - >Z - >B.
This DT FIFO using when data erase of B Image like B
Service Ma nual
- M mode .
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.
Sec tion 2-3. DSC Board Read Zoom Block Diagram
s_RZ_InputB
s_rz_hintp_cur0 Read Zoom FIFO 0
PXL_CLK
H s_rz_hintp_prv0 Interpolator 0 Latch s_H_OutputB0
OutputB
V Interpolator
s_H_OutputB1 s_rz_hintp_cur1 Read Zoom FIFO 1
PXL_CLK
H s_rz_hintp_prv1 Interpolator 1 Latch
Read zoo m send data wit h signal of Sdo ut_En whe n active HS. First, edge Enhan cement wai t for active of Sdout_En , when active HS.
(Maxim um 1us)
Edge Enhance Block Diagram s_rz_data_out_b s_ee_fifo_wen0
EE FF 0
s_serial_data0 Serial Adder 0 s_serial_center0
s_ee_fifo_wen1
EE FF 1
s_serial_data1 Serial Adder 1 s_serial_center1
EE FF 2
s_serial_data2 Parallel Serial Adder Adder 2 s_serial_center2
Mean EE
s_ee_fifo_wen2
s_ee_fifo_wen3
EE FF 3
s_serial_data3 Serial Adder 3 s_serial_center3
s_ee_fifo_wen4
EE FF 4
s_serial_data4 Serial Adder 4 s_serial_center4
EEfifo_REN
s_serial_center0 s_serial_center1 s_serial_center2 s_serial_center3 s_serial_center4
EE Filter
EE_Data_Out
Center
MUX
EECenter_Sel
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Serial Adde r Bloc k Diag ram
s_ee_fifo_data0
Latch
s_Data_A
Adder
s_Adder_out1
Latch s_Data_B
Adder Latch
s_Data_C
Adder Latch
s_Adder_out3
s_Adder_out2
s_Serial_data0
s_Data_D
Latch s_Data_E
s_Data_C
Adder
Latchs_Data_E_1d Latch
Latch
s_Data_C_1d
Latch
s_Data_E_2d
s_Data_C_1d
s_Serial_center0 Latch
Above Block diagram show serial adder part of Edge enhance. For serial adding, delay 2
add ing
Input signal by latch. And make output sustenance of latency serial center of Serial Adder.
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Parallel Adder s_Serial_data0
Adder
s_Adder_out1
s_Serial_data1
Adder
s_Adder_out3
s_Serial_data2
Adder
s_Adder_out2
s_Parallel_mean_data
s_Serial_data3
s_Serial_data4
Adder
Latch
s_Serial_data4_1d
Latch
s_Serial_data4_2d
th
For parallel adder, delay 2 adding each Input signal by latch. And last adding 5
sustenance of
latency. EE Filter
InputOrg
Sub
s_Sub_out
s_mult_out
Adder
s_add_out
Saturation
s_sat_out
InputMean
D_Alpha Latch_6d s_mean_6d EE filter process using final output of parallel and final output of Center data Last, B out FIFO and M Out FIFO uses for reading Data as signal of FM_se and Loop_se from VM part. Video Manager will be process data from signal of FM_se and Loop_se Service Ma nual
.
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3) V/M PART (1) Concept of VM. ?? VGA
clock
:
clock
?? Image
Grabber
?? VCR
In
8bit ?? VCR
:
:
and
(2) VM
25Mhz
Using
and
by
But
and
Using
NTSC
x
256K
x
480
640
32bit
x
x
480
2bank(KM41
after by KM0127 transformat
memory. /
type
VCR
640
standard
video nd signal using
field
to
expression
type.
:
input
AL422 VGA
stand ard
25Mhz
Memory
Using
VCR
monitor
:
Receiving
format
out
?? VGA
PAL
:
converter
VGA
chip(AL4 22)
expression
input/output laced type. is
is
Non
inter
Inte
Function
?? Executing after
Keying
making
receiving ?? Also
it
8bit ?? It
by
the
640
Block
Video
IN
input
data,
control
function
480
to
to
receive
/
function
display
x
image
Interlace
the
Post
Memory,
(3)
VCR
has
has
VGA
VCR
Using
?? Image
Non and
to
FPGA that
display
save
and
DSC
Post
does
DT
and
DSC
Image
it
after data
It
d ha
Decoding
in
Imag
Map.
(It MUX
DATA
in
with displays VG
grabber
image to
monito
signal)
Manager Scan
Video
Converter
Input
Image
Image
(I-->NI) Grabber
Field (KS0127) Memory
Image
(SDRAM)
FIFO
640*480(1HS:37us)
MemCtr) Post Map
Filing
Acq
BW_SD[0..7]
-->640*480(1HS
Mode Image Grabber
Converter Ctr
(Field Memory)
VGA[0..7] R:5
NI
G:6 B:5
Video Key
Post
Control
FPGA
Video DAC
Video
(VGA
Out
Monitor)
(BT121)
Scan Converter Video (NI->I) Field
DAC (BT121)
Memory
Service Ma nual
VGA
Diagram
Decoder
(from
and
si gnal.
input
saved
monitor data. after
signal
from
Interlace
Published by C ustomer Servic e Depa rtment
Sec tion 2-3. DSC Board
(4) Function o f each part ¨ç
VIDEO & IMAGE PART SA9900 can display 800 x 600 full si ze at monitor. But ultrasound imag
e expression zone
is just 640 x 480 size. Also this part can display external input such as VCR input. SA6000II can display 640 x 480 size with ultrasound image, VCR input and VGA data 640 64
512
32
480
Below picture is real image format of SA6
Service Ma nual
000II
Published by C ustomer Servic e Depa rtment
Sec tion 2-3. DSC Board
¨ è VCR INPUT An al og ue vi de o si gn al (V HS , S - VHS) to be tran smit ted fr om VCR is TV si gn al an d Interlace type signal. And TV image signal is divided NTSC, PAL and SECAM type by character of each r egion. So, it uses e xclusive usin g chip like One chip fr o
nt
end(KS0127) to process each different input data, and executes A/D conversion in the inside. And it makes UV/Y format from input analogue video signal by internal Chrominance circuit and Luminance circuit. And it transmits to be changed data.
¨ é B,M I NPUT (DSC INPUT) In imag e part, B - mode image and M
- mod e dat a to b e tra nsm itt ed fr om D SC bo ard
transmit to Post control. In this part, it transmits input signal according mode(B, M) to Post map after separating signal. ( V/M part ou tput /IMGH S, /IM GVS, IM
GdotClk, /FM_se, FM_sc , /Loop_s e, Loop_s c to
DSC part) Post control use P ost FPGA (SC2S100 - FG256)
¨ ê IMAGE GRABBER Real image signal and VCR signal is saved in Image grabber and image grabber data works to make Vide o signal a fter transmitting to Output FIFO
. Also, it works to
transmitting image of image grabber to main PC or receiving that. SDRAM clock using 50Mhz. Reason is save and output at /HS 1 circle at same time. Image Grabber memory using KM4132G512(256K x 32bit x 2bank) and clock is 50Mhz. It store d 512 COLUMN to under ROW and stored 128 CO LUMN to upper A bank. This is storage B - mode. Gray bar area is 0~39 and Image size is 512 so, Start 1 is 40 end 1 = 512 and Start 2 is 0 end 39. But real input end2 is 128. left area : start 1=40 end 1=295 start 2=
0 end 2=0
right area : start 1=296 end 1=511 start 2=0 end 2=40
Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-3. DSC Board 512 256 A bank
B bank
512
1024
¨ ë FIELD MEMORY It has to transform the signal after matching synchronism with Sync to display at VGA monitor. Field memory works this function. And Field memory uses AL
422 and supports
suitabl e resolution to use VGA and TV signal. It is set for s ynchronize signal. AL422 is 3M - bits FIFO field memory and it is possible to operate each read/write. ¨ì
VIDEO KEY Image/VCR signal of 640 x 480 size to be
transmitted from field memory is displayed at
monitor in 640 x 480 si ze with overlay or other Menu signal. In this time, it is the part to do MUX with VGA signal.
¨í
NON- INTERLACE DAC Digital BW signal to be exe cuted Keying is transmitted to VGA monitor after changin g into Analogue BW through Video DAC(BT 121).
¨î
INTERLACE Output It is necessary output signal to display at Echo printer or Interlace monitor separately VGA signal, and it uses chip AL442. Also it is
necessary field memory to display 640 x 480
size of Interlace sync. Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-3. DSC Board
3.4 DSP d escription
3.4.1 DSC DSP 1) DSC DSP ?? DSC
DSP
and
?? It
controls
various
also
interr pt
memory
kinds
controls before
of
the
controller
frame
signal
sending
data
and
memory,
in/out
line
path
of
from
input
DSC
board SSRAM
to
interpolation.
3.4.2 RTC DSP 1) Functions of RTC DSP ?? HOST
Interface
-
Receiving the cycle of PRF, EADC, XSYNC, EDFDLY sync from host.
-
Sends the condition of RTC FPGA and sequence to ho
-
Receive the sequence of operation of each mode.
-
Receiving operation sequence of each mode from host.
?? Sequence
Carries out sequence table and specific mode transmission.
-
Reads send data and register data is controlled by RTC FPGA
?? RTC
FPGA
st
Change
-
Contro
-
Post out to RTC FPGA various data.
-
Sets register of RTC FPGA by determined value.
RTC makes standard signal for whole system operation in real time and controls system operation. BF, DSP, P RF, O F, RP, Line t ype, scan line and M id_PRF, ATGC_PRF for MGA01
5 of D SP a re
made and controlled. In addition, it has the role of making signal to control data stream in the DSC board internally. RTC(Real time controller) makes standard signal for whole system operation in real time and controls system operation. It makes the various standard signals essential to system operation because PC is the main HOST and controls FPGA by DSP. Because these standard signal are used for whole system operation, it should be easy to control and op erated accor di ng to basic frequency.
RT C is
composed of DSP and RTC FPGA DSP part is commanded by HOST(PC) and carried out. Or
Service Ma nual
SSRAM
memory
Published by C ustomer Servic e Depa rtment
by
co
and
stan
vide
c
Sec tion 2-3. DSC Board
receives Sequence(operation order for each mode) at the form of table and makes progress. And controls cycle of each signal by register setting of FPGA. FPGA is comm
anded by DSP and ma kes
a real signal.
Below block diagram is RTC part.
Host Interface
61.6Mhz HSYNC VSYNC /BW_RDY
RTC-DSP (ADSP2183)
LNTYP RLNTYP Scanline /OF /RP /prf /ETRG SWEEPRATE xsync /MID_TRP /ATGC_PRF
RTC-FPGA (XC2S30-TQ144)
ATGC_INFO Fig1. Overall Structure of RTC
Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-3. DSC Board
2) Structure of RTC - DSP Below flow chart is RTC - DSP.
Variable Init.
Host command process No
PRF Interrupt ?
Ye s
Prf Process
Set Port Value
Port out to PLD
Set Next Sequence
Change Sequence Table
Flow chart of RTC-DSP
Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-3. DSC Board
This shows processing of f low receiving data and command from Host.
?? Command It
Proc ess
re eives
Command
will
be
the
command
from
part
is
RTC
is
receiving r port data out to f
3rd
part
it
the
the ?? Set
is
control
command
signal
for
occurred
controls
PRF
the
definition A.
There
DSP
generation RTC
part
FPGA
debugging
purpose.
that
is
proper
is
to
the
After state
value
part
to
checking change
x
_
e
x
i
st m
value
by
/EADC
per to
port
and
from be
assigns
/RP.
RTC
FPGA,
processed rred. scan
And
t
whe
line
and
prepare
to
each RTC
map
Mode
FPGA.
list
per
among from It
Host the
should
each
and tra
assign
PRF.
e
n
sy
a
b
transmit
the
n
l
c
_
f
l
a
the
assigned
value FPGA. from
the
Table simulation
g
form.
process.
m
PRF,
it
to
FPGA
Sequ ence
_
signal flow
occurred,
transfer
presented
Out
?? Change
of
/PRF data
Value
assigns
?? Port
by
overall
interrupt
frequency Port
preparing
each
diagram
PRF, sh ow
changing ea ch
tra n
1
i seq_Utable
e
e
State
of
Followin g
x
i
st
t i x e
t i e d _
seq_Mtable
Service Ma nual
and
Appendix
Process interrupt
IF
of
list.
part
If
HOST
list
2nd
part,
It
Data
1st
?? PRF
It
and
described DSP in command the RTC
seq_ table iagram
of
Sequence
Published by C ustomer Servic e Depa rtment
Tabl
Sec tion 2-3. DSC Board
3.4.3 RTC FPGA 1) RTC All commands are sent fro m RTC- DSP and are written at internal register. The function of each command is defined in port map
table. First, TPRT and XPRT must make reference signal. It
is
made by co unter MCLK(61.6Mhz). And all signals are made synchronous to MCLK.
2) Structure of RTC FPGA ?? DSP
interface
Data or
to
receive
from
DSP
write
data
that
it
will
send
t
Host.
?? PRF Xprt_n
makes
system
Xprt_n
makes
Tprf_n,
clock, PRF
PRT
period
blank
is
period
made
is
from
made
DSP
from
DS
?? sweep_rate ync x Makde It
is
sweep
made
?? MID_PRF
3)
,
ATGC_PRF
is
made
signal
It
is
exist
MID
DSP
signal
input
It
Belw they
rate
with
,
xsync and
signal
delay
value
from
Hsync
ATGC_INFO
needs
part
and
clock
in
MID DSC
processor(MGA015) board
and
make
by
RTC
FPGA.
Interface picture
store
register. movement
is
data
st ructure to
be
Therefore
is
part
transmitted
all
stabilized
of
to
internal match
to
recei ve
from
D SP.
data
And
when
MCLK
/PR F_ BL ANK_ CS /TPRF
TPRF GENERATION 16BIT CNT
PRF,
because
we
/XPRF_N
RPEN
DSP_D[15:0] LATCH /PRTCTRCS0
LATCH
FIREEN LSTPRF FSTPRF
/TPRF
DSP Inteface of RTC-FPGA
Service Ma nual
PRF
selected
/TPRF
XPRF GENERATION 16BIT CNT
DS c
registers th every are changed PRF. The s
DSP_D[15:0] /PRF_WIDTH_CS
from
Published by C ustomer Servic e Depa rtment
th
Sec tion 2-3. DSC Board
4) PRF
61.6MHz 20.53MHz =MCLK prf period
/tprf
prf blank
prf blank
/xprf
Firing Start
eof_n etrg_delay
/etrg_dy focusing start
/prf eadc enable
/eadc
eadc delay Timing Diagram of Main Signal Picture 20
Above picture show timing relation of PRF and EADC to be main signal. First, receiving sy clock of 61.6Mhz and making MCLK(master clock) of 20.53Mhz to divide
stem
it by 3. It determines
reference clock of RTC FPGA. It makes reference /tprf and /xprf according to PRF period value to be transmitted from MCLK and DSP. And it makes /etrg_dy to be
delayed as setting value in
ETRG- delay register to /prf of system. So, make /eadc signal.
3.5 Checking issue of each function
(1) Check mode image : B mode , Dual B , B
- M left/right , B - M top/down , Depth Change,
128ch mode (2) Cine , Loop operation : cine fast
256frams, density 128frams, Loop 4096 lines
(3) Check save of cine memor y : Using debug menu (4) Check save of VM Image : Using debug menu (5) Check of External VGA Monitor, check Echo Printer, VCR recording /
Playing, PAL/NTSC
(6) Check Probes : convex and Linear
Service Ma nual
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Sec tion 2-4. Key Interface & Matrix
4. Key Interface & Matrix
4.1 Key Interface & Matrix
const ructi on and function
SA6000II KI/M is consists of two parts with one board. One part is Key Interface that supports UI and the other part is Alpha Numeric Key. The Key Interface Part that 89C51 t
ake the lead in the work and Alpha Num
eric Key Part that
HT82K28A take the lead in the work . The Key Int erface Part that 89C51 take the lead in the wor k through MAX239 The Key Interface Part that 89C51 take the lead in the work through MAX239 / through Ser ial Port of 89C 51 MAX 239(RS - 232C Inte rface)/ to the side of PC B/D and COM2( T/B ),COM3( System Key )/ as Serial / Data exchange. Alpha Numeric Key Part that HT82K28A
take the lead in the work HT82K28A have itself Serial Port
and by it through MAX239(RS- 232C Interface) Alpha Numeric Key Part pass the key value to PC. HT82K28A have itself Serial Port and by it. And, SA6000II Key Interface & Matrix / is consists of each ke ys to appl y Multi - langua ge/e ach keys/ as Ma cro Key (one Key has va lue of many keys and key S/Ws are consists of pushing key pad and
attach a point of contact to
key pad / send
electric curre nt into part again /form to work/ not push - button .
Diagram1. SA6000I I KIM Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
4.2 Block Diagram & Description
+3.3V TTXA,B Track Ball
TTYA,B
SR[8..15] Key contol CPLD
TBR,TBL
XC9572X L-TQ100
SC[0..7]
] 7 .. 0 [ A S
TGC Volume
ADC 0808
Key Matrix
Power Control Signal ] 7 .. 0 [ A T A D
] .7 . 0 [ D S
Track Ball & Key Power Control Foot s/w Alpha Nemuric Key
SD[0..7] uP 89c51
+5VA
Connector
TXD,RXD
DATA[0..7]
UART 8250
RS-232C MAX239 MSOUT
POWER +5V , +12V
KEY INTERFACE PART
Diag ram 2. S A600 0II KEY INT ERFA CE P ART Bloc k Diagr am Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
PC_KEY_DATA
PC_KEY_CLK
From:PC
To :PC
HT82K28A C[0..7]
Alpha Numeric Key Matrix
R[0..17]
Alpha Numeric Key Part Diagram 3. SA6000II Alpha Numeric PART Block Diagram
Above diagram 1,2 shows Block Diagram about SA6000II Key Interface & Matrix At first, we will explain about Key Interface Part. As you see the BD , Ke y In terfac e Pa rt 89 C51 take the le ad in the work an d it
co nsis t of Ke y
Interface Controller ( CPLD),ADC0808,82C50,MAX239. Key Interface discharges as followi ngs. ¨ ç Track Ball Counter ¨ è Key Button( Scan ) ¨ é TGC Volume Control ¨ ê Power Control ¨ ë PC to Key Panel Communication
4.2.1 Track Ball Counter ( A phase ) Clock ( B phase ) Up/Down Clear
8 Bit Counter
cnt_data[7..0]
cpu_data [7..0]
Try State 8Bit Buffer /RD
TRACK BALL PART
Diagram 4. Track ball part
Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
A direction in A, B direction to input from X,Y
axis of Track Ball.
According to the condition of direction B, fix Up/Down of counter. At this time, data is converted into a form of 2
¡complement ¯ and transmit to Main. (
a high positio n
bit is Direction )
A Phase B Phase
ClockWise
A Phase B Phase
CounterClockWise
Diagram 5. T/B wave form ( direction relation )
4.2.2 Key Button( Scan ) Key Button is constructed as and (for reference, Map ) send Scan Line (SR8 ~15) that is on ROW side signal in order and is input Column side decodes D ata (SC0~7) and interpr et to in put existence and nonexistence of each Button. At this time if the value of SC is not FF, interpret
that Data is input and go on next work.
# Key map
SC6 SR8
SC5
ID
SC4
SC3
END
SC2
SC1
PROBE
I/F
SAVE
SC0
EXAM SR9 SR10
USER1
USER2
SR11
USER3
USER4
SR12
USER5
REPORT
MENU
SETUP
APPL.
BODY
INDICATOR
BODY CLR
CALIPER MEASURE
CHANGE
DOCUMENT
MEA.CLR
DOC.CLR
SR13 DEPTH+
DEPTH-
SPEED
HARMONIC
FREQ.
FOOTSWA
SR14
ZOOM-
DIRECTION
B
M
FOOTSWB
APEX
B/B
3D
FREEZE
ZOOM+
SR15 FOCUS + FOCUS-
Table 1. Key Matrix Map
Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
# Between Track Ball& Key Button and PC of transmitting and receiving connect to COM Port of (MAX239 ) PC through RS - 232 Level. Port
Setting
Usage
COM 2
0x2F8 / IRQ 15
Track Ball
0x3F8 / IRQ 14
Key Panel
COM 3
Table 2. COM Port 4.2.3 TGC Volume Control It is use 50K ? Σλιδε ςΡ, α χχουντσ αν δ σενδ ω ιτη Α/ ∆ Χονϖ ερτερ (Α∆Χ0808) ποτεντι αλ βοτη ενδσ οφ ςΡ (ΓΝ∆ ∼ +5ςΑ)
διφφερενχ ε οφ
. ςΡ νυµβερ το υσε ισ 7πχσ.
4.2.4 Power Control PC_DOWN
POWER_DOWN CPLD XC9572
Power
PC
PC_ON_OFF
POWER_ON_OFF Power Control Diagram 6. Pow er Control
Key Panel observes POWER_DOWN signal that is input from Power and when Power Switch is off ( Low
?
High
PCIO
that
this
after
it
is f let PC
senses
time)
After
)
Key
and
it
it
Panel
know. PCIO
complete
is
let
Key
observes
2seconds let it Power i
to
practice
Panel
PC_ON_OFF
know
that
it
all
Windows
Program
know. signal is
that
receive
fr
OFF.
4.2.5 PC to Key Panel Communication ?? - Track
>
Serial
1200 Bit st word 1
No
bps
Ball
Mouse ,
non
6
:
transmit
Data
by
82C50.
Mode parity
5
,
4
1
stop
3
7bit 2
data
length
1
0
1
L
R
Y7
Y6
X7
X6
nd word 2
0
X5
X4
X3
X2
X1
X0
rd word 3
0
Y5
Button status
Y4
:
1
=
Table
Service Ma nual
Y3 pressed, 3.
Y2 0
Track
=
Y1
Y0
released
Ball
Serial
Data
Construction
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
> Initial Tim ing
Diagram 7. Ser ial Ti ming ?? Transmit
Next,
Alpha
we
will
IC
Key
Win98
is
by
consists
transmit
Key
Map
as
C7
R1 R2
F5 /1 @/2
discharges
of
values
R0
abo Numeric
Keyboard
Key
is
Serial in 89C51. port with
explain t Alpha
Numeric
Standard
This
Data
Row in
is
Key
Part.
General
the
PC
Key
exclusive
18bit,
PC
built
Column
side.
Board HT82K28A functi is
use
8bit
of
as
followings.
C6
C5
C4
C3
C2
C1
C0
L-RL
PAUSE
~/`
Z
F1
X
A
TAB
S
%/5
B
V
G
F
T
R
R5
&/7
^/6
N
M
H
J
Y
U
+/=
,
F8
APP
_/
?//
F9
F12
R11
DEL
D-
R12
INSERTR-
R8
)/0
R9
PRINT
R10
F10
F4
F6
D
M
#/3
(/9
C
Q
CAPLOCK
$/4
*/8
F2
ESC
R3
R6
Matrix ey Map form
(Serial ompounding of communication) Row and Column. by
R4
R7
IC.
K
>/.
R-LT
}/] L
¡°¯
F3
:/;
F7 {/[
L-LT ENTER
F11
E
I O P SCRLOCK
|/
BACKS
NUMLOCK SPACE
ARROW
ARROW R13
PGDN
P GUP
R14
END
HOME
L-
U-
ARROW
ARROW
R15
R-HT Diagram
Service Ma nual
5.
Alpha
L-HT
Numeric
Key
Map
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
4.3 Key Main program Description
Following is a description of Main program.
START
initialize 89C51 Main Loop Start
TrackBall Event
yes
Key Button Event
yes
scan_trackball
scan_button_ matrix
yes TGC Event
Di a
scan_tgc
Shutdown Event
yes
manage_system_ power
Command Event
yes
process_ command
gram 8.Key Main S/W Flowchart
First, main S/W Flowchart show 89C51 doing early time setting and each parameter initializing as soon as system start. Second, Main loop run, sensing the event flag and call it. SA6000II use fo llowing 5 eve nts.
Service Ma nual
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Sec tion 2-4. Key Interface & Matrix
¨ ç Track ball ¨ è Key button ¨é
TGC
¨ ê Power (shutdown) ¨ë
Command
If this five event flag is sensed, call the subroutine and return to main loop.
4.4 Dat a sheet
The following data sheet is important IC used for SA6000II Key Interface & M atrix.
4.4.1 CPLD XC9572XL-TQ100 Pin Description
75
51
76
50
XILINX
R
XC9572XLTQ100
10 0
26 1
Service Ma nual
25
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
Pin Name
Pin NO
I/O
Description
P2_6
20
I
/RD
25
I
CPU READ
/WR
23
I
CPU WRITE
/RESET
13
I
PLD RESET
ALE
12
1
ADDRESS LATCH ENABLE
XCLK
22
I
SYSTEM CLOCK(11.0592MHz)
PC_ON_OFF POWER_DOWN
28 29
I I
PC ON/OFF SIGNAL POWER SWITCH OFF SIGNAL
/EOC0
18
I
A/D CONVERTER END FLAG
PADCSTT_1D_I
36
I
A/D CONVERTOR START_1D_I
PADCSTT_2D_I
33
I
A/D CONVERTOR START_2D_I
TTXA
14
I
TRACK BALL X AXIS A PHASE
TTXB
15
I
TRACK BALL X AXIS B PHASE
TTYA
16
I
TRACK BALL Y AXIS A PHASE
TTYB
17
I
TRACK BALL Y AXIS B PHASE
TBL
32
I
TRACK BALL LEFT BUTTON
TBR
30
I
TRACK BALL RIGHT BUTTON
D [0..7]
1,3,4,6,8,9,10,11
I/O
CPU DATA
SA [0..5]
93,94,95,96,97,99
I
SCAN ADDRESS
SC [0..7]
82,85,85,87,89,90,91,92
I
SCAN COLUME DATA
SD [0..7]
64,63,61,60,59,58,56,55
O
SCAN DATA
SR [8..15]
74,72,71,70,68,67,66,65
O
SCAN LINE SELECT
A[0..2]
42,41,40
O
CPU ADDRESS
FRZLED
81
O
FREEZE LED ON
/FRZLED
79
O
UNFREEZE LED ON
SVO_6
53
O
A/D CONVERTOR OE
PADCSTT
37
O
A/D CONVERTOR ALE
PADCSTT_2D
52
O
A/D CONVERTOR START
PADCSTT_1D_O
35
O
A/D CONVERTOR START_1D_O
/8250CS
39
O
8250 CHIP SELECT
PC_DOWN
50
O
PC OFF SIGNAL
POWER_ON_OFF 49
O
POWER ON/OFF SIGNAL
RESET
77
O
CPU RESET
/TMRINT
78
O
TGC INTERRUT
ADCLK
54
O
ADC0808 CLOCK
Service Ma nual
SCAN COLUME DIRECTION
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
4.4.2 MAX239 ( RS-232C )
The function of this part is to convert normal signal into RS
Service Ma nual
- 232C Serial.
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
4.4.3 8250 ( UART )
#Pin Description
# Cl oc k : 1.8 43 2 Mh z
Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
4.4.4 A/D Converter ( ADC0808 )
# Pin Description
Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-4. Key Interface & Matrix
4.4.5 Alpha Numeric Key Controller ( HT82K28A )
Service Ma nual
Published by C ustomer Servic e Depa rtment
Sec tion 2-5. Rear Boa rd .
5.REARBOARD
The function of th is boa rd is t o communicate with sub
- apparatus. ( Ech o printer, Line printer, LAN,
USB, RS- 232C,Vid eo,VGA Monitor , Main Monitor, Foot SW) and composed of PCB and various Connector. It doesn ¡ t¯have internal c ircuit Logic. Rear B/D is connected with BNC, Foot SW and Cable at Rear Panel.
5.1 Rear B/D Configuration Diagram
J3
Serial Port (RS-232C)
JP3
P1
Pararell Port (Printer)
JP2
USB
JP1
LAN (DICOM)
J2
VGA (External)
J4
Service Ma nual
Echo Printer Remote Jack
Published by C ustomer Servic e Depa rtment
Sec tion 2-5. Rear Boa rd .
5.2 Rear Pa nel Configuration D iagram
Monitor
Echo Printer
RS 232C
P a r a r e l l
Video out
USB Video in
LAN
Foot SW VGA
E.P Jack
Service Ma nual
Published by C ustomer Servic e Depa rtment
Section 2-6. PC Board. 6. PC BOARD 6.1 Introd uction
6.1.1 External PC board There has IO and bus as like general PC main boards. It is just
different that ethenet card and
VGA card mount on this board.
6.1.2 PART OF PC ?? SYSTEM
?? USER
&
CONTROL.
PERIPERAL
INTERFACE
?? VGA
6.1.3 DESIGN CONCEPT (SPEC) 1) BASIC DESIGN CONCEPT
Service Ma nual
Published by C ustomer Servic e Department
Section 2-6. PC Board. ?? Low
Cost
?? High
System
Performance mbedded for Application
?? Simply
Design
?? Supply
the
?? Can
be
interface
use
various
for
using
easily
Application
2) Memory
?? Main
Memory
?? Minimum
16Mbyte,
?? Fa t
SDRAM
?? Use
1
?? Flash
3) Supply
(SDRAM)
(PC
DIMM
ROM
:
256Mbytes
133)
Socket
512K
internal
4) External
Max
(Service gradable man
x
PCI
16bit,
bus/ISA
peripheral
up
3.3V
bus
connection
supply
Serial,
Parallel
5) VIDEO
?? Basic
resolution:
640
x
480,
Color
24bit
mode
operation
6) Storage
?? 2
EID Connector
?? Extendable
6.2
General
4
for
Hard
HDD
disk
Description
6.2.1 H/W 1)
PC specification Parameter
Specification
Remark
Processor
Strong ARM (RISC processor)
SA110 (21281 - EB)
OS
Linux
Kernel 2.4.3 - rmk1
Memory
64MB (DIMM)
64, 128, 256MB
VRAM
1M x 16 Dynamic EDO RAM
IS41C16100
Hard drive
20GB
Quantum
VGA
640*480 color 16bit
CHIPS F65550
Service Ma nual
Published by C ustomer Servic e Department
Section 2-6. PC Board. ROM
512K*16bit (1MB)
Power
+3, +5, +12,
Flash ROM
- 12V
Network Interfac e
Ethenet 10/ 100 ba se TX
Fast ethernet c ard
Serial
RS - 232C
DB - 9 Conne ctor
Pa rallel
Standa rd EPP, EC P c ompa tibleness
DB - 25 C onnector
Keyboa rd
86/ 103 keyboard
6pin DIN co nnec tor(PS2)
Mouse
PS/ 2 Mouse
6pin DIN connector (PS2)
IDE po rt
4 HDD suppo rt
LCD
16bpp
Using only Signal
2) Block diagram
Flash ROM
168pin DIMM
39VF800A
SDRAM
CP U
North Bridge
SA110
SYSTEM BUS 50MHz
21285
COM0
PCI BUS 33MHz SouthBridge
Ethernet
VIA82C686A - 2 Serial ports - PS/2 - 1 Parrallel port - 2 USB ports - RTC - 2 IDE controller
VGA
RTL8139
- 10/100B T, 1 RJ45 port
F65550
PCItoISABridge
PLX9054
- 256K*16*2 VRAM
PC ¿Üº Î bus
S U B A IS , T O L S N IO S N E P X E
DSC
RX
BEAM
In g eneral P
C, PCI bus
¡¯s function of network and VGA mount on CPU board as slot
case, each function chip is built
Service Ma nual
. But, in this
- in of PCI bus on Board.
Published by C ustomer Servic e Department
Section 2-6. PC Board. 3)
CPU
?? Intel
?? Core
?? It
strong
ARM
clock:
is
useful
SA110:
Hi gh
performance
I/O
?? It
has
slow,
for
power tion. consum That
is
clock
bus
management
of
as
instruction
unit
general point Pentium operation PC. is
(MMU)
cache
and
support
16KB
virtual
wri te
back
memory
data
– low power consumption ideal for power sensitive app
microsecon interrupt
response time
?? Excellent level high language
and
Little
1149.1
?? 144pin
Service Ma nual
valu
’t feel hot.
operation
sub
?? IEEE
’t
calorific
buffer
?? Static
?? Big
like
say,
– enhancing performance
?? Write
?? Fast
and
to
B v
because as no it FPU.
?? Memory
?? 16KB
processor
233MHz
need cooler, and if u sers touch it when it is running, user doesn ?? 3V
RISC
TQFP
endian
support
operating
boundary
for application real
mode
scan
package
Published by C ustomer Servic e Department
sy
cac
Section 2-6. PC Board. SA - 110 micropr oc essor is gener al pu rposes micropr oc essor. It is one chi p th at is a bu 16KB instruction ca che, 16KB write b ac k data c ac he, 8
ilt- in
- entry write b uffer with 16 bytes per entry, and
memory management unit (MM U). SA - 110 play a role A RM V 4 arc hitec ture p roc essor family and software c ompa tible, and it c an b e use with ARM support c hip for I/O, memor y and video . On - chip Ca che c an be rise exec ution speed with write buffer, and to red uc e a verage memory ba ndwidth req uested b y proc essor. Ab ove things make possible to use external memory for supplying ad ditional proc essor and direc t memo (DMA ). This instruc tion c a n be use for
ry ac c ess
assessing memory mana geme nt, c onfiguration, and ca c he
cont rol register. SA - 110 have 1 6KB instructi on cac he ( lca che) by 32
- byt e block and 3 2 - way
associatively . Lc a c he supports flush - all- entry function. The I c ac he enab les when memory mana gement is disab le. If Me mory manag ement disab les, all memory wa s cac hea ble b y Ic ac he. And , SA - 110 have 16KB data c ac he (Dca che) by 3 2 - byte block and 32 - way associat ively . Dca c he suppli ed fl ush - all, flush - entry, and c opyba c k- entry function. But, in c ase of co py ba c k- entry, it supplied b y software. Not hardwa re. Strong ARM has 8 type of ba sic instruction. 4)
North Bridge
?? Exclusive
PCI
?? Substantial
?? PCI
?? Flash
Service Ma nual
all
bridge
?? SDRAM
bridge
device
(PCI
for
SA110:
21285
control
revision interface: 2.1 complian 32bit,
33MHz)
interface
ROM
interface
Published by C ustomer Servic e Department
Section 2-6. PC Board. ?? DMA
controllers
?? Serial
port
?? Interrupt
?? PCI
bus
?? IEEE
(For
debugging)
controller
Arbiter
1149.1
?? 21285
COM0,
contr ol
Debugging.
boundary
all
scan
device
But,
It
is
of
and
PC
big
JEDEC
board
include the
problem that ’t check all pins cause of BGA type. it
point CPU.
can
5) South Bridge
?? Supply
all
peripheral
interface
?? US B
?? 2
Serial
?? Primary
ports
and
?? Parallel
Secondary
IDE
port
?? RTC
?? Keyboard/Mouse
?? Power
?? Floppy
?? AC97
Service Ma nual
monitor
disk
link
(Usentrol) for reset
(Not
(Not
c
use)
use)
Published by C ustomer Servic e Department
ofT
Section 2-6. PC Board. 6) VGA
?? Flat
panel
?? 640X480
?? NTSC
?? YUV
/
/
?? System
/
CRT
GUI
Accelerator:
CHIPS
F65550
16bpp
PAL
RGB
support
output
used
only
digital
RGB,
and
send
digital
RGB
data.
?? F65550 : 1M
X
16
EDO
/
RAM(IS41 C16100 )
used
2ea
MONITOR
640*480
Whole
VGA
FORMAT
DSC MUXIMAGE
Displays
DATA
All DISPLAY
TRANSMIT TO
EXCEPT PC IMAGE
DSC BOARD ONLY RXIMAGE
Service Ma nual
Published by C ustomer Servic e Department
to
DS
Section 2-6. PC Board. 7) Ethernet
?? Fast thern controller: et
?? Complaint
PCI
RTL8139
Revision
2.2
?? 10/100B TX
?? Use
93C46
ROM
for
?? Mac(Media and
data
giving
appointing
Mac
Access trol) Co address
structure
specific
:
It
through
number
address
find
this
each
specified
address.
system.
It
port,
It
was
is
po
managed
802.2. ?? Mediso n ?? 00 ?? XX
05 XX
?? FF ?? 00
Mac
B2
XX
FF
00
00
–address Received address officially from Medison XX
XX
defined ~
00
?? Shipped ¨çMac
XX
FF ~
FF
system
as
FF
belo w.
FF
FE
has
:
FF
sh ipped MAC
only
for
R&D.
system address
correspond enc
addr ss generation
makes
¨é Remark
Service Ma nual
:
system
exclusive
mac_generate.exe ¨è It
The
system
making
to
:
Mac
write
date
and
mac
address address
serial
generation on
ROM.
number
Published by C ustomer Servic e Department
prog
Section 2-6. PC Board. 8)
PC I - ISA bridge
?? PCI
I/O
accelerator:
?? PCI
dual
address
?? Two
independent
?? Use
for
?? DSC,
?? ISA
?? Why
??SA
PCI
RX,
bus
to
system
is
bus
than
Service Ma nual
bridge
use
with
can
control
and
interface
between
each
bus) – It16bit is slower than PCI bus.
very
proramme r PCI
ISA
(DAC)
channe
Beamformer
this
bus
cycle
DMA
(16MHz,
PLX9054
ISA
bus.
useful same
change
for
programmer.
ontrolled Because, by
SA
address. ¯address And, each is always device same. the
address
with
using
virtual
ISA.
Published by C ustomer Servic e Department
ad
Section 2-6. PC Board. 9)
Flash ROM
?? 512K
X
?? Supply
?? Boot
?? ROM
??
16
flash
ROM
:
Use
SST39VF800A
ROM
file
BIOS
Service Ma nual
purpose
JEDEC dard sta
lode
??
multi
:
In
the
Kernel
the
Linux
:
early
Booting,
Kernel
on
It
can
be
initialize
system.
Linux rmk1 kernel is go 2.4.3 to RAM
after
BIOS.
Published by C ustomer Servic e Department
Section 2-6. PC Board. 10)
Loc k source
33MHz SA110 U8
33MHz
OSC 3.68MHz
33MHz 21285
U2
U43 ICS9169M
33MHz
OSC 50.0MHz
33MHz PLX9054
X2
OSC 48.0MHz
Y2 VIA82C686
X3
RTC
XTAL 14.31MHz
OSC 14.3MHz
Y3 XTAL 32.68KHz
F65550 X1
Y4
OSC 14.3MHz
XTAL 32.68KHz Y5
RTL8139 XTAL 25.00KHz
?? Theyave
clock
generator
?? Although
ICS9169M
?? Y3
(Rea l
is
power
?? U2
RTC
turn
supply
mentioned
Service Ma nual
Time
off,ery it
system
is
bus
33,
at
need
66,
Clock).
except
48MHz
When
PCI
frequency
power
turn
clock/33M
generator
on,
it
t
takes voltage. bat
CPU clock. -ort h RAM bridg e
inter face
b etween
clock.
Published by C ustomer Servic e Department
e
Section 2-6. PC Board. 11)
C loc k source Analysis Below table is type of clock for Ma in Board. Name
Source
Frequenc y
Remark
SA - 110
Oscillator
3.6864Mhz
+3.3V
DC212 85
Oscillator
50Mhz
Me mory cloc k
PC I_C LK_21285
33Mhz
PCI clock
PCI_CLK_VGA
33Mhz
PCI clock
Oscillator
14.318Mhz
Me mory cloc k
C rystal
32.768Khz
PCI_CLK1
33Mhz
Crystal
25Mhz
PCI9054
PCI_CLK2
33Mhz
PCI clock
VT82C 686A
PCI_CLK0
33Mhz
PCI clock
C rystal
14.318Mhz
RTC
Oscillator
48Mhz
USB
Oscillator
32.768Mhz
C T65550
RTL8139C
?? PCI
CLOCK
?? It
is
SOURCE
Clock
Generator
(14.318Mhz). Damping
?? PCI
PCI clock
In
Register
for
that
making
time,
(RN96,
33Mhz
tha
t
is
del
Each nected interface through ¯about 33R
RN98)
DEVICE
?? It
means
And,
PCI
each
Device
for
oscillator
is
S A6000II
System.
clock ystem(VIDEO for driving RAM,
A ll
4
ISA, sub
PCI USB
d e
Device.
??
SYSTEM
?? When er u And
uses
U2 ¯50
exert
a
MHz bad
U8, is
user
very
has
to
use110 3.3V. works Because, with 3.3V SA
important ¯North clock Bridge. as U1
influence
to
the
whole
system
If
U2
is
function,
Halt.
Referenc : User
must
use
at
lease
under
50PPM ach Crystal Device and detail Osci
below.
¨çStrong
?? CLK:
ARM
3.68Mhz
Clock.
Service Ma nual
And
Clock it
uses
input.
After
making
a
change
’s Oscillat or.asIf use 3.68Mhz 5.0V ’s OSC, CP U needs 3.3V
+3.3V
Published by C ustomer Servic e Department
23
Section 2-6. PC Board. case of Level c ha nge. ?? MCLK
:
48Mhz
MCLK.
¡Û
Not
Clock
Wait
Input,
21285 ving Output, BUS control 21285 the for
Cycle dr
Signal.
DC212 85
?? PCI_CLK
?? OSC
:
:
33Mhz
48Mhz
?? Generation. CLK :
?? FCLK_IN
:
Clock
Clock
Input,
48Mhz
48Mhz
Input
21285
Clock
Clock
from
Core
Output
input,
Clock
clock,
for
FCLK
Generator(CY2260)
FCLK,
MC LK,
sync
and
FCLK_IN
should
be
‘s MCLK Output is used to MCLK Input, in that time, happen to delay depend on PCB
?? 21285
Pattern Capacitance. 21285 g enera ted SD RAM ’ s Clock and Con trol Signal, in that time, It occur disc ord be tween CPU ’s SDRAM Ac cess Cyc le and 2128 5 ’s Clo ck and C ontrol Sign al case of mentioned delay. For preventing discord, the length that is from FCLK to FCLK_IN makes the same as length that is from 21285 ’s MCLK Ou tput to CPU ’s MCLK Input. ?? MC LK
: 8Mhz
Clock
output DCLKfor [3:0] CPU :
48Mhz
Clock
48Mhz
Clock
Output
Modules
¨é
DI M M
?? SDCLK[3:0]
¨ê
:
from
21285
VGA
?? PCI_CLK
?? OSC
:
?? XTAL
:
:
33Mhz
:
:
?? XTAL
:
Input
Clock
Clock
Input
Input
Clock CI to ISA Input Bridge
33Mhz
Clock
Clock
Crystal
Input
Input
SB_CLK Input
from
Clock
form
from
for
from
from
Generator,
Osc,
Clock
Video
Generator,
Clock
:
Generator
33Mhz
Clock
Input
Output
Clock
Clock
Clock,
for
Co
Syste
T 10/100Base
Generator,
Oscillator,
for : 48Mhz RTC
Syste
Timing
for
14.318Mhz
PCI
Syste
TC_CLK I/O Device :
Input
Generator
?? PCI_CLK
Service Ma nual
33Mhz
.318Mhz 1
?? 32.768Mhz
Clock
Clock
for .318Mhz 1
25Mhz
?? PCI_CLK
?? OSC
:
Use
?? PCI_CLK
¨ë
Input
Device,
Published by C ustomer Servic e Department
USB
Section 2-6. PC Board. 12) M emory a rchitecture ??
Main
It
is
Memory
basic
(SDRAM)
Memory
for
SA6000II
System.
When
this
memo
there.
?? Memory
?? DIMM
It
is
Type
Socket
¨ç21285
Map
21285
¨ê When
other
Power
+5,
power
?? Change
?? User
use
compo sed
Memory
for
is
SDRAM
DIMM
of
:
below
16,32,
64,128,256Mb
4artic le.
Map
CPU
Master,
Memory
Devices are mater xcept 21285,
Map
is
Memory
on Map
PCI is
Bus on
is
5V
used
to
must
+3.3, 12V from +12, Power
Service Ma nual
B
2V
to
FUSE
by
cas e
LM317
B/D
of
protecting
for
supplying
check ecause 2V output. It was
over
current
voltage
reflected
by
to
.
CPU
charact
Resistance.
?? +12V
PCI
part
?? Supplied
?? Each
is
General
¨è Memory
1ea
to
Map
¨é When
SDRAM(60Mh z)
:
possible
?? Memory
13)
:
–12V andis use for only serial communication.
Published by C ustomer Servic e Department
Section 2-6. PC Board.
1)
Linux
128 B/ W system be used Linux O S pro gra m so it is very
impo rtant know to pe c uliarity Linux
command. Basic c ommand C ommand describe
Linux
Dos / Window
Sea rch for direc tory
Ls
Dir
C hange direc tory
CD
CD
Ma ke to direc tory
Mkdir
MD
Remove
Rmdir
rm
Cp
co py
Co py 2) Mod ule ?? Powerman
:
?? iop480
ISA
:
?? hdd_info
?? ide csi
6.3
Booting
:
:
Shutdown
bus
process
read
Reading
/
write
serial
number
from
HDD
MO ver dr
Sequence
6.3.1 H/W booting Seque nce Power good signal is supplied to south bridge
Pic tur e 1.1.1 ?? Originally, delay
Pi cture 1.1.2 power
good
signal
chip(Pic.1.1.1)
generated
for
following
from
ATX
’ stabi lity an d
easiness of debugging.). Pic. 1.1.2 shows how power good signal moves into south bridge.
Service Ma nual
power,
reasons.(other
Published by C ustomer Servic e Department
Section 2-6. PC Board. 1) Reset This de als with the Globa l Reset of whole board(signa ls up to
¡°C PU¡±are reset). System Reset is
as followings. (1) Power O n Reset ISA Bridge does the monitoring Power State through POWER_GOOD Input Pin and drives PC I Reset (Low Ac tive) a nd RSTDRV (High Ac tive) when Pow er is Relea ses. RSTDRV is reversed by I
¡° On¡± , and finally
nverter and b ec omes RSTDRV_L (Ac tive Low). After
making DC21285 reset, put 21285 ready. By two times Inverter (delay), CPU comes to be reset. Befo re this stag e, other devices are a lrea dy reset (Ethernet, PLX, VG A, ISA) and wait for starting in CPU. C onside ring time, C PU is finally reset and oth er device s ca n start code at stable c ondition. (2) South bridge receives po wer good signal and transfers reset signals into north bridge, C PU, HDD. (3) 21285 makes chips at PCI bus reset after rec eiving reset signal. (4) Rea d comma nds from memory ad dress ¡°41000000H ¡±and prac tice. (5) Me mory initial (6) PCI bus initial (Device initial and ad dress mapping) (7) H/W op erating.
6.3.2 S/W booting Sequence 1)
When Power on, firstly BIOS have authority of control
2)
After BIOS is over, jump to Kernel
3)
Kernel decompress ?? Initialize
?? Call
POST (power on self test)
-
Memory CHE CKING
-
Address mapping of each device
-
Interrupt vector table
-
Page table
¡ ¯s start point.
and
Resister.
decompress_kernel
?? Increase
Service Ma nual
Stec
-
to 000 0x10 at
of
misc.c utomatically and decompressed
memory.
Published by C ustomer Servic e Department
?? From
this
point,
Section 2-6. PC Board. booting “Uncompressing Linux …message. OK, booting the
output
srcinal
kernel.” 4)
After this, Kernel from memory takes this function. ?? Kernel
’s operating for computer and provides basic many basic services with
is
essential
other opera ting par ts. Generally , Kernel o btains as followings. ¨ ç Input/Output process ¨ è Interrupt management. (All requests for Kernel ¡ s¯ ser vice.) ¨ é Scheduler. (Which program and order will use Kernel ¨ ê Supervisor. (After scheduler, give the
¡ ¯s management time. )
rights to use computer )
¨ ë Kernel also manage address room for memory and storage and give to all surrounding equipments and others.(Memory Manager). Kernel ¡ s¯ service requested by other operating parts and consecutive program interface, ?? Kernel has
5)
IDE
device
?? Linux
6)
path
HDD
file
?? Practice
??
6.4
PC
6.4.1
all
mount
needs
init
to
application
(MO,
mounting
start
module
Because
¡S ° ystem Call ¡ .±
HDD)
for
for
use
(Freeing
for
Kernel
H/W
use
of
of
HDD,
init
device
for
HDD
Floppy,
memory
CDROM.
212K)
system.
is
at der Bios, is not Boo t necessary Lo
(LILO).
DEBUGGING
CHECK
¨ç Check
Ex)
parts
Resistance
¨è After
¨é Check
Ex)
POINT
if
parts
insertion,
Power
Service Ma nual
correctly.
Short
&
Open
Check
setting
error. bo
¨ê After nsertion check
Ex)
connected
value, ¯ connection, Parts and Chips Condenser ¯polarity.
Jumper
System t
are
user.
power
source
of
board.
short
Published by C ustomer Servic e Department
Section 2-6. PC Board. ¨ë Power is supplied with boa rd. ¨ì
Check if each chip ¡¯s cloc k is generated c orrec tly.
¨í
C heck reset input.
Ex ) Check if eac h chip ¡¯s reset is input. ¨î
At this point, pow er is ap proved. If no er
ror, messag e ab out bo oting shows to debug po rt.
To see output of debut port, set other computer ¡¯ s serial port as baud rate = 38400, data bit = 8bit, No Parity, 1 Stop bit. After that, you can obtain exact message. If the message is broken or abnormal, sett ing proc ess abo ve should be chec ked. ¨ï
From this, think normal booting is done.
If the booting fails, check the followings. ?? Check
?? CE
&
ROM ¯Chip
OE
Enable
should
?? Check
8
?? Check
Serial
?? Power,
Controller
of
will
00xx
:
0000
:
0000
00xx
:
0000
00xx
:
0000
RAM
on
connecting
?? U3,
U4,
?? PCI
Device
?? SDRAM
?? U3
After
¨ñ Check
¨ò ISA
Service Ma nual
U5,
U4
U6
Device
on
into
debug
or
Short)
po rt
r board like and 10, err ram
check
Damp
this,
(Open
&
interface
is
not
e
Short).
check.
check
No.1
(100uF)
ram
(Open
Port
sho wn
pci_clk
is
checking
condenser
time.
board
RAM
Clock
and
Enable(OE).
(U53)
Resistance
Debug
be
00xx
When
Out
activ e ? 60nS) as Low at (about t he same 50
Condenser,
?? Message
and
data from line ROM.
?? Connection
¨ð Connect
be
(CE)
pin
ram
(RN
and
check
check
because
this
14)
will
output
from
21285(U
be Clock normal. is very During bad,
problem
is
caused
carefully.
check
Published by C ustomer Servic e Department
by
powe
Section 2-6. PC Board. ?? ISA
is
Mouse
¨óVGA
at ,
Device
Initialize
interior Serial
VT82C686
1,
and
Serial HDD1&2 2, .
interfac
e
Parallel And do the
with
exteri
initializati
chec k
VGA
Device,
F65550
(U54),
and
output
on
LCD
and
image,
?? Jumper
setting
check
?? Check
video ¯Open RAM
?? Check
Clock.
?? Check
Hsync,
?? VGA
¨ô Copy
Connector
Kernel
¨õ Practice
16 During
&
from
?? U100 ®Open
?? U100
U54.
ROM
to
RAM.
boot
by
Kernel
(U100)
input
of
check.
Kernel ¯operating,
?? Clock
Short.
,B Vsync, ¡¯output R,
Linux
17 Ethernet
(J10)
HDD.
is
done.
check.
check
&
Short
check.
opera ting After check power at on, least
Active,
Booting
10/100B)
should
be
one
of
LED1,
working.
6.4.2 Detail debugging 1) POWER (1) Power Source : ATX Power Supply Input (+12V, - 12V, +5V, - 5V, +3.3V, - 3.3V) (2) Useable Power +12, - 12V : serial communicatio n +5V : PCI Bus System +3.3V : PCI Device Power Source +2V : C PU Core Voltage Only (3) CHECK list before supply to power Before power - on, FUSE and each power ¡ s¯ GND, short with power check is needed. ¨ ç FUSE CHECK
Service Ma nual
Published by C ustomer Servic e Department
LED2,
Section 2-6. PC Board. fuse c he ck for F1, F2, F3, F4 ¨è GND SHORT CHECK about eac h of power # F 4(
- 12V) an d GND
# F1(3V) an d GND
# F3(12V) an d GN D
# F2(5V) an d GND
# L12(2V) an d GND
¨é Eac h power¡ s¯short chec k. Following is meas urement by mu l # F4 ( # F4(
- 12V), F3(12V)
# F4(
- 12V), L12(2V)
# F3( 12V) , L12(2V)
timeter. Check the power . - 12V), F2(+5V)
# F3(12V), F2(5V)
# F 2(5V) , F1(3V)
# F4(
- 12V), F1(3V)
# F3(12V), F1(3V)
# F2(5V) , L12(
2V)
# F 1(3.3V) , L12(2V) ¨ê POWER C HECK ( - 12V, 12V, 5V, 3V) After po wer- on, chec k the po wer is c orrec tly input by OSC ILLOSCO PE. F1, F2, F3, F4 chec k and c heck the same signal.
F4 signal
VCC_- 12V
F1 signal
VCC_ 3V
F3 signa l
F2 signal
VCC_ 12V
VCC_ 5V
< picture > ea ch powe r signal form
Service Ma nual
Published by C ustomer Servic e Department
Section 2-6. PC Board. ¨ë C PU Power chec k (2V) CPU¡¯s po wer should be
1.8 ~ 2.0V
from Regulator(SC 1117) ¡¯s No 2 PIN. So, C PU ca n
work normally. By me a suri
ng L12 with OSCILLOSCO PE, check the signals are as following.